JPS608653B2 - Distortion cancellation circuit - Google Patents

Distortion cancellation circuit

Info

Publication number
JPS608653B2
JPS608653B2 JP14685576A JP14685576A JPS608653B2 JP S608653 B2 JPS608653 B2 JP S608653B2 JP 14685576 A JP14685576 A JP 14685576A JP 14685576 A JP14685576 A JP 14685576A JP S608653 B2 JPS608653 B2 JP S608653B2
Authority
JP
Japan
Prior art keywords
amplifier
distortion
voltage
cancellation circuit
voltage transformer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14685576A
Other languages
Japanese (ja)
Other versions
JPS5370741A (en
Inventor
昇 常世
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14685576A priority Critical patent/JPS608653B2/en
Publication of JPS5370741A publication Critical patent/JPS5370741A/en
Publication of JPS608653B2 publication Critical patent/JPS608653B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3223Modifications of amplifiers to reduce non-linear distortion using feed-forward

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 本発明は例えば高周波の広帯域な中継器における増幅装
置の歪を除去する回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for removing distortion of an amplifier device in, for example, a high frequency broadband repeater.

高周波における広帯域増幅装置を作る場合増幅器の歪が
問題となる。
When creating a wideband amplification device for high frequencies, distortion of the amplifier becomes a problem.

2次歪は例えばプッシュプル増幅によって避けることが
できるが奇数次の歪は除去できない。
Second-order distortion can be avoided, for example, by push-pull amplification, but odd-order distortion cannot be removed.

所が例えば2つの周波数f,,f2の入力に対し増幅器
の3次歪による混変調が生じるとが,±f2,公2土f
・等の3次高調波成分が発生し、これは利用周波数帯域
内に入ってくる場合が起るので、特に増幅器の3次歪が
重大な問題となる。一般に周波数が高くない場合,歪の
小さい増幅器性を得るには負帰還回路が用いられるが、
周波数が高くなると位相まわりが大きくなり、周波数に
よっては発振してしまうので使用することができない。
For example, if cross-modulation occurs due to third-order distortion of the amplifier for inputs of two frequencies f, , f2, ±f2, public frequency f2,
Since third-order harmonic components such as . Generally, when the frequency is not high, a negative feedback circuit is used to obtain amplifier performance with low distortion.
As the frequency increases, the phase rotation becomes larger, and depending on the frequency, it may oscillate, making it unusable.

このような高周波領域ではフィードフオアード(fee
dfoward)増幅器が使用されるが、構成が複雑で
又遅延調整が面どうである欠点を有す。簡単なものとし
てはダイオードの非線形を利用して増幅の歪を相殺する
回路もあるが、相殺は不完全であり、2次歪が生じたり
する欠点がある。本発明は前述の欠点を除去し比較的簡
単な構成で特に重大な3次歪を相殺する回路を提供する
ことにあり、その目的は高周波入力信号を増幅する第1
の増幅器と、該第1の増幅器とともに前記高周波入力信
号が入力され、これを所定の比率で昇圧する電圧変成器
と、前記第1の増幅器と前記電圧変成器の出力を合成し
得られた出力信号が入力される、前記第1の増幅器と同
機の特性を有する第2の増幅器とを有する歪相殺回路に
よって実現することができる。
In such a high frequency region, the feedforward (fee
dforward) amplifiers are used, but they have the drawbacks of complex construction and inconvenient delay adjustment. As a simple circuit, there is a circuit that uses the nonlinearity of a diode to cancel the distortion of the amplification, but the cancellation is incomplete and has the disadvantage that second-order distortion occurs. SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit that eliminates the above-mentioned drawbacks and cancels particularly important third-order distortion with a relatively simple configuration.
an amplifier, a voltage transformer to which the high frequency input signal is input together with the first amplifier and boosts the signal at a predetermined ratio, and an output obtained by combining the outputs of the first amplifier and the voltage transformer. This can be realized by a distortion canceling circuit having a second amplifier having the same characteristics as the first amplifier to which a signal is input.

以下本発明を詳細に説明する。図は本発明による歪相殺
回路の1実施例であり、入力信号V,は増幅器101こ
よって増幅され出力電圧V2を出力し、又入力信号V,
は電圧変成器20にも与えられ、電圧がP倍され電圧玉
V,を出力し、出力電圧V2とpV,が合成されて電圧
V4として増幅器301こ入力され、電圧V5が得られ
る。
The present invention will be explained in detail below. The figure shows one embodiment of the distortion canceling circuit according to the present invention, in which the input signal V, is amplified by the amplifier 101 and outputs the output voltage V2, and the input signal V,
is also applied to the voltage transformer 20, and the voltage is multiplied by P to output a voltage ball V, and the output voltages V2 and pV are combined and input as a voltage V4 to the amplifier 301 to obtain a voltage V5.

ここで増幅器10と30の特性は等しく、高入力インピ
ーダンス、低出力インピーダンスであり、かつ2次歪は
無視できるものとする。又電圧変成器20も入力インピ
ーダンスが充分高く、出力インピーダンスが充分低くか
つ一方向性の無歪回路であるとする。増幅器10の出力
電圧V2は次式のように表わせる。
Here, it is assumed that the amplifiers 10 and 30 have the same characteristics, high input impedance and low output impedance, and second-order distortion can be ignored. It is also assumed that the voltage transformer 20 has a sufficiently high input impedance, a sufficiently low output impedance, and is a unidirectional distortion-free circuit. The output voltage V2 of the amplifier 10 can be expressed as follows.

V2=aVI+CV亭=VI<a+CV亭) ‐
…‐‐(1)電圧変成器20の出力は入力電圧v.がp
倍されて、pv,となる。
V2=aVI+CV-tei=VI<a+CV-tei) -
...--(1) The output of the voltage transformer 20 is the input voltage v. is p
It is multiplied by pv.

このpv,と出力電圧v2を合成した電圧は増幅30の
入力電圧v4となり、V4=V・〔(a+p)十CV亭
〕 ……【21で表わされる。
The voltage obtained by combining this pv and the output voltage v2 becomes the input voltage v4 of the amplifier 30, and is expressed as V4=V[(a+p)0CVtei]...[21].

従って終段の出力電圧v5は次式のようになる。V5=
V4(a+CV葦) =v,〔(a+p)a+{a+(a+p)3}cv三十
3(a+p)2C2V子+3(a+p)C3V亘十C4
〆〕 ‐…‐‐(3)式{3)より1次、即ち基本
波成分vo,は v。
Therefore, the final stage output voltage v5 is expressed by the following equation. V5=
V4 (a+CV reed) =v, [(a+p)a+{a+(a+p)3}cv33(a+p)2C2Vko+3(a+p)C3VWatariC4
〆〆〆〆〆〆〆〆〆〆〆〆From equation {3), the first-order, that is, the fundamental wave component vo, is v.

,=(a十p)av, ……【413次
歪波成分vo3はv。
,=(a0p)av, ...[The 413rd-order distorted wave component vo3 is v.

3={a十(a十p)3 }cべ ・・…・【51
式■より3次歪波相殺の条件は次のようになるp=−a
−3ゾa ……(61式(6’
を式(4}に代入すればv〇,=一3ノa.av,
……(7)が得られるが、式{7}の
意味は第1図の歪相殺回路において増幅器10と電圧変
成器20を合成した前段による利得が一3ノaであり後
段の増幅器30による利得がaであることを示している
3 = {a ten (a ten p) 3 } c be ... [51
From the formula ■, the condition for third-order distortion wave cancellation is as follows: p=-a
-3 zo a...(61 formula (6'
Substituting into the formula (4}, we get v〇,=-3ノa.av,
...(7) is obtained, but the meaning of equation {7} is that in the distortion canceling circuit shown in FIG. It shows that the gain is a.

従って前段の利得をデジタルで表わして、後段の利得の
3分の1になるように電圧変成器20の倍率Pを定める
と3次歪は相殺される。以上の説明から明らかなように
本発明による歪相殺回路によれば電圧変成器の倍率Pを
適当に選ぶことによって3次歪を消去できるので、本発
明における増幅器10? 30として例えばプッシュプ
ル増幅器を使用することによって、2次及び3次歪の無
い増幅装置を実現することができる。
Therefore, if the gain of the front stage is represented digitally and the multiplier P of the voltage transformer 20 is determined to be one-third of the gain of the rear stage, the third-order distortion is canceled out. As is clear from the above description, according to the distortion canceling circuit according to the present invention, third-order distortion can be canceled by appropriately selecting the multiplication factor P of the voltage transformer. By using, for example, a push-pull amplifier as 30, it is possible to realize an amplification device free of second-order and third-order distortion.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の歪相殺回路を説明するためのブロック図で
ある。 図において、10,30‘ま増幅器、201ま電圧変成
器を示す。
The figure is a block diagram for explaining the distortion canceling circuit of the present invention. In the figure, an amplifier 10, 30' and a voltage transformer 201 are shown.

Claims (1)

【特許請求の範囲】[Claims] 1 高周波入力信号を増幅する第1の増幅器と、該第1
の増幅器とともに前記高周波入力信号が入力され、これ
を所定の比率で昇圧する電圧変成器と、前記第1の増幅
器と前記電圧変成器の出力を合成し得られた出力信号が
入力される、前記第1の増幅器と同様の特性を有する第
2の増幅器とを有することを特徴とする歪相殺回路。
1 a first amplifier that amplifies a high frequency input signal;
The high-frequency input signal is inputted together with the amplifier, and the voltage transformer boosts the voltage at a predetermined ratio, and the output signal obtained by combining the outputs of the first amplifier and the voltage transformer is inputted. A distortion cancellation circuit comprising a second amplifier having similar characteristics to the first amplifier.
JP14685576A 1976-12-07 1976-12-07 Distortion cancellation circuit Expired JPS608653B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14685576A JPS608653B2 (en) 1976-12-07 1976-12-07 Distortion cancellation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14685576A JPS608653B2 (en) 1976-12-07 1976-12-07 Distortion cancellation circuit

Publications (2)

Publication Number Publication Date
JPS5370741A JPS5370741A (en) 1978-06-23
JPS608653B2 true JPS608653B2 (en) 1985-03-05

Family

ID=15417068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14685576A Expired JPS608653B2 (en) 1976-12-07 1976-12-07 Distortion cancellation circuit

Country Status (1)

Country Link
JP (1) JPS608653B2 (en)

Also Published As

Publication number Publication date
JPS5370741A (en) 1978-06-23

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