JPS6085467A - Disk motor controlling signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a PWM signal for driving a disk motor in a rational manner by comparing a self-advancing counter that circulates at a specified speed with speed command data. CONSTITUTION:A pulse width modulation PWM circuit 41 is self-advanced by a latch circuit 42 and an internal clock (clock formed by a crystal oscillator) and detects coincidence with a counter 43 that circulates at every 1 frame period by a coincidence detecting circuit 44, and outputs a motor driving signal DM+ or - at pulse width prescribed on the basis of the coincidence detection, and drives a disk motor 3 through a motor controlling section 45. These driving signals DM+, DM- do not exist simultaneously. Driving in normal direction is made by DM+, and driving in reverse direction is made by DM-. The rotation speed is controlled by the pulse width of driving signals DM+, DM-, and the narrower the pulse width, the lower the rotation speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a generation circuit for a PWM (/e pulse width modulation) signal for driving a disc motor in a connosect disc (OD) player, etc. By using a counter and comparing the count II with speed command data of the disc motor, a PWM signal for driving the disc motor with a pulse width corresponding to the speed command data can be reasonably obtained.

BACKGROUND OF THE INVENTION Connogect disks are used to record information at a constant linear velocity and to reproduce RFM signals (reproduced from the disk with nine FIF signals).
The phase of the frame synchronization signal created from the M signal and the internal synchronization signal created by the crystal oscillator is compared, and the rotation of the disk motor is controlled using the phase difference data as a speed command. Disk motors are generally Ij! L
A flow motor is used, and is driven by a signal obtained by converting the above speed command into a PWM signal.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a disk motor control signal generation circuit that can rationally generate the PWM signal for driving the disk.

Structure of the Invention This invention provides a counter that runs and circulates at a predetermined speed, compares this counter) f The PWM signal is generated by outputting the signal in the width until reaching the set value, or in the width from reaching the appropriate set value until reaching the speed command data.

Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

Note that in the following embodiments, the notation of logic circuits is simplified in order to make the drawings easier to understand. An example of this is the notation shown in FIG. 1(,), which corresponds to the configuration shown in FIG. 1(b) when shown in a general notation.

FIG. 2 shows an example of the overall configuration of a disk control system to which the present invention is applied. This disk control system includes, in addition to a disk rotation servo system, a focus servo system that focuses the light beam and a tracking servo system that causes the rQ record light beam to follow the track.

The frame positive synchronization signal generation circuit 1 determines whether the rotation of the disk motor 3 is stable (rotating stably at a rotational speed at which a predetermined linear velocity can be obtained - hereinafter referred to as synchronous speed) or unstable. It detects whether the rotation speed is fluctuating outside of the synchronous speed.
In a stable state, a frame positive synchronization signal 5YIilQ is output. For example, as shown in FIG. 3, the frame positive synchronization signal generating circuit 1 with
At the same time as counting up the counter 16 at step c, the frame synchronization signal reproducing circuit 17 detects the frame synchronization signal at the beginning of each frame in the EFM signal, and outputs the detected signal P.
Every time 22 is output, the counter 16 is reset and counting is repeated, and at that time, the 588th count of counter]6 is outputted and the detection signal P! The positive synchronizing signal 8YEQ is configured to be outputted via the AND circuit 18 when the timing at which the signal 2 is output matches. That is, in the data format of a compact disc, as shown in Figure 4(a)K, one frame consists of 588 channel bits, and a frame synchronization signal is placed at the beginning of each frame to indicate the beginning of the frame. . The synchronization detection circuit 17 detects this synchronization signal and detects the fourth synchronization signal.
The reproduction synchronization signal ptt shown in FIG. 3(b) is output. On the other hand, the reproducing circuit 15 outputs a regenerated 4-pulse Pc of 588 pulses per frame based on the past data of the BFMQ signal.

Therefore, if the disk motor 3 is rotating stably at a synchronous speed, the reproduction synchronization signal pu
A reproduced clock Pc of exactly 588 pulses is obtained during the period t. Therefore, at this time, the reproduced clock Pc is set to counter 1.
6 and reset the counter 16 every time the reproduction synchronization signal pH is obtained, the counter 16 will always count 588 when the reproduction synchronization signal P11 is output.
As shown in FIG. 4(d), the reproduction synchronization signal Pat IIC
In synchronization, a frame positive synchronization signal 8YEQ is obtained. However, if the rotation of the disk motor 3 deviates from the synchronous speed, the disk rotation servo will control it so that it approaches the synchronous speed, so the rotation speed will fluctuate and the generation cycle of the playback synchronization signal Plt will fluctuate. do. On the other hand, since the reproduction Pc is created based on the past data of the IilPM signal, it does not immediately follow changes in the rotational speed. Therefore, there is a difference between the generation timing of the reproduction synchronization signal P1m and the timing of the 588 count of the reproduction clock Pc.For example, if it is slower than the synchronization speed, it is controlled to accelerate,
Since the generation cycle of is short, the next reproduction synchronization signal P1m is generated before counting 588 reproduction cycles Pc.

If the synchronization speed is high, it is controlled to slow down, so the generation cycle of the reproduction synchronization signal P1m is long.
The reproduction clock P is generated before the next reproduction synchronization signal Pal is generated.
588 counts of c are completed.

In this way, when the rotation of the disk fluctuates away from the synchronous speed, there is a difference between the timing of generation of the reproduction synchronization signal PH and the timing of the 588 count of the reproduction clock Pc, so the frame positive synchronization signal 8YBQ cannot be obtained. It is possible to detect whether the rotation of the disk is in a stable state or in an unstable state depending on the presence or absence of the frame positive synchronization signal 8YBQ.

In FIG. 2, a disk motor drive control circuit 2 controls the rotation of a disk motor 3. As shown in FIG. This rotation control is DM+, DM- 2flI type PWM.
(pulse width modulsi on) This is done by a modulated drive signal. These drives (N
The numbers DM+ and DM- do not exist at the same time; driving in the forward rotation direction is performed by DM+, and driving in the reverse rotation direction (braking for the forward rotation direction) is performed by DM-. The rotational speed is controlled by the pulse width of the drive signals DM+ and DM-, and the wider the nosolus width, the higher the rotational speed, and the narrower the pulse width, the lower the rotational speed.

The optical system servo I circuit 4 controls the position of the optical system that irradiates the disk 5 with a light beam and receives the reflected light, and includes focus servo, tracking servo, and feed servo circuits 2. There is.

The focus control circuit 6 is for controlling the focus of the light beam, and when the light beam is out of focus, it outputs a focus out signal FOO to the disk motor drive control circuit 2 and performs control to refocus. That is, in response to the initial setting signal FO8, the focus actuator is returned to the initial position and is gradually sent out from there to confirm that the reflected light is captured by the 4-split photodiode P, that is, that it has approached the vicinity of the focal point. Is the detection signal FB correct? ), and when it is detected that the difference signal between the two diagonal outputs of the 4-split photodiode crosses zero (detection signal t'zo), it is determined that the focus is on,
The focus-out signal FOO is canceled to stop the focus actuator.

The tracking control circuit 7 controls the position of the light beam in the disk radial direction so that the light beam accurately tracks the track on the disk 5. Rough control is performed by moving the entire optical head using a feed motor. , precise control is by tracking actuator) Optical spatula P
Let's move the relative position of the objective lens in . Each control signal output from the tracking control circuit 7? ), TR0F is a tracking serve off signal for turning off the tracking serve in search operations such as random access, and TRGLFi is a signal for switching the tracking servo gain. , ) This is a signal that switches the gain of the clock servo to high gain. T.R.
HD is a hold signal that temporarily holds a tracking error signal for tracking control. In order to prevent tracking serve from becoming unstable after a feed or track jump is completed, the tracking error signal of the feed or track jump is temporarily held, and after the feed or track jump is completed, tracking is performed using the held tracking error signal. This is to restore control. KP+ is a kick pulse in the positive direction (the tracking actuator moves in the outer circumferential direction), and KP- is a Φtsuk pulse in the negative direction (the tracking actuator moves in the inner circumferential direction). H
The EM engineer uses a signal to forcibly drive the feed motor in search mode, etc., and FBM+ is a drive signal in the outer circumferential direction.
F'BM- is a drive signal in the inner circumferential direction. FBOF is a signal that turns off the feed motor while the feed signal FFfM is being output.

The input device 8 is an operation switch for performing operational modes such as playback, search, fast forward, and backward, and for setting a track number in a search mode. The microcomputer 9 outputs various commands (operation instructions) in response to operations on the input device 8. The command names and their contents output from the microcomputer 9 are shown below.

oO mode (8TOP) Command to stop all operations o1 mode (FF! l1lD) @1) 0-E--de (li'BFID FORWARD
): If a command is given to feed the optical spatula P toward the outer circumference, when the playback is finished, a command is given to feed the optical spatula P to the end position of the inner circumference and return the light beam. Focusing command o3-0 mode)' (DISK 5TART) When the tray on which the disc is placed is stored in the OD device, it rotates a little and uses its inertia to detect whether or not the disc is on the tray. Command 1 for disc rotation motor brake (applying reverse voltage) command 04%-F' (pbAy) Reproduction operation command 05 mode/5-0 mode ([>shi+): Fast forward command 06 mode・6-0 mode ([>l>[>+): High speed fast forward command 5
If the -0 mode is operated for, for example, two seconds, the mode is automatically shifted to this mode. 7 mode (S F) AROH) Target address search command The commands that can be output from the microcomputer 9 are I
The signal is stored in the command register 10 via the 10 circuit 12, is coded by the command P decoder 11, and is applied to the disk motor drive circuit 2 and the tracking control circuit 7. The disk motor drive circuit 2 outputs a drive signal DM so that the rotation of the disk motor 3 corresponding to this command can be obtained. Also, in the tracking control circuit 7, tracking control corresponding to this command P is performed. This tracking state (for example, the difference between the target position and the current position in search mode P) is transmitted to the microcomputer 9, and is used to switch the command from search mode to playback mode when the target position is reached.

The display device 13 displays time information of the playback position and the song number set in the search mode.

The memory circuit 14 is for storing set song numbers and the like in the search mode.

The configuration of the disk motor drive circuit 2 is shown in FIG.

In FIG. 5, a change detection circuit 21 determines whether a predetermined linear velocity is obtained from the pattern of the BFM signal based on @1'' to @θ'' or 10'' in the EPM signal.

In other words, the FIFM modulation signal is 1 as a frame synchronization signal.
The maximum pulse width is defined as a pattern in which 1 channel pit "12" is consecutively followed by @O" for 11 channel bits, and a pattern in which 11 channel pits or more are consecutively 11# or '0#" is defined as the maximum pulse width. Since it does not exist within one frame, a clock (4,32 h) is obtained by dividing 136 μs (hereinafter referred to as one frame period), which corresponds to the time of one frame when the correct linear velocity is obtained, into 588. If you make it with a crystal oscillator and use that clock to count the consecutive times of "1", "0", and "0" of the FfFM number, you will understand that if there is a part with 12 or more consecutive counts, it will be slower than the normal speed. ! J, when there is no continuous part of 11 counts, and there is no continuous part of 12 counts or more, you can understand that Jin and 1'JL are faster than the Royal Palace rotation. In this way, the pattern 8 circuit 22
Based on the signal, it is determined whether the actual linear velocity is faster or slower than the specified linear velocity, and if it is fast, a decision signal DB is output, and if it is slow, a decision signal AFf is output. Further, in order to detect whether the disk rotates or stops, the nog-turn determination circuit 22 detects the presence or absence of a change in the EFM signal for each frame, and if there is a change even once during one frame period, it indicates that the disk is rotating. and outputs a judgment signal PX.

The counter circuit 23 has two uses; one is based on the frame positive synchronization code 8YEQ and its inverted signal 8YEQ (a signal indicating that the rotation is unstable), and the one is to check whether the rotation of the disk remains stable; The other one is used to determine whether the rotation of the disk has stopped based on the rotation detection signal PX. These uses are carried out by: That is, command signal 8
In operating modes other than applying the brake, it is necessary to judge whether the disc rotation is stable or unstable.When applying a command brake, it is necessary to judge whether the disc rotation is stable or unstable, so the disc rotation is determined based on the signal PX. It is determined whether the rotation of has stopped.

The counter circuit 23 determines whether the disk rotation is stable or unstable using the frame positive synchronization signal 8 obtained for each frame.
YEQ or frame asynchronous signal 8YFiQ with +4 and -1 respectively correspond to frame positive synchronous signal 8YB
This is done by counting up by 4 each time Q is generated and counting down by 1 each time frame asynchronous signal 8YFIQ is generated. In other words, if the stable rotation state continues, the count value increases, so the count value increases to a preset value (102 in this example).
4 counts), it is determined that stable rotation is continuing, a PLL flag is set in the register 32, and disk rotation control is switched to phase control by PLL. In addition, even if the PLL flag is set once, if it becomes unstable after that, count down by 1 every time the frame asynchronous signal 8YEQ is output, and when the count returns to OK, lower the PLI flag and change the disk rotation control to the PLL. Switching from phase control to direct control using predefined drive signals to quickly restore disk rotation.

The determination by the counter circuit 23 as to whether or not the disk rotation has stopped is determined by the disk rotation detection signal PX'f: disk stop detection signal PX created by inverting the disc rotation with the inverter 05.
This is done by counting. That is, 3--
After entering the mode, reset the count value for determining whether the disk rotation is stable or unstable, and count the disk stop detection signal PX every 17 frames. It is determined that the rotation has stopped, and 47 lags are set in the register 34. These four flags are inverted by an inverter 35 and used as a brake enable signal BEI to issue a brake reverse voltage application release command.

The counter circuit 23 having the above functions is composed of a serial counter consisting of an 18-bit shift register 24 and an adder 25, and a counter control circuit 26. The serial counter inputs the noggles sent from the color control circuit 26 at a predetermined timing to the input of the adder 250, and returns the final bit output of the shift register 24 to the input of the adder 250B. The carry output 00 is delayed by 1 bit by the register 27 and inputted to the carry output O1. The shift register 24 has an 18-pit configuration, and one frame period is 18.
Because it is divided into four people and counted by φB,
It goes around once every frame period. Counter control circuit 26
When used to judge whether the disk rotation is stable or unstable,
For each frame in which the frame positive synchronization signal 8YPXQ is generated, 1" is added to the input of the adder at the timing of 3B of the frame. Here, the timing of 3B is as shown in FIG. , φB counts 18 in one frame period, and at the timing of the third LSB bit, a) the third bit from the LSB of the count value of the shift register 24 is output from the shift register 24, and the B input of the adder 24 is output. In other words, the third bit from the bottom corresponds to the decimal number 4, so inserting "l" here means adding 4. Note that the counter The control circuit 26 outputs "1" during one frame every time the frame asynchronous signal 8YRQ is generated, and the control circuit 26 outputs "1" to the shift register 24.
Add ``l'' to all bits of . In other words, a subtraction of 1 is performed. The f shift register 24 is 1
When it reaches 024, the register 31 is set and the lK flag is output. This IK flag is a signal indicating that the stable rotation state continues. When the IK flag is set, the register 32 is set and the aforementioned PLL flag is output, indicating that the rotation is stable. When the stable rotation state is broken, the shift register 24 counts down, but the PLL flag continues to rise until the count value returns to O. When the count value reaches O, register 33
is set, the 0 flag rises, the register 32 is reset, and the PLL flag falls. This indicates that the rotation is unstable.

FIG. 7 shows the relationship between the count value of the shift register 24 and the PLL flag. The count value increases by 4 every time the frame positive synchronization signal SYBQ is output from the start of counting, and the count value increases by 4 every time the frame positive synchronization signal SYBQ is output.
Each time Q is issued, it counts down by 1, and if stable rotation continues and the count value reaches 1024, PLL7
There is a lag, indicating stable rotation. After that, if the unstable rotation continues, the PLL flag goes down when the count value reaches 0, indicating that the rotation is unstable.

When a - mode command is issued, the change detection circuit 38 verifies its rising edge, resets the count value, and counts the stop detection signal PX every frame period.

When the count value reaches 4, the register 34 is set and 47 lags are output.

This 47 lag is inverted by the inverter 35 and used as the brake enable signal BB. In other words, when the brake enable signal BEI is @l'', it means that the disc is rotating a little, and 3--
In this mode, when the signal BB falls, it is detected that the rotation of the P disk has stopped, and the application of the reverse voltage for applying the brake is released. When the command in the 3--mode falls, the count value is reset again in preparation for counting the frame positive synchronization signal 8YEIQ and the frame asynchronous signal 8YBQ in the next mode.

(19) The registers 31 to 34 that output each of the seven lags are updated once per frame at the timing of the signal MOB (FIG. 6). Additionally, the brake enable signal B14. IK
A signal nζ obtained by inverting the flag at the inverter 36 and a signal nζ inverting the O flag at the inverter 37 are used to stop counting, respectively.

In FIG. 5, the PWM circuit 41 includes a latch circuit 42,
Internal clock (created by crystal oscillator or clock)
2) Counter 4 that runs on its own and circulates every frame period.
3 is detected by the coincidence detection circuit 44, and a motor drive signal DM is output with a pulse width specified based on the output of the disc Tanabata 3 through the motor control section 45.
It is what drives the.

For example, as shown in FIG. 8, the motor control unit 45 includes a constant current circuit 55, inputs a motor drive signal DM via an amplifier 54, and causes the drive amplifier 56 to drive the disk motor 3. It is composed of

(20) In FIG. 5, the counter 43 is 29 from θ to 293.
It is a 4-count counter, driven by clocks φl and φ2 of 1 frame period 294 pulses (2,1609 h) generated by a crystal oscillator, and runs by itself, making one cycle in one frame period. A decoder 46 decodes the count value of the counter 43. The period of one frame shown in Fig. 6 is 18
Divided signals L8B, 2B, 3B, ..., 17
B, MSB is also created here. The latch circuit 42 has a PW
It doubles the data that defines the noggle width of the motor drive signal DM, which is the M signal, and the data to double is determined by each control mode signal of PLL% SIM, OFF% BLK from the control logic 48. .

- The loading/unloading circuit 44 matches the latch circuit 42 and the counter 43 and controls the timing of the rise and fall of the motor drive signal DM. Since the counter 43 makes one cycle in one frame period, a coincidence signal is obtained every one frame period, and one pulse of the motor drive signal DM is outputted.

The selection circuit 47 is a PLL from the control logic 48.

8IM selects and outputs the output of the simulation circuit 51 or the output of the frame remaining amount counter 52,
It is latched into the latch circuit 42.

The frame remaining amount counter 52 indicates the amount of E to be played back from the disc.
Its purpose is to detect the deviation between the FM signal and the internal circuit made of a crystal oscillator.

This frame remaining amount counter 52 is derived from an upper counter 52A and a lower counter 52B. The 52 upper counters detect shifts in frames, and are composed of up/down counters, which count up by 1 for each frame of BFM@i using the frame synchronization signal of the IilFM signal, and count up by 1 for each frame of BFM@i using the internal clock. Frame period (136μ
Count down by 1 for each attack. Therefore, when the linear velocity is faster than the prescribed linear velocity, the count value increases because the number of times it is counted up is large, and when the linear velocity is slower than the prescribed linear velocity, the number of times it is counted down is large and the count value decreases. The lower counter 52B detects the phase shift between the frame synchronization signal of the gFM signal and the frame synchronization signal generated by the internal clock, and is reset for each frame of the EF'M signal by the frame synchronization signal of the FIPM signal. The BPM sindel signal (signal output every 17 channel bits of the FIF'M signal) synchronized with the sinsel of the FIF'M signal is counted up. The lower counter 52B itself always reaches a predetermined count value for each frame, regardless of the deviation (gFM symbol signal).
As will be described later, the count value is latched in the latch circuit 42 by the PLL control mode signal output at the timing of the 293 count signal which is output once per frame synchronized with the internal clock, so it depends on the magnitude of the phase difference. The latching timing changes, and the latched value corresponds to the magnitude of the phase difference within the frame (23).

The shimmy range circuit 51 integrates the output of the latch circuit 42 with a certain time constant (for example, 18 seconds). Since the data of the latch circuit 42 defines the pulse width of the disc motor drive pulse DM, its integral value is the average of the pulse width of the disc motor drive pulse DM± over a certain period of time. This shows the rotational state of the disc motor 3. The output data of this simulation circuit l is output in playback mode, etc.
The focus is off and the regenerated clock cannot be obtainedJ),
PLT.

When phase control by the control logic 48 becomes impossible,
It is selected by the 8IM control mode signal from the 8IM control mode signal, is latched by the latch circuit 42, and is used to create a disk motor drive signal DM. Since the latched value at this time is fed back to the simulation circuit 51 as it is, the output of the simulation circuit 51 continues to hold the predetermined value. That is, the disk motor 3 continues to maintain the speed before switching to the 8IM control mode P. In addition, the output of stain (24) 1-61*s1 indicates the rotational state of the disk motor 3, so the output is inputted to the control logic 48 via the decoder 53 and set in the control mode. It is also used for switching.

The output love code of the decoder 53 and the simulation circuit 51 is Mji, MIi+MZ%ML0MM.

Outputs five types of signals: ML and MH. Here, MH,
MM and ML%MZ are signals representing the following speed ranges, respectively.

MH: +200 Orpm or more MM: +100 to +200 Orpm ML: O to +100 rpm MZ: Orpm or less (reverse rotation) The control logic 48 is controlled by the microcomputer 9 (Fig. 1)
The operation mode r signals 81 to 82 from , the focus state display signal FOO indicating whether the light beam is in focus or out of focus, the stable rotation display signal PLL from the register 32, the signal B, AE, DE, Input each signal of disk rotation status display signal MH-MZ to PLL, SI
Each control mode signal of M%OFF and BLK is output selectively. Each of these control mode signals has the function of determining data to be latched by the latch circuit 42 and causing the corresponding control mode to be executed. The data latched in each control mode and the control contents accordingly are as follows.

The output data of the frame remaining amount counter 52, which is intended to indicate the difference between the BFM signal reproduced from the oPLL control mode disk and the internal clock generated by the crystal oscillator, is selectively outputted from the selection circuit 47 and sent to the latch circuit 42. Latch. This allows PLL
The rotation of the disk motor 3 is controlled by phase control.

The output data of the OS I M control mode simulation circuit 51 is selected by the selection circuit 42
The output signal is selectively outputted from the output signal and latched into the latch circuit 42. Control is thereby performed to maintain the current rotational speed.

The drive pulse DM is applied to the oOFF control mode latch circuit 42 over the entire width.
0'' (D It rotates due to inertia.

The drive pulse DM- is applied to the oBLK control mode latch circuit 42 over the entire width.
1''(DM+=0.DM-=1>) is forcibly latched and direct control is performed using this data.

At this time, since a driving force is applied in the opposite direction, a brake is applied to the rotation in the forward direction.

oFo control mode When any of the above control mode signals of PLL, 8IM, OFF, and BLK is specified, the FO control mode is entered.

That is, the latch circuit 42 is forcibly latched with data that sets the drive signal l) M+ to 11'' (DM+=1, DM-=O) over the entire width, and direct control based on this data is performed.At this time, Since a driving force is applied in the positive direction,
accelerated in the positive direction.

Control logic 48 turns these PLLs %SIM, OFF.

There are five control modes: BLK and FO, operation modes 0 to 7, rotation status of the disk motor 3, focus status,
The execution is switched as shown in FIG. 9 depending on the presence or absence of the PLL flag. Switching of control modes in each operation mode O to 7 will be explained.

o O (S TOP ), 1 (F BED ) mode Since rotation of the disk is not required, the OFF control mode is used in the entire speed range.

o2 (FOOD8 5TART) mode 2 mode is used to adjust the focus when the focus is already correct. Therefore, since the reproduced clock is obtained at this time, it cannot be controlled by the PLL control mode P. Therefore, the simulation circuit 51 performs control in the fiHOLD control mode. Note that in the MH speed range, the OFF control mode is set to prevent high rotation. Further, in the MZ speed region, the OFF control mode is set to prevent reverse rotation.

o 3 (DI8K 5TART) Mode DI8K 8
In TART mode, when a disc tray is pushed into the 0D device, the disc motor rotates a little and the inertia at that time is used to detect whether or not the disc is mounted on the tray. To accelerate. However, when the speed enters the MH speed range, the OFF control mode is set to prevent high rotation.

), 7(8EA几0)l) When the mode focus is correct and the PLL7 lag is set, use the frame remaining ψ counter 52 to set the PLT
, performs lock control using control modes.

If the focus is correct but the PLL flag is not set, control by the signal AE%DE (AFO: au
tomatic frequency control
). That is, when the signal AI is output (when the linear velocity is slower than the specified linear velocity), the FO control mode is set and acceleration is performed. Further, when the signal DFf is output (when the linear velocity is faster than the specified linear velocity), the speed is reduced by setting the BLK control mode.

And FO control mode straddling B L K fli
When the control mode is selected, the OFF control mode is set when the specified linear velocity is reached and the signal AE or DB disappears. If this control causes F T, L 7 lag,
When switching to the PLL control mode, in the -■ speed range, the OFF control mode is set to prevent high rotation. M.L., M.L.
In the Z speed region, the FO control mode is set and acceleration is performed in the forward direction.

When the focus is off, a reproduced clock cannot be obtained and control using the PLL control mode or AFO control mode cannot be performed.
Use LD control mode.

During execution of this HOLD control mode, the focus is restored and the mode is switched to the PLL control mode or the AFO control mode. In the MH speed range, set to OFF control mode to prevent high rotation.

In the MZ speed range, the OFF control mode is set to prevent reverse rotation.

Apply reverse voltage to decelerate. When it is detected by the brake enable signal BE="O" that the rotation of the disc motor 3 has stopped, the BLK control mode P is released. In the MZ speed range, set to OFF control mode to prevent reverse rotation.

FIG. 10 shows the configuration of the control logic 48 that performs the control shown in FIG. 9 above.

Each region in FIG. 9 corresponding to AND circuits 181 to 188 is shown in FIG. 9 using symbols (,) to (h), respectively.

The reason why there is no AND circuit corresponding to the OFF control mode area in FIG. 9 is because the area that does not correspond to any of the AND circuits 181-188 is treated as the OFF mode. The outputs of AND circuits 183 to 188 are OR circuit 191
are combined to form a signal instructing the FO control mode P.

The output of the AND circuit 184 becomes a signal instructing the PLL control mode. The outputs of AND circuits 185 and 186 are combined by OR circuit 192 to become a signal instructing the HOLD control mode. The outputs of the AND circuits 187 and 188 are combined by an OR circuit 193 to form a signal instructing the BLK mode. The NOR circuit 194 includes the OR circuits 191, 192 .
Input the output of i93 and AND circuit (31) 184, and when all of these are "0"
1'' is output from the NOR circuit 194. The output °1'' of this NOR circuit 194 becomes a signal instructing the OFF control mode.

From the control logic, the PLL control mode and HOLDFO control mode can be treated as a state in which none of these four control mode signals is output, so the signal instructing the FO control mode from the OR circuit 191 is
No output from control logic 48.

Here, a specific example of the part surrounded by a person in FIG. 5 is shown in FIG. 11. In FIG. 11, the EFM signal change detection circuit 2
1 x 2 bit shift register 61 and exclusive OR circuit 6
It is composed of 2. The shift register 61 has one frame of 588 /R/l/s(4,3) made from a crystal oscillator.
2M)(z), and the input BFM signal is driven by the clock φ3. φ4
Shift (32) in accordance with internal synchronization. The exclusive OR circuit 62
By inputting the output of the second stage and the second stage, a clock φ3° is output every time the EFM signal rises and falls.

The pattern determination circuit 22 uses the output pulse of the change detection circuit 21 as a clock φ3. The registers 63-1 to 63-11 are shifted sequentially by φ4, and the output pulses of the change detection circuit 21 are inputted through the input terminal 65, respectively. Therefore, when one pulse is output from the change detection circuit 21, as long as "0" continues, the register 6
3-1 to 63-2.63-3. . . . However, if the nogle signal is input again in the middle, the AND circuit 64 is turned off, and the previously transferred pulse disappears. Therefore, the 11th register 63-11 is not set until 11 consecutive "0" or 11# in the original EpM signal, and the output of this register 63-11 is ""1. It can be seen that there are at least 11 consecutive 0's. Furthermore, register 63-1
The output of Inno-Taro 5 is applied to the register 63-12 via the AND circuit 68 and the OR circuit 66. Therefore, register 63-12 is
When there is no change in the EFM number in the next bit after 11 is set, that is, when 12 consecutive "0's" are set, the bit is set and sold. The set state of this register 63-12 is self-held via the AND circuit 67 until the next change occurs in the BFM signal.

The output of the register 64-11 is sent to the register 73 along with the change detection signal via an AND circuit 71 and an OR circuit 72.
is input. Therefore, if register 73 is set, it means that a change has occurred after 11 consecutive @θ'', that is, exactly 11 10'' or 1
I understand that there are consecutive `` characters.Register 73
The set state of is self-maintained by a signal obtained by inverting the signal 587 at an inverter 78. Here, the signal 587 inputs the signal 293 of the final pitch (293 counts) of the decoder 46 (FIG. 5) to the 2-bit shift register 75, and outputs the output of the first stage and the output of the second stage. This signal is generated by inputting a signal inverted by an inverter 76 to an AND circuit 77, and corresponds to the signal of the M final bit when the l frame is divided into 588 (0 to 587). Therefore,
The register 73 is released from self-holding and updated at the end of the frame υ. The output of the register 73 is input to the AND circuit 81 along with the signal 587, and is applied to the register 83 via the OR circuit 82. Therefore, when register 73 is set, register 83 is set at the end of the frame. The set state of the register 83 is held by the signal 587 through the 772 circuit 84 for one frame until the next signal 587 is output. Therefore, the state in which the output 11E of the register 83 is "1" indicates that there was a portion in the BFM signal in the previous frame in which exactly 11 consecutive 0s were present.

The output of the register 63-12 is input to an AND circuit 85 together with the FfFM change detection signal, and is input to a register 87 via an OR circuit 86.

Since the register 63-12 holds the set state when 12 or more 0s are consecutive in the lilFM signal, the next E
Register 87 is set when a change occurs in the PM signal. Note that the register 63-12 is reset at this time.

Is the register 870 set state determined by signal 587? 77
2 circuit 88 until the end of the frame. The output of register 87 is input to AND circuit 91 along with signal 587, and is input to register 93 via OR circuit 92. Therefore, when register 8 is set, register 93 is set at the end of the frame.

Register 930 set state is set to 77 by signal 587.
It is self-held for one frame until the next signal 587 is output via the 2 circuit 94. Therefore, 0 is 1 in HFM signal.
If there are two or more consecutive signals and there is a change in the BFM signal thereafter, registers 93 to 11'' will be changed during the next frame.
will be output. The output of this V raster 93
” is used as a signal indicating that the linear velocity is slower than the prescribed linear velocity.

The signal 11E and the signal AE are input to the NOR circuit 99, and when both nl and rt are O, that is, EF'M in the previous frame.
When there is no part of the signal with 11 consecutive 0's and no part with 12 or more consecutive 0's, the NOR circuit 99 outputs wl.
The EFM change detection signal used as the signal DI indicating that the linear velocity is slower than the standard linear velocity is output from the AND circuit 95 and the OR circuit 96? This set state is self-held by signal 587 through AND circuit 98 until the end of the frame. When the register 97 is set to n, the AND circuit 101 and the OR circuit 102'l are activated at the timing of the signal 587 at the end of the frame.
The register 103 is set via r, then the signal “11
The set state is maintained by the amplifier circuit 104 for one frame until V falls. This register 10
The output ``11'' of 3 is a signal indicating that the EFM signal has changed at least once in the Ail frame, that is, that the disk is rotating.
Used as X. This signal PX is inverter 05
It is output as a signal PX which is inverted at n. Signals AI', DI, and PX output from the pattern determination circuit 22
is updated to one frame by signals 587 and 587.

The change detection circuit 38 receives a play mode operation signal from the register 13 via an AND circuit 111 and an OR circuit l12.
Enter ko'rL? I-Set.

The register 130 set state is updated by the signal MSB every frame during the duration of the signal MSBIC inverted by the signal Ni8Bt inverter 18. When signal 837 falls, the next signal MSB
The register 13 is reset at the timing of . It is input to the output of register 13 and z. Therefore, the signal w1'' is output from the exclusive OR circuit 115 at the timing of the signal Mf9B.
It is used to reset the count value of .

As mentioned above, the shift register 24 is composed of 18 bits, inputs the 8 output signals of the adder 25, shifts the signal by the clock φA-φB divided by 18 by 136 μs per frame, and outputs the output of the lowest stage. The 0-count value, which is fed back to the 8 inputs of the vO calculator 25 via the key-AND circuit 109 and circulated every frame period, is input from the input to the 7111 calculator 25 at which timing. The 110n value differs depending on whether it is input using the 110n value. In other words, the lowest pit I, 8B is input by timing R%.
nba1 is 7:ll'11I1. After that, input at the timing of lower 3 bits 3B and 4 is 7Jl.
] will be calculated n. Carry output Oo of adder 25
is delayed by 1 bit in the register 27, and then the AND circuit 11
0 is input to the carry power Oi, and a carry is performed.

Three AND circuits 123 (39
) to 125 are provided. AND circuit 12; t is PX
When the circuit 123 is enabled to count the number of consecutive frames issued by the brake mode signal circuit 124-1
25 becomes operational. and BFM for l frames
If there is no change in the signal, the signal PX becomes 1'', and the signal LS
AND circuit 123 and OR circuit 12 at timing B
A signal is input to the adder 2508 input through 7t-.

In this way, when the signal PX is issued, the current is increased by one for each frame. 4-alarm signal P
When X becomes "1" and the count value of the shift register 24 becomes 4, the AND circuit I is activated at the timing of signal M8B.
31 and the OR circuit 130, the register 34 is set. Register 340 set--AND circuit 13
3t- is self-maintained through ζ. The output of the V dimeta 34, that is, the previous (40
) The above 472g means that there was no change in the EFM signal for 4 frames. This 47 lag signal is inverted by the inverter 35 and is used as a determination signal that the rotation of the brake enable signal has stopped, and as a timing signal to terminate the application of the reverse voltage DM- for the brake.

4 flag is raised and play cow enable signal BFi is 10
”, the AND circuit 123 is turned off and the count is stopped. In this state, the falling edge is detected by the brake motor 38 and the 7111 counter 2 is output via the n1 in/?-1135.
The shift register 24 is reset while cycling through the 50 A and B inputs all off L/%17 frames. When the shift register 24 is reset, the self-holding of the register 34 is released at the timing of the signal M8B, and the play enable signal BE returns to 1''.

AND circuit 124°125 out of 250A input to adder
becomes operational. When the frame positive synchronization signal 5YBQ is obtained in this state, this frame positive synchronization signal 8Y
After EIQ is aligned with internal synchronization in the register 141, it is applied to the register 144 via the AND circuit 142 and the OR circuit 143 at the timing of the signal MOB, and is completely set. The signal M88 is then self-held via the AND circuit 145 for one frame. register 144
When is set, signal 3B causes shift register 24
°1# is AND circuit 1 at the timing of the lower 3rd bit of
24 to the λ input of the adder 25, and addition of 4 is performed in decimal notation. Also, frame positive synchronization signal 8YE
If Q is not set, the register 144 is not set and the signal 8 Y H
Q is output. Signal 8YEQ is input to AND circuit 125. Since the AND circuit 125 does not contain a signal that determines the timing of addition at a specific timing, ``1#'' is input to the A input during the one frame in which the signal 5YBQ is input. It continues to be input.In other words, a subtraction of 1 is now performed.One of the signals 5YEQ and 8YEQ is output every 7 frames, and each time the count increases by 4 (8'YEQ).
Or a 1 countdown (SYBQ) is performed.

When the count value reaches 1024, the IK of the shift register 24
(1024), the register 31 is set via the AND circuit 151 and the OR circuit 152 at the timing of the signal M8B.The set state of the register 310 is determined by the signal MSB.
53 for the duration of the frame. When the shift register 31 is set, its output is sent to the inverter 3.
The AND circuit 123 is turned off via 72, and further count-up is prohibited. However, since countdown is not prohibited, if the frame asynchronous signal 8YEQ is input, the countdown will start.

If it is counted down, the shift register 31 will be filled (43
), so it is possible to count up again.

During steady operation, the count value is 1024t.
``It fluctuates up and down around that area at its maximum.

The output of the bit corresponding to IK of register 24 is also:
It is directly added to the register 165 as an IK flag at the timing of the signal MSB via the AND circuit 161 and the OR circuit 162, and sets pn2. The recent state of register 165 is self-held during the frame by signal MSB via AND circuit 164. register 165
From then on, the PLL flag 2 is output in the set state.As mentioned above, the count value of the shift register 24 is 7 to IK.
Is it still around that area after 1 count up? Although it fluctuates, register 165 is once self-held n, rL is set even if shift register 24 drops from IK? Last, PL
T, continues to output 7 lags. However, the unstable state of the 1-disk motor continues and the countdown continues, and when the count value drops to 0, all bits in the shift register 24 become '01', so (44) the output of the NOR circuit 172 becomes "1", This signal is applied to the register 175 via the AND circuit 173 and the OR circuit 174vi at the timing of the signal MSB, and is then set. The set state of register 175 is self-held during its frame by signal MSB. When the count value falls to 0, the output of the register 175 is transferred to the AND circuit 1 of the A input of the adder 25 via the inverter 372.
25 are all turned off, and subtraction beyond Soe is prohibited. Further, the output 11'' of the NOR circuit 172 turns off the AND circuit 163 via the inverter 1671'', and resets the register 165 at the timing of the signal MSB. Due to this, P L
The L flag goes down.

As described above, from the circuit of FIG. 11, the circle, L flag and signal AJDJBI! Each time t is outputted.

Next, a specific example of the portion surrounded by the symbol B in FIG. 5, which is controlled by the output of the control logic 48, is shown in FIG. 12. In FIG. 12, the 294 counter 43 consists of a 9-bit half-7 der. Each stage 43-1 to 43
The S output of -9 is input to registers 211-219 via AND circuits 201-209. Registers 211-2
19 is a 1V-5 cycle (136μs) made with a crystal oscillator.
)? divided into 294 (i.e. 2.1609 MHz)
It is driven by clocks φ1 and φ2, and its outputs are applied to the inputs of each stage 43-1 to 43-9. Each stage 43-1
The carry outputs of 43-9 to 43-9 are input to the next stage's carry power. Clock ψ1, φ2
In other words, at the time of one frame period of 136 μs, θ
Construct a counter to count 29477 of ~293.

The signal XFSYNO is input to the AND circuits 2'01 to 209 by the inverter 221? Input via fL, 294 cow/p
43 is the initial reset. Here, signal XF8
YIiO is a signal that is output with the internal clock pulse width. The count values of Vjimeta 211 to 219 are determined by the decoder 4.
It is input to 6, and the necessary categorization decodes it and cuts it out. Said T, SI'S, 3B,
Signals such as F and ISB are also generated based on this output. Further, in order to control the circuit shown in FIG. 12, signals of 293 counts and 292 counts are decoded.

The 293 count signal is applied from the OR circuit 222 to each AND circuit 201 to 209 via the input circuit 221,
Every 293 counts 1.(-Used to reset n
Ru. 2 from 0 to 293 for each frame
The 1,292 count signal is used as a count signal for the counter 52 for every remaining frame.The remaining frame counter 52 is composed of an upper counter 52A and a lower counter 52B. It's cool.

The lower counter 52f (is composed of a 5-pit half adder), and the 8 outputs of each stage 52β-1 to 52B-5 are input to registers 241 to 245 via AND circuits 231 to 235. Carry human power Ui
An EF'M symbol signal is input to the EF'M symbol signal. BI'M
The sindel signal is a signal that outputs symbol data of 32 sindel data constituting one frame (47). One symbol data consists of a total of 17 pits, including 14 data bits and 3 margin bits. Therefore, the EPM synchronized signal is the KPM
It can be created by counting each reproduction clock 17 reproduced from the signal. The lower counter 52B is this EF.
The count is increased by ■ by the M-sin 2 signal. Lower counter 52Bf)% stages 5213-1 to 52B
The AND circuits 231 to 235 that input the output of -5 have
The signal obtained by inverting the EF'M frame signal by the inverter 201 is zero. BLi'M frame M is EFM
This signal is output once for each frame of the signal, and the frame synchronization signal at the beginning of the frame is detected and output. When this oil FM frame signal is output, the AND circuit 231
~235 is turned off, so the lower counter 52 becomes EFM.
(Reset for each frame of No. ii.

The upper counter 52A is constructed with a 4-bit full adder.
The S output (48) of each stage 52A-1 to 52A-4 is input to the V rasters 246 to 249. The outputs of the registers 246 to 249 are input to the B input of each stage, and the carry output of each stage is input to the carry input of the next stage. The carry human power OovCfdEFM frame signal of the first stage 52A-1 of the 52 upper counters is input, and the count is increased by 1 for each frame of the EPM signal.

In addition, the input to each stage is 292 from the decoder 46.
It counts down by 1 every 136 μs when a count signal is input and a 292 count signal is output.

Therefore, the upper counter 52A is fixed at a constant value because the L1 Atsuzo pulse and the down pulse alternately change to 0 when a normal linear velocity is obtained. However, if it is faster than the normal linear velocity, the period of Atzunogurus becomes shorter and the count value increases. , the count value decreases.

When the upper counter 52Aa count f reaches 8VC, the AND circuit 223 and the input/? - AND circuit 20:l is turned on via the counter 224, and counting up beyond that limit is prohibited. Also, when the count value becomes 0, the AND circuit 2
25 and the AND circuit 227 via the inverter 226
t is turned on, and downdown below T'L is prohibited.

Note that when p L L 79 is turned on, the add/do circuits 236, 237, 239 are turned off via the inverter 228, the registers 246, 247, 249 are reset, and the register 248 is turned off via the OR circuit 238. It is set and initialization is performed.

The selection circuit 47 uses the control mode signals PLL and 8IM from the control logic 48 to select the frame remaining amount counter 5.
Output 2 or H selects and outputs the output of the lapse circuit 51.

The selection signal PLL, 8 iM is an AND circuit 281°2
82, it is output at the timing of the 293 count signal. When the 8IM mode is selected, the AND circuit 241 becomes operable and the AND circuit 5 is activated.
A corresponding bit output of 1 is output via the OR circuit 243. Also, PLI.

When the mode is selected, the AND circuit 242 becomes operational and the corresponding bit output of the frame remaining amount counter 52 is outputted via the OR circuit 2432. Selection (No.N is output at the timing of the 293 count signal by the internal clock, while the frame residual counter 5
The lower counter 52B of 2 is 1' which is asynchronous to the internal clock.
Since it is reset by the M frame synchronization signal and counted by the EFM symbol signal, the count value at the timing of 293 counts is changed by the phase difference between the EFM signal and the internal clock. The magnitude r of the phase difference within one frame can be found by

The latch circuit 42 is a register 2 that launches 2 6-bit signals.
51-260? What signal is selected by the selection circuit 47? The signal 293 is inverted by the inverter 245 and held by the AND circuit 2442. In addition, in the latch circuit 42, the input circuit 246 connected to the registers 257, 258, and 259 has a Vss of 0" when the input (51) is input, and is not functionally meaningful. Further, when the OFF control mode is selected by the control logic 48, "11" is latched in the VC only in the register 259 via the AND circuit 247. Also,
When the BLK control mode is selected by the control logic 48, 0.1'' is added only to the register 260 via the AND circuit 128.

Note that the register 251 of the least significant bit of the latch circuit 42
B, only the signal from the simini-region circuit 51 is input T'L. This is because, in order to increase the accuracy of the control by the simulation circuit 51, the number of output bits of the simulation circuit 51 (t frame residual energy counter 52) is also increased by one lower bit.

- The number output circuit 44 associates the output of the latch circuit 42 with the count value of the 294 counter 43 and detects all coincidences between them. - The number output circuit 44 includes exclusive OR circuits EX1 to hiX9, each of which receives each bit output of the latch circuit 42 and each bit output of the 294 counter 43. Exclusion (52) Other or time V! The outputs of rEX1 to EX9 are the NOR circuit 2
61. Therefore, when the count value matches the output of the latch circuit 42, the NOR circuit 261 also outputs a match signal BQ (=-11).

The PWM circuit 41 includes a register 262 that outputs a positive driving pulse DM1 and a V raster 263 that outputs a negative driving pulse DM-.

The register 262 is self-maintained when the AND circuit 264 turns on vcxv and the AND circuit 2650 turns on. AND circuit 26411 This three signals are latch circuit 4
2 register 259.260 output? This signal is input to the OR circuit 272 and inverted by the inverter 273, and it is appreciated that "1" is not set in any n of the V raster 259, 260, that is, it is not overtime in the negative direction. Signal BQ is a coincidence signal. The signal OR256 is sent to the register 219 corresponding to the count value 256 of the 294 counter 43.
This is the signal inverted by the output r inverter 271, which shows that the count value has not reached 256. Therefore, when a match is found in the positive drive and the count value has not reached 256, the AND circuit 264 is turned on.
The register 262 is set through the OR circuit 264.
Ru. The set state of the register 262 is determined by the AND circuit 256? until the p count value reaches 256 by the signal GIM256.
Self-preservation through. When the count value reaches 256, the signal GE256 becomes "O", and the AND circuit 264.2
65 is also turned off, and the register 262 is reset. The above operation is performed for each frame. In addition, the register 262 has a width of 17 frames (136
μs) period? With PWM@1.11srt, the positive direction drive pulse Dλ1+ is output.

The register 263 is set when the AND circuit 267 is turned on, and the register 263 is self-held when the AND circuit 268 is turned on. The AND circuit 269 has four signals GF1128 and BQ.
, GE256 and GEO are input. Does GB128 drive in the negative direction? The signal shown, signal BQ, is the coincidence signal R
Signal inverted by Q inverter 274, GEO is 293
Is the signal delayed by 1 bit in the count signal register 275 3:b 294 the timing of the θ count? This is a signal that indicates Therefore, with negative drive, 2
94 When the count value of the counter 43 is 00, the AND circuit 2
67 is turned on, f'L$A circuit 267 is connected to register 2.
63 is set. Is the set state of the register 263 the AND circuit 268? self-retained through n. When the match signal EQ is output, the AND circuits 267 and 268 are turned off and the register 263 is reset. As a result of this 1L, the register 262 outputs a negative direction drive pulse DM- which has a width that rises when the 294 counter 43 is reset and falls when there is a match, and is f'WM modulated and has a period of one frame (136 μs). It will be reduced.

In this way, the positive direction drive pulse DM+ rises at a match (55) and falls at a count of 9,256, whereas the negative direction drive pulse DM- rises at a count of 0 and falls at a match. As the position of the coincidence changes, the width of one of the driving nozzles becomes wider, while the width of the lupus of the other driver becomes narrower. Then, the pulse width of the positive direction drive pulse DM+ becomes wider, while the pulse width of the negative direction drive pulse DM- becomes narrower; While the pulse width becomes narrower, the pulse width of the negative direction drive pulse DM- becomes wider. [Figure 13 shows the output of the IPWM circuit 41 for each output of the latch circuit 42]
This shows the changes in Gurus.

The operation of the circuit shown in FIG. 1112 in each control mode will be briefly described.

・PLL control mode As shown in Figure 9 above, the rotation is MM in modes 4 to 7.
(100 rpm to 200 rpm), when the focus is not captured and the PLL flag is set, the PLL mode (56) signal is output from the control logic 48, and the frame remaining stitch counter 52 is set at the selected path 47. Data from nib is selected, also P L L
With 7 lugs, the top 4 of frame remaining stitches J counter 52
Bit registers 249, 248, 247° 246
The nib is initialized to 1-0100J. In this one, F.
A stone that transitions to lock control by PLLK. In other words, if the linear velocity is faster than the specified linear velocity, the 14PM symbol signal, EIFM
Since it is shorter than the peripheral part of the frame signal, the latch circuit 42
(-) The counter value of the remaining frame amount counter 52 increases. As a result, the time it takes for the -scattering product output-l coincidence to be achieved becomes longer, the pulse width of the drive pulse DM+ becomes shorter, and the speed changes in a downward direction. On the contrary, the specified I%! If it is slower than fast skin, EFM thin signal, R
As the period of the FM7 frame signal becomes longer, the count value of the nb frame remaining 1+t counter 52 latched by the latch circuit 42 decreases. As a result, the time it takes to find a match with the scattered and integrated output lights is short, and the driving noculus DM+
The pulse width becomes longer and the speed changes in the direction of increasing. In this way, the count value from the frame remaining amount counter latched by the latch circuit 42 is stabilized at a time when the nozzle width corresponding to the normal linear velocity is obtained. Since the rotation speed of the OD is 480 rpm (inner circumference) to 21 Orpm (outer circumference), the relationship between the simulation output and rotation speed in FIG. 9 is vcxn.

For example, in a steady state, the values of the latch circuit 42 are m1O from the top.
II becomes stable at about 100XXX.

If the wnJ operation mode is 2 mode or 4 to 7 mode and the rotation is in the MM region and the focus is off, the playback clock cannot be obtained and lock control force cannot be obtained, so 8 IM control Switch to mode (happy 10
figure). That is, the selection circuit 47 receives the SIM mode signal from the control logic 48 from the simulation circuit 51.
Select the data from the latch circuit 42VC latch,
The pulse width of this latched jlLV drive pulse DM+ is recognized.

Since the 2-touch rt, fc+ direct to the latch circuit 42 is fed back to the simulation circuit 51 as it is, the simulation value does not change, and the rotational speed v, 1 . It is held constant.

-ot'P control mode When the OP F tri++ input signal is output from the control logic 48, the register 259 of the latch circuit 42 is set by the timing of the AND circuit 2841 and the 293 count signal. 'n, small. At this time, since the other control mode signals d:fL are not output, the other registers 251 to 258.26 (litter n:r) of the latch circuit 42 are
;:stomach.

Therefore, the output of register 259 becomes 21'',
At the timing when the signal XF'5YNO is issued, that is, at the timing when the count of 294 counter 43 is 0, the register 263
tries to set, but the inputs from the latch circuit 42 to the exclusive OR circuits EXI to EX9 all become "O" and the match signal EQ is not output. y263 is hri station output, drive Hals DM
+, DΔ・1- Yes, no output (DM+=Q,
DM-=O). L 'fC7: r
(It will be [ql.

@BLK 1lilJ control mode (59) In 3i mode, when the rotation is in the MH or MM region, the control logic outputs the BLK control mode signal, and the AND circuit 283 sets the timing 2 of the 293 count signal. The register 260 of the circuit 42 is set to T.
'Lru. At this time, other control mode signals are not output, so the other registers 251 to 259 of the latch circuit 42 are set to 1. , signal XI”5YNO
The register 263 is set by tying
Ruth DM- is output. The register 263 receives the match signal R set by the register 219 of the 294 counter 43.
Since it is reset only after Q is output, the driving force becomes ``l'' for the entire range of DM-1 from 0 to 256. This 7'LIC generates a driving force in the opposite direction to the disk motor 3. ◎ In the ego control mode I+"c+control mode, the control logic does not output any control mode signal f'L. Therefore, registers 251 to 260 of the latch circuit 42 are all reset (60 ) 9 6. In the set state. ! l), the integrated output signal EQ is output at the timing of the count value O of the 294 counter 43,
The register 262 is set and the drive pulse DM0 is output. The register 262 is reset when the count value of the 294 counter 43 reaches 256. Therefore, the entire period of the drive pulse DM+Q~256 is output. Therefore, the disk motor 3 is rotated at the same speed in the forward rotation direction.

As described in detail, according to the present invention, it is possible to rationally generate a PWM signal for driving a disk motor by comparing a counter that runs and circulates at a predetermined speed with speed command data. can.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram of the notation method of logic circuits used in the drawings of this application, Fig. 2 is a block diagram showing the layout system of a disc playback device to which this invention is applied, and Fig. 3 is a frame positive synchronization 18 No. 8: A block diagram showing an example of the YEQ creation circuit, Figure 4 is an explanatory diagram of the operation of the circuit in Figure 3, Figure 5
The figure is a block diagram showing one embodiment of the present invention, and FIG. 6 shows the control signal L8B. 2B..., an explanatory diagram of M2R, FIG. 7 is an explanatory diagram of the operation of the counter circuit 23, FIG. 8 is a circuit diagram showing a specific example of the motor control circuit 45, and FIG. 9 is a control by the control logic 48. FIG. 10 is a circuit diagram showing an example of the configuration of the control logic 48 for implementing the switching shown in FIG. 9, and FIG. 12 is a circuit diagram showing a specific example of the part surrounded by B in FIG. 5, and FIG. 13 is a circuit diagram showing the data latched by the latch circuit 42 in FIG. FIG. 3... Disc motor, 5... Disc, 23... Counter circuit, 41...
PWM circuit, 42... Latch circuit, 43...
... Karayuri, 44...--Scattered U road, 45
...Motor control circuit. (63) S B

Claims (1)

[Claims] A circuit that outputs the speed command data of the disk motor and a counter that self-runs and circulates at a predetermined speed compare the speed command data and the count value of the counter, and determine whether the count value reaches the speed command data. a circuit that outputs a drive signal for a DO motor for rotating the disk in a range from when the set value is reached to when the speed command data is reached, or from when the set value is reached until the speed command data is reached. Control signal generation circuit.