JPS608517Y2 - Current detection relay - Google Patents

Description

[Detailed description of the invention] This invention relates to a power flow detection relay that detects power flow in a power transmission system.

In a power transmission system, voltage adjustment is performed in order to maintain a constant voltage at a consumer end of the load and supply high-quality power even if the load fluctuates.

Furthermore, as the interconnection of grids progresses and the scale becomes wider and more complex, power flow control will become necessary to improve operational efficiency and safety, reduce losses, and optimize equipment.

For this purpose, it is necessary to detect power flow.

Fig. 1 is a block diagram showing the principle of a conventional power flow detection relay, in which 1 is a current transformer that transforms the grid power flow, 2 is a rectifier circuit that performs full-wave rectification of the power flow transformed by this current transformer, and 3 is a rectifier circuit that performs full-wave rectification of the power flow transformed by this current transformer. A level detection element that operates when the output of this rectifier circuit exceeds a set level; 4 a delay element that extends the operation of this level detection element by a predetermined time t1; 5 a level detection element made up of this delay element and the level detection element 3; The detector 6 is a drive circuit that energizes a determining element 7 (for example, a relay) according to the operation of the level detector, and 7a is a contact that closes when the determining element 7 is activated.

2 is a waveform diagram showing the operation of each part of the block diagram shown in FIG. 1, and a is a rectifier circuit 2. b is a level detection element 3t; c is a delay element 4. d is a waveform diagram showing each operation of the drive circuit 6. FIG.

In other words, the system power flow is transformed by the current transformer 1 and then the rectifier circuit 2
full-wave rectification.

Now, if the current that has been full-wave rectified by the rectifier circuit exceeds the set level of the level detection element 3, the level detection element 3 operates, and the drive circuit 6 is operated via the delay element 4, and the determination element 7 to support.

However, since the power flow input to the level detection element 3 is a full-wave rectified waveform as shown in waveform a shown in FIG. falls below the above set level every half cycle.

Therefore, the level detection element 3 becomes inactive every half cycle as shown in the waveform shown in FIG.

However, since the delay element 4 extends the operation of the level detection element 3 by a predetermined time t□ as shown in the waveform C shown in FIG. If this is selected, the drive circuit 6 will continue to operate as long as the system power flow exceeds the set level of the level detection element 3, as indicated by the waveform d shown in FIG.

When the drive circuit 6 operates as described above, the determination element 7 is energized, so the contact 7a is closed and the external device (not shown)
power flow control.

Next, a conventional power flow detection relay will be explained in detail with reference to a circuit diagram shown in FIG. 3 that satisfies the block diagram of FIG. 1 described above.

In Figure 3, 1 is a current transformer that transforms the grid power flow, 8A
~8D is a rectifying element, 9A~9S is a resistive element, IOA, I
OB is a variable resistance element, IIA, 11B is a capacitor, 1
2A to 12F are transistors, and transistor 12
F has a relay 13 inserted in its main circuit.

In addition, 13a is an operating contact that is closed by the operation of the relay 13, and 14 is a tap that arbitrarily selects the setting level at which this device operates. The circuit corresponding to the block shown is shown.

Next, the operation of the conventional power flow detection relay will be explained in detail with reference to FIG. 3 mentioned above.

The system power flow transformed by the current transformer 1 is transferred to the rectifier elements 8A, 8.
Full-wave rectification is performed by B, rectifying element 8C and resistor element 9D.
to the base terminal of the transistor 12A.

By the way, in normal operation, the transistor 12A is
A base current is supplied from a power source at a predetermined level via the variable resistance element 10B and the resistance element 9E, and the device is in an operating state.

Therefore, the current that can flow from the power supply at a predetermined level to the base of the transistor 12B via the resistive elements 9F and 9G flows via the resistive element 9F and the transistor 12A, so that the transistor 12B becomes inoperable.

Furthermore, since the transistor 12B is inactive, the transistor 12G is non-conductive between the collector and emitter of the transistor 12B, and is operated by being supplied with base current from the power supply at a predetermined level via the resistive elements 9I and 9J. do.

Hereinafter, based on the same principle as the operation described above, the transistor 12
D is inactive, transistor 12E is active, and transistor 12F is inactive.

Therefore, the relay 13 inserted into the main circuit of the transistor 12F is not energized because the transistor 12F is inactive and there is no conduction between its collector and emitter.

Next, when the current exceeding the set level reaches the base terminal of the transistor 12A via the rectifying element 8C and the resistance element 9D, it is thereby supplied to the base of the transistor 12A via the variable resistance element 10B and the resistance element 9E. The base current is restricted rendering the transistor 12A inoperative.

If the transistor 12A becomes inoperable, the current flowing from the power supply at a predetermined level through the resistor element 9F between the collector and emitter of the transistor 12A is blocked.
B is supplied to the base of transistor 12B to operate the transistor 12B.

Therefore, the initial operation and non-operation of each of the following transistors 12C to 12F are reversed, and the transistor 12C9 becomes
12E is inactive, and transistors 12D and 12F are active.

Therefore, relay 1 inserted in the main circuit of transistor 12F
3 is energized because the transistor 12F operates and conducts between its collector and emitter, and its contact 13
Close a.

Incidentally, the current proportional to the current flowing through the rectifying element 8C and the resistive element 9D to the base of the transistor 12A has a full-wave rectified waveform rectified by the rectifying elements 8A and 8B, as shown in waveform a shown in FIG.

Therefore, the base current that can be supplied to the transistor 12A from the power supply at a predetermined level via the variable resistance element 10B and the resistance element 9E is a current that reaches the transistor 12A via the rectifier element 8C and the resistance element 9D every half cycle of the power flow. This causes the transistor 12A to repeat operation and non-operation every half cycle of the power flow as shown in the waveform shown in FIG.

Therefore, the transistor 12B also operates in the opposite direction to that of the transistor 12A, so that it repeats non-operation and operation.

However, when a system current exceeding the set level appears, the transistor 12A becomes inoperative, and accordingly, during the period when the transistor 12C is inactive and the transistor 12D is in operation, the capacitor 11B is charged via the resistor element 9L and the rectifier element 8D. be done.

Then, when transistor 12A operates in the next half cycle,
In accordance with this, the transistor 12C operates, and the resistance element 9L is connected to the power supply at a predetermined level.

The base current of the transistor 12D, which can flow through the rectifying element 8D and the resistance element 9M, is passed between the collector and emitter of the transistor 12C via the resistance element 9L.

Therefore, the transistor 12D tries to become inoperable, but
As mentioned above, the capacitor 11B is connected to the transistor 12.
Since it is charged when C is inactive, the capacitor II
The amount of electricity charged in B can supply the base current of the transistor 12D, and the transistor 12D continues to operate.

In addition, the values (time constant) of capacitor IIB and resistance element 9M
By appropriately selecting the transistors 12A and 12C, the transistors 12A and 12C can
Even if the transistor 12D becomes inoperative, the operation of the transistor 12D continues as shown in the waveform shown in FIG.

Therefore, transistor 12E continues to be inoperative, and transistor 12F continues to operate.

Therefore, the relay 13 inserted into the main circuit of the transistor 12F is energized and closes its contact 13a, allowing power flow control to be performed by an external device connected to the contact 13a.

Note that the setting level of the detection element 3 can be arbitrarily selected by arbitrarily switching the tap 14 or by adjusting the value of the variable resistor 10B.

However, the conventional power flow detection relays described above operate when the system power flow exceeds a set level and become inactive when the system power flow falls below the set level. If the increase/decrease is repeated, relay 13 will be repeatedly energized and deenergized, and relay 1
In addition to being undesirable in terms of maintenance of the relay 13, the relay 13 also has the disadvantage of accelerating a reduction in its lifespan.

The purpose of this invention is to eliminate the above-mentioned drawbacks by inserting a control circuit combining a variable resistance element and a rectifying element into the above-mentioned conventional device and adding a history characteristic to the operation of the relay 13.

FIG. 4 is a block diagram showing the principle of an embodiment of this invention.

In FIG. 4, reference numeral 15 is a control circuit that lowers the set level of the level detection element 3 by the operation of the delay element 4, and since the other configurations are the same as the block diagram shown in FIG. 1, a description thereof will be omitted.

Further, FIG. 5 is a waveform diagram showing the operation of each part of the block diagram shown in FIG. b is the level detection element 3t; c is the delay element 4; and d is the waveform representing the operation of the drive circuit 6.

Next, the operation of the block diagram shown in FIG. 4 will be explained.

The system power flow is inputted to a rectifier circuit 2 via a current transformer 1, and the power flow is full-wave rectified by the rectifier circuit and reaches a level detection element 3.

When the level of the current exceeds the set level of the level detection element 3, the level detection element 3 is operated.

By the way, the operation of the level detecting element 3 is such that its input is the fifth one.
Since the waveform a shown in the figure is a full-wave rectified waveform of the system power flow transformed by the current transformer 1, it becomes inactive every half cycle of the system power flow.

During the non-operation period of the level detection element 3, the delay element 4 operates to extend the operation of the level detection element 3 by a predetermined time t1. (Since it is within the cycle, it is set to, for example, half the cycle of the system power flow).

Therefore, during a period when a power flow exceeding a set level appears in the system, the delay element 4 causes the drive circuit 6 to continue operating and the determination element 7 to be energized.

Further, the delay element 4 operates the control circuit 15 to lower the set level of the level detection element 3 to, for example, about 70 to 80% of the level at which the level detection element was operated.

Therefore, the level detection element 3 operates at the initially set level as shown in the waveform shown in FIG.
It becomes inactive at a level of ~80%, and the drive circuit 6 is operated via the delay element 4 as shown in the waveform d shown in FIG. 5 to energize the determination element 7.

In other words, the determination element 7 is operated in a historical manner.

Next, this invention will be explained in detail with reference to an embodiment of the invention shown in FIG. 6 which satisfies the block diagram of FIG. 4.

In FIG. 6, reference numeral 15 denotes a control circuit consisting of a variable resistance element 10C and a rectifying element 8E, which operates the transistor 12D in accordance with the operation of the delay element 4 to lower the set level of the level detection element 3.

The rest of the configuration is the same as the conventional circuit diagram shown in FIG. 3, so the explanation thereof will be omitted.

Next, the operation of the power flow detection relay of this invention will be explained with reference to FIG.

The system power flow transformed by the current transformer 1 is transmitted through a rectifying element 8A,
Full-wave rectification is performed by 8B, rectifying element 8C and resistance element 9.
D to the base terminal of the transistor 12A.

As long as the system power current does not exceed the set level, the transistor 12A flows from the power supply at the set level via the variable resistance element 10B and the resistance element 9E.
The base current overcomes the current flowing through the rectifying element 8C and the resistive element 9D to the base terminal of the transistor 12A, indicating an operating state.

When the system current exceeds the set level, the current flowing through the rectifying element 8C and the resistive element 9D to the base terminal of the transistor 12A overcomes the base current of the transistor 12A flowing through the variable resistive element 10B and the resistive element 9E. to disable the transistor 12A.

By the way, as mentioned above, since the level of the system current that makes the transistor 12A inoperable is such that the transistor 12D is inoperable, the current that can flow from the power supply at a predetermined level to the base of the transistor 12A via the variable resistance element 10B and the resistance element 9E. Since the voltage (1) is not shunted through the variable resistance element 10C and the diode 8E (I□=■3), the device operates at the same setting level as the conventional device shown in FIG.

When the transistor 12A becomes inoperative, there is no conduction between the collector and emitter of the transistor 12A, and the base current is supplied to the transistor 12B through the resistor elements 9F and 9G, and the base current is supplied to the transistor 12B through the resistor element 9■. Pass current through 12B.

Therefore, the transistor 12C becomes inoperative because the base current is not supplied, and the transistor 12E becomes inoperable and the transistors 12D and 12F become inoperable based on the same intercropping principle.

Therefore, the relay 13 inserted into the main circuit of the transistor 12F is energized and closes the contact 18a since the transistor 12F operates as described above to establish conduction between the collector and emitter of the transistor 12F.

Note that since the current that restricts the base current of the transistor 12A is a full-wave rectified waveform as shown in waveform a shown in FIG. 5, the transistor 12A repeats operation and non-operation every half cycle of the current.

However, as explained in the conventional device shown in FIG. 3 above, during a period when the grid current is set due to the charging and discharging of the capacitor IIB and the resistive element 9M and exceeds the current, the transistor 12F is replaced with the transistor 12D.

Since the relay 12E is operated via the main circuit, the relay 13 inserted into the main circuit continues to be energized.

Therefore, the contact 13a is closed, and power flow can be controlled by an external device (not shown) connected to the contact 13a.

Next, when the grid current falls below the set level, the current that reaches the transistor 12A via the rectifying element 8C and the resistive element 9D can flow from the power supply at a predetermined level to the base of the transistor 12A via the variable resistive element 10B and the resistive element 9E. The current cannot be restricted and the transistor 12A is tried to operate.

However, since the transistor 12D is operating at this time, the current □ which could be supplied to the transistor 12A is shunted to the transistor 12D via the variable resistance element 10C and the rectifying element 8E.

Therefore, the base current I3 supplied to transistor 12A
is (If-I2) and is constrained.

Therefore, if variable resistance element 10B and IOC are selected to appropriate values, even if the system power flow falls below the set level of detection element 3, transistor 12A repeats activation and deactivation to continue energizing relay 13.

Then, when the above-mentioned system power current drops further and reaches, for example, 70 to 80% of the set level at which the detection element 3 operates, the base current 3 supplied to the transistor 12A flows through the rectifying element 8C and the resistive element 9D. The transistor 12A continues to operate by overcoming the current, and the relay 13 is deenergized.

When the relay 13 is deenergized, its contact 13a is opened and the external device connected to the contact stops power flow control.

By the way, the rectifying element 8E provided in the control circuit 15 does not shunt the current that operates the transistor 12E when the transistor 12D is inactive.

In the above embodiment, the set level of the level detecting element 3 is lowered by the operation of the delay element 4, but a similar operation is expected when the set level of the level detecting element 3 is lowered by the operation of the determining element 7. can.

As described above, according to this invention, the set level of the level detecting element that operates when the system power flow exceeds the set level is determined because the set level of the above-mentioned detector is lowered by the control circuit after the level detecting element operates. The element can be controlled in a so-called historical characteristic manner, and maintenance of the above-mentioned judgment element is facilitated.
It also has the effect of suppressing the decrease in its lifespan.

Furthermore, since this invention has a delay function that maintains operation during the period when the grid power flow is below the set level every half cycle, it has the effect of allowing the control circuit to arbitrarily determine the set level lowering value of the level detector. .

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the principle of a conventional power flow detection relay, Figure 2 is a waveform diagram showing the operation of each part of this block diagram,
Fig. 3 is a circuit diagram that satisfies the block diagram shown in Fig. 1, Fig. 4 is a block diagram showing the principle of an embodiment of this invention, and Fig. 5 is the operation of each part of the block diagram shown in Fig. 4 above. FIG. 6 is a circuit diagram of an embodiment of this invention that satisfies the block diagram shown in FIG. 1 is a determination element, and 15 is a control circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] A level consisting of a full-wave rectifier circuit that performs full-wave rectification of the system power flow, a level detection element that operates when the output of this full-wave rectification circuit exceeds a set level, and a delay element that extends the operation of the level detection element for a predetermined period of time. A power flow detection relay comprising a detector, a determination element energized by the operation of the level detector, and a control circuit that lowers the set level by the operation of the determination element or the level detector.