JPS6082884U - Up-down converter - Google Patents
Up-down converterInfo
- Publication number
- JPS6082884U JPS6082884U JP17458583U JP17458583U JPS6082884U JP S6082884 U JPS6082884 U JP S6082884U JP 17458583 U JP17458583 U JP 17458583U JP 17458583 U JP17458583 U JP 17458583U JP S6082884 U JPS6082884 U JP S6082884U
- Authority
- JP
- Japan
- Prior art keywords
- down converter
- partition plate
- shield
- balanced mixer
- double balanced
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structure Of Receivers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
１１図はＣＡＴＶコンバータのダブルバランスドミキサ
一部分を示す回路図、第２図は従来のダブルバランスド
ミキサーの組付状態を示す平面図、第３図及び第４図は
本考案−実施例のダブルバランスドミキサーの組付状態
を示す斜視図及び平面図である。
１・・・ダブルバランスドミキサー回路、７・・・枠状
、シールドベース、８・・・シールド仕切板、９・・・
区画室、１２・・・ＲＦ倍信号伝送線、１５・・・局部
発振信号の伝送線、１６・・・プリント基板、１７・・
・混合された信号の伝送線。Fig. 11 is a circuit diagram showing a portion of a double balanced mixer of a CATV converter, Fig. 2 is a plan view showing the assembled state of a conventional double balanced mixer, and Figs. FIG. 2 is a perspective view and a plan view showing an assembled state of the balanced mixer. DESCRIPTION OF SYMBOLS 1... Double balanced mixer circuit, 7... Frame shape, shield base, 8... Shield partition plate, 9...
Compartment room, 12... RF double signal transmission line, 15... Local oscillation signal transmission line, 16... Printed circuit board, 17...
・Transmission line for mixed signals.
Claims (1)
した区画室内に、シールド仕切板と平行に、且つ区画室
内空間を入力側と出力側とに部分するようにダブルバラ
ンスドミキサー回路を組付けたプリント基板を配設した
ことを特徴とするアップダウンコンバータA double balanced mixer circuit is installed in a compartment formed by dividing the frame-shaped shield base with a shield partition plate, parallel to the shield partition plate, and so as to divide the compartment space into an input side and an output side. Up-down converter featuring a printed circuit board
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17458583U JPS6082884U (en) | 1983-11-10 | 1983-11-10 | Up-down converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17458583U JPS6082884U (en) | 1983-11-10 | 1983-11-10 | Up-down converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6082884U true JPS6082884U (en) | 1985-06-08 |
Family
ID=30380039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17458583U Pending JPS6082884U (en) | 1983-11-10 | 1983-11-10 | Up-down converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6082884U (en) |
-
1983
- 1983-11-10 JP JP17458583U patent/JPS6082884U/en active Pending
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