JPS6082870A - Inspection of active matrix substrate - Google Patents

Inspection of active matrix substrate

Info

Publication number
JPS6082870A
JPS6082870A JP58190224A JP19022483A JPS6082870A JP S6082870 A JPS6082870 A JP S6082870A JP 58190224 A JP58190224 A JP 58190224A JP 19022483 A JP19022483 A JP 19022483A JP S6082870 A JPS6082870 A JP S6082870A
Authority
JP
Japan
Prior art keywords
driver
active matrix
gate
matrix substrate
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58190224A
Other languages
Japanese (ja)
Inventor
Kazumasa Hasegawa
和正 長谷川
Toshiyuki Misawa
利之 三澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58190224A priority Critical patent/JPS6082870A/en
Publication of JPS6082870A publication Critical patent/JPS6082870A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836Fault-finding or characterising

Landscapes

  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To make it possible to perform various inspections prior to a panel assembling process, in a driver built-in type active matrix substrate, by providing the contact region with an external probe and a switch. CONSTITUTION:Pads 220-239 for the contact with an external probe are provided on gate wires 201-205 and data wires 206, 210 and switches 240-249 are provided between a driver 214 for driving the gate wires and the pads as well as between a driver 215 for driving the data wires and the pads. The opening and closing of the switches 240-244 and 245-249 is controlled by using external signals 250, 251 and the external probe is brought into contact with the pads to perform various inspections such as the presence and absence of the disconnection between the gate wires and data wires or the short-circuit of the gate wires and the data wires. By this method, various inspections can be performed prior to a panel assembling process.

Description

【発明の詳細な説明】 本発明け、周辺駆動回路内蔵型アクティブマトリクス基
板の検査方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing an active matrix substrate with a built-in peripheral drive circuit.

アクティツマ) I+クス型液晶表示装置の小型化、高
性能化、低コスト化のため、アクティブマトリクス基板
への周辺鳴動回路(以下ドライバーとする)の内蔵が要
求されるが、功在ドライバー内蔵型アクティブマトリク
ス基板と1.ては、単結晶シリコン基板上にMOS)ラ
ンジヌタを形成して成るもの、汲び絶縁基板上に炎嘆λ
40Sトランジヌクを形成し、て成るもの等が製作・試
作されている。
In order to reduce the size, performance, and cost of I+X type liquid crystal display devices, it is required to incorporate a peripheral ringing circuit (hereinafter referred to as a driver) into the active matrix substrate. Matrix substrate and 1. In this case, a MOS transistor is formed on a single-crystal silicon substrate, and a MOS transistor is formed on a single-crystal silicon substrate.
Products that form the 40S Transinuku are being manufactured and prototyped.

従来のドライバー内蕨、型アクティフマトリクス基板を
第1図に示す。同図1でおいて、101乃至103等は
ゲート線、104乃至107等はデータ線、110乃至
112等は画素、113及び114はゲート線tl−駆
動するドライバー、115及び116はデータ絆f駆動
するドライバーである。m1図におけるドライバー内蔵
型アクティブマトリクス某板においては、特に有効な検
査方法がなく、ドライバーのシフトレジストにおけるデ
ータ出力、汲びl°ライバーの消費電流を観測する程度
しか可能でなかった。よって、パオ、ル絹立後に各種欠
陥が発見される例が著しく、アクティブマトリクス型液
晶表示装置の低コスト化に大きく歯止め金かけていた。
FIG. 1 shows a conventional driver-type actif matrix substrate. In FIG. 1, 101 to 103, etc. are gate lines, 104 to 107, etc. are data lines, 110 to 112, etc. are pixels, 113 and 114 are gate line tl-drivers, and 115 and 116 are data bond f drives. A driver who does. For a certain active matrix board with a built-in driver in the m1 diagram, there was no particularly effective inspection method, and it was only possible to observe the data output in the shift register of the driver and the current consumption of the driver. Therefore, there were many cases in which various defects were discovered after the manufacturing process, and this greatly put a brake on the cost reduction of active matrix liquid crystal display devices.

本発明の目的は、ドライバー内蔵型アクティブマ1リク
ス基板をパネル絹立工程以前に検介し、欠陥個所まで明
らかにし、有効に以後の工程を行い、アクティブマトリ
クス型液晶表示装置の低コスト化を実用することにある
The purpose of the present invention is to inspect an active matrix substrate with a built-in driver before the panel assembly process, identify defects, and effectively carry out subsequent processes, thereby reducing the cost of active matrix liquid crystal display devices. It's about doing.

本発明の要旨は、ドライバー内蔵型アクティブマトリク
ヌ基板において、ドライバー出力部と画木部間を結ぶゲ
ートζ汲びテータ絆上に外部探針との堕胎領域(以下バ
ッドとする)を設け、該バッドとドライバー出力部間も
しくけ該バッドと画素部間にスイッチを設け、外部信号
により該スイッチの開閉を制御し、外部探針をバノHに
接触□させ、検査を行うことである。
The gist of the present invention is to provide an abortive region (hereinafter referred to as "bad") with an external probe on the gate ζ pump link connecting the driver output section and the drawing section in an active matrix board with a built-in driver. A switch is provided between the pad and the driver output section, and between the pad and the pixel section, the opening and closing of the switch is controlled by an external signal, and an external probe is brought into contact with the vano H to conduct the inspection.

以下、実施例に基づ六、本発明の詳細な説明する。Hereinafter, the present invention will be described in detail based on six examples.

第2図に本発明の実施例を示す。同図において201乃
至205けゲート線、206乃至210けデータ線、2
11乃至213等は画素、2141−tゲート線を駆動
するドライバー、215はデータ線を駆動するドライバ
ー、220乃至239け外部探針との接触用に設けたバ
ッド、240乃至249ハアナログスイツチ、250ハ
アナログスイヅテ群240乃至244の開閉を制御する
信号の入力端子、251けアナログスイ・フチ群245
乃至249の開閉を制御する信号の入力端子である。ア
ナログスイッチ群は、制御信号がハイの時に導通するよ
うになっているものとする。
FIG. 2 shows an embodiment of the present invention. In the figure, 201 to 205 gate lines, 206 to 210 data lines, 2
11 to 213, etc. are pixels, 2141-t a driver for driving the gate line, 215 is a driver for driving the data line, 220 to 239 are pads provided for contact with an external probe, 240 to 249 are analog switches, 250 Input terminal for signals that control opening/closing of analog switch groups 240 to 244, 251 analog switch edge group 245
This is an input terminal for a signal that controls the opening and closing of 249 to 249. The analog switch group is assumed to be conductive when the control signal is high.

まず制御信号入力端子250及び251の1行位をロー
にすると、アナログスイッチ240乃至249け全て非
導通となる。そこで外部探針を辿じ、バッド220及び
225を通してゲートI%+201の抵抗を測定するこ
とによりゲート線201の断線の有無が検査可となる。
First, when the first row of control signal input terminals 250 and 251 is made low, all analog switches 240 to 249 become non-conductive. Therefore, by tracing the external probe and measuring the resistance of the gate I%+201 through the pads 220 and 225, it is possible to check whether or not the gate line 201 is disconnected.

同様にバッド221及び226.222乃び227等を
通した抵抗測定によりゲート線202.203等の断線
の有無、バッド230及び2′55.261及び236
等を通しfc抵抗測定によりデータ線206.207等
の断線の有無が検を可と方る。また、バッド220と、
230間の抵抗測定により、ゲート線201とデータ線
206間の上下短絡の有無が検査可となる。同様にバッ
ド220と231,232等との間の抵抗沖1定により
、ゲート線201とデー4線207 、208等の上下
短絡の有無が検査可となり、これらの繰り返しによりゲ
ート線とデー4線の全ての交点における上下短絡の有無
が検介可となる。そして、以上の検査でθ好な基板のみ
について制御信号入力端子250及び251の電位をハ
イにしてアナログスイッチ群を導通させ、ドライバー2
14及び215を動作させると、バッド220乃至22
4を通じゲート側ドライバー214の出力波形、バッド
230乃至234を通じデータ側ドライバー215の出
力波形が観d用できる。
Similarly, by measuring the resistance through the pads 221 and 226, 222 and 227, etc., the presence or absence of disconnection in the gate lines 202, 203, etc., was determined through the pads 230, 2'55, 261, and 236.
It is possible to detect whether or not the data lines 206, 207, etc. are disconnected by measuring the fc resistance. Also, with Bud 220,
By measuring the resistance between the gate line 230 and the data line 230, it is possible to check whether there is a vertical short circuit between the gate line 201 and the data line 206. Similarly, due to the constant resistance between the pads 220 and 231, 232, etc., it is possible to check for vertical short circuits between the gate line 201 and the data 4 wires 207, 208, etc., and by repeating these steps, the gate line and the data 4 wires 207, 208, etc. The presence or absence of vertical short circuits at all intersection points can be checked. Then, for only the board with good θ in the above inspection, the potential of the control signal input terminals 250 and 251 is set high to make the analog switch group conductive, and the driver 2
14 and 215, the bads 220 to 22
The output waveform of the gate side driver 214 can be viewed through pads 230 to 234, and the output waveform of the data side driver 215 can be viewed through pads 230 to 234.

第6図に本発明のもう一つの実施例を示す。同図におい
て、301乃至305はゲート線、306乃至610は
データ線、611乃至313等は画素、614及び61
5けゲート線を駆動するドライバー、316及ヒ517
はデータ線を駆動するドライバー、320乃至339は
外部探針との接触用パ・ド、640乃至3591″1ア
ナログスイツチ、360. 561. ろ62及び36
6はそれぞれアナログスイッチ群340 乃至3443
45乃至349. 350乃至354及び355乃至3
59の開閉を制御する信号の入力端子である。
FIG. 6 shows another embodiment of the invention. In the figure, 301 to 305 are gate lines, 306 to 610 are data lines, 611 to 313 are pixels, and 614 and 61 are data lines.
Driver for driving 5 gate lines, 316 and 517
is a driver that drives the data line, 320 to 339 are pads for contact with the external probe, 640 to 3591''1 analog switch, 360. 561. 62 and 36
6 are analog switch groups 340 to 3443, respectively.
45 to 349. 350 to 354 and 355 to 3
This is an input terminal for a signal that controls the opening and closing of 59.

まず、制御信号入力端子36G乃至3630雷位をロー
にして、アナログスイッチ340乃至359を全て非導
通とすることにより、ゲート線301乃至305とデー
タ線606乃至610の交点における上下短絡の有無が
検査可となる。上下短絡検査について良好な基板の入に
ついて制御信号入力端子360の電位全ハイにすると、
ゲート側ドライバー614の出力波形が観測できる。ま
た、制御信号入力端子360の電位をロー、361の電
位をノ・イとすることにより、ゲート側ドライバー31
5の出力波形が観測できる。同様にして、データ側ドラ
イバー316及び317の出力波形がそれぞれ独立に観
測可能となる。
First, by setting the control signal input terminals 36G to 3630 low and making all the analog switches 340 to 359 non-conductive, the presence or absence of a vertical short circuit at the intersection of the gate lines 301 to 305 and the data lines 606 to 610 is inspected. Yes. Regarding the inspection of upper and lower short circuits, when the potential of the control signal input terminal 360 is set to full high for good board insertion,
The output waveform of the gate side driver 614 can be observed. In addition, by setting the potential of the control signal input terminal 360 to low and the potential of the control signal input terminal 361 to no, the gate side driver 31
5 output waveform can be observed. Similarly, the output waveforms of the data side drivers 316 and 317 can be observed independently.

ところで第3図において、例えばゲート側ドライバー3
15の動作が不良であつ斤とする。この相合、制御信号
入力端子361の電位をローK t、てアすUグヌイッ
チ345乃至549f非導通とすることにより、ゲート
側ドライバー314の入でゲート線301乃至305を
駆動することがで入る。すなわち制御信月の操作1つで
欠陥救済が可能となる。この場合、さらにアナログスイ
ッチ340乃至344f非導通とすることにより、ゲー
ト線301乃至305の断線の有無が検育可となる。
By the way, in FIG. 3, for example, the gate side driver 3
15 is malfunctioning. In this phase, by setting the potential of the control signal input terminal 361 to low Kt and setting the U Gnuit switches 345 to 549f non-conductive, the gate lines 301 to 305 can be driven by the input of the gate side driver 314. In other words, defects can be repaired with a single operation of the control signal. In this case, by further turning off the analog switches 340 to 344f, it is possible to detect whether or not the gate lines 301 to 305 are disconnected.

対上述べた如く、本発明を用いることにより、ドライバ
ー内蔵型アクティブマトリクス基板の各科検査及び簡単
な欠陥救済が可能となり、有効に欠陥修正もしくけ後工
程を行うことが可能となりアクディプマ) 11クス型
液晶表示装置の低コスト化が丈覗これる。
As described above, by using the present invention, various inspections and simple defect relief of active matrix substrates with built-in drivers are possible, and it is also possible to effectively correct defects and perform post-processing. The cost reduction of LCD display devices is expected to continue.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来のドライバー内蔵型アクティブマトリク
ヌ峡板を説明するための図。 第2図は、本発明の詳細な説明する゛ための図。 第3図は、本発明のもう1つの実施例を説明するための
図。 以 上
FIG. 1 is a diagram for explaining a conventional active matrix plate with a built-in driver. FIG. 2 is a diagram for explaining the present invention in detail. FIG. 3 is a diagram for explaining another embodiment of the present invention. that's all

Claims (1)

【特許請求の範囲】[Claims] 複数本のゲート線、該ゲート線に直交する複数本のデー
タ線、前記ゲート線及びデータ線の交点に設けfr、 
M OS l−ランジスタによる画素部、及び周辺、’
!ty、 1lrh回路よりIj!+る周辺駆動回路内
蔵型アクティブマトリクス基板において、周辺部ルh回
路出力部と画素部間を結ぶゲート線及びデータ線上+C
外ざ](探測との接触舶載を設け、該接触領域と周辺部
1i1+回路[1)1もしく’ fd該接触領域と画素
部間にヌイー・−/−を設け、外部信号により該スイッ
チの開閉を制御し2、外部探測を該接触クロ域に吸触さ
せ、検査を行うことを特徴とするアクティブマトリクス
基板の検査方法。
a plurality of gate lines, a plurality of data lines perpendicular to the gate lines, fr provided at the intersection of the gate lines and the data lines,
Pixel part and surrounding area by MOS l-transistor,'
! ty, Ij from the 1lrh circuit! In an active matrix substrate with a built-in peripheral drive circuit, +C on the gate line and data line connecting the peripheral circuit output section and the pixel section.
Outer area] (Provide a contact ship with the probe, and connect the contact area and the peripheral area 1i1+circuit [1)1 or ' fd Nui -/- between the contact area and the pixel area, and connect the switch with an external signal. 2. A method for inspecting an active matrix substrate, comprising: controlling the opening and closing of the active matrix substrate;
JP58190224A 1983-10-12 1983-10-12 Inspection of active matrix substrate Pending JPS6082870A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58190224A JPS6082870A (en) 1983-10-12 1983-10-12 Inspection of active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58190224A JPS6082870A (en) 1983-10-12 1983-10-12 Inspection of active matrix substrate

Publications (1)

Publication Number Publication Date
JPS6082870A true JPS6082870A (en) 1985-05-11

Family

ID=16254544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58190224A Pending JPS6082870A (en) 1983-10-12 1983-10-12 Inspection of active matrix substrate

Country Status (1)

Country Link
JP (1) JPS6082870A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63272046A (en) * 1987-04-21 1988-11-09 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method of testing display device and display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63272046A (en) * 1987-04-21 1988-11-09 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method of testing display device and display device

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