JPS6080200A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the size of a fuse ROM within a memory chip by using a fuse ROM containing transistors connected to an end of each fuse respectively and a fusing pad connected in common to the other end of each fuse. CONSTITUTION:A memory cell array is provided together with a redundant memory cell which is provided in the array and substitutes a faulty memory cell, plural address input pads 23-0-23-n which receive addresses to designate prescribed cells within the array, and a fuse ROM having same bit pattern as the address corresponding to the faulty memory cell. An access is given to the redundant memory cell when an address equal to the bit pattern within a fuse ROM3 is received. The fuse ROM contains fuses 12-0-12-n which form a bit pattern by fusing, transistors 22-0-22-n which are connected in series to the other end of each fuse 12-i respectively and a single fusing pad 21 which is connected to the other end of each fuse 21-i. The gates of the transistors are connected to corresponding pads 23-0-23-n respectively.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor memory device with redundant memory cells in 1% of the semiconductor memory device.

Background of the Technology In recent years, the degree of integration of semiconductor memory devices has increased dramatically. For example, 256 kbit memory is also entering the practical stage. In such highly integrated semiconductor memory devices (hereinafter simply referred to as memories), the probability of including defective memory cells also increases.

Therefore, when there are several defects, the defective memory cells are replaced by redundant memory cells prepared in advance without discarding the memory chip. In use, when the address comparison circuit detects that the defective memory cell has been addressed, the memory cell is skipped to the redundant memory cell. Here, the address comparison circuit is connected to the normal external address input and the fuse ROM.
(readonly memory) is compared to detect a match between the two. The fuse ROM holds the address of the defective memory cell in a fixed manner.

The present invention primarily refers to such a fuse ROM.

Prior art and problems Figure 1 shows a fuse RO provided in a semiconductor memory device.
FIG. 2 is a circuit diagram showing a conventional configuration example of M. In this figure, 1
2-0.32-1 and 12-n each beep) B
,, B, . . . are fuses corresponding to BrL, and show a blown state for bit B.

All of these constitute a fuse ROM. The fuse ItOM thus formed represents the address of the defective memory cell. Therefore, in a later step, the RO
Necessary wiring for taking out a certain address bit output from M (not shown) leads to the address comparison circuit described above.

An object of the present invention is how to blow out the fuses 12-0 to 12- in accordance with the address of the defective memory cell. In the conventional fuse ROM shown in FIG. 1, first,
Fusing pad 11-0.11-1 for each fuse.
- Provide a 11-hole and apply a high enough voltage to selectively fuse any of the pads (11-Q...11-L) connected to the fuse you want to blow.This fusing operation is performed on the wafer before packaging. Therefore, it is made about the memory tip.

The pads 11-0...11-71 become ε-pads after being packaged. However, each of these dummy pads requires a large area S, and
A total area of ('7L+1)S is required.

This is clearly a problem despite the high integration of memories.

Purpose of the Invention In view of the above problems, the present invention provides a fuse R that requires less area.
An object of the present invention is to provide a semiconductor memory device equipped with an OM.

Structure of the Invention In order to achieve the above object, the present invention includes transistors connected in series to one end of each valley fuse, and a single blowing pad commonly connected to the other end of each fuse, The present invention is characterized in that a plurality of address input pads that are originally normal are also connected to the gate terminals of the corresponding transistors.

Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 2 is a circuit diagram showing an example of the basic configuration of a fuse ROM provided in a semiconductor memory device according to the present invention.

In this figure, 12-0...124 are the fuses mentioned above, and the fuses 12-1 and the like are assumed to be blown later. Transistors 22-0.22-1...22-n- are connected in series to one end of each fuse. The other ends of the valley fuses are commonly connected to a single fusing pad 21. Furthermore, each transistor 22-0...22-f
Each gate of L has a corresponding address input pad 23-0.
23-L...Connected to 23-L. These address pads 23-0°23 to 1 . , A4...ATL is applied. To designate this memory, these addresses are input to the decoder DEC during normal memory use.

On the other hand, at the memory manufacturing stage, the address corresponding to the defective memory cell (Ao...ATL) is given to the address pad 23-0.23-1...23-fL, and the same bit pattern as that address is given. , turns on or off the transistors 22-0.22-1...22-. Here, when a high voltage is applied to the blowing pad 21, only the fuses connected to the transistors in the on state are blown with the bit pattern, and the fuse ROM 2
0 is formed.

Comparing the fuse ROM shown in FIG. 2 with the fuse ROM shown in FIG.
-0...1l-rL (Fig. 1). Here, the degree of memory integration t increases significantly.

The reason for this is that a plurality of pads (it-o, 1t-rL) corresponding to the addresses shown in FIG. i pad 2
This is because it was replaced with 1. Single pad 2 like this
The LK was made possible by using the original address input pads 23-0...23- and providing gates connected to each of them.

Transistors corresponding to addresses 22-0.22-1...
This is because 22-rules were established. In this case, the area required to form the transistors 22-0...22-.

Although an extra area is required for wiring each gate and each address manual pad, this is compared to drastically reducing the pad area from (rL+1)S to S.

This is an increase in area that is hardly a problem.

FIG. 3 is an overall diagram of the memory configuration for explaining the positioning of the fuse ROM shown in FIG. 2.

In this figure, 31 is a memory cell array (MCA), which also includes redundant memory cells to replace defective memory cells. The row decoder (RDEC) 32-R and column decoder (CD
EC) 32-C, and the row side redundant cell driver 33-R and decoder 34-R select redundant memory cells.
R, a column-side redundant cell driver: 33-C, and a decoder 34-C.

, these decoders 32-1ζ, 32-C, 34-R, 3
4-C is driven by address Ai (A shown in Figure 2.
The address input pads 23-0...z3-yz shown in FIG.
(only an arbitrary one 23-i is shown).

Note that row system drive and column system drive are RAS (ro
w address 5trobe) signal and CAS
(column address atro, be) signals, the timings are shifted from each other and selection is made alternately. The external address Ai is stored in the address buffer (AD
B) 35 allows complementary internal addresses A' and A
i becomes.

These addresses A'i Ai are sent to the decoder 32-R.

The signal is supplied not only to 32-C but also to the previously described address comparison circuits (36-R on the row side and 36-C on the column side). One fuse ROM 37-R (low side) referred to in the present invention is connected to each first comparison input of the circuits 36-R and 36-C.
and 37-C (column side) (both are 20 in Fig. 2)
(equivalent to ) is applied. However, the figure does not depict any one of the redundant address outputs (a7-R, a7-0) L.

When the externally given address matches the fuse ROM address, the row side switch 38-R and column side switch 38-C are switched to the redundant side, and the word driver output WD and column enable clock CE are respectively set to the decoder. 34-R and 34-C to access redundant memory cells.

FIG. 4 is a circuit diagram partially showing a detailed example of the fusel OM according to the present invention, and FIG. 5 is a waveform diagram used to explain the operation of the circuit of FIG. 4. Figure 4 is 1 in Figure 2.
Although only the bit system (L-th bit) is depicted, all other bit systems have the same configuration. Also, the transistor z2-i in FIG. 4 (any one in FIG.
(transistor) + IVR pad 21. Redundant address output aL Internal address "A'z Fuse 1z-i (any one fuse in FIG. 2) is as already explained in FIG. 2 or FIG. 3.

Whether or not to melt the wax type heats and whether to melt the column type heats depends on (1) and <2) K in Figure 5.
It is determined by the timing of the RAS signal and CAS signal shown in FIG. The operation is the same for either system. Whether or not to blow fuse 1z-i is determined by internal address A'iC.
It is determined by the logic in (8) in Figure 5. "Hll", the transistor 41 is on, the transistor 22-i is off, and the fuse 12-i remains as it is.
If so, fuse 12-L will be destroyed.

The operation begins with the CO double signal ``H'' ((4) in FIG. 5). This turns on the transistor 42, and a voltage of V.0 is applied to the capacitor 43 via the transistor 42'. charged.Then the auxiliary fusing pad 44
For example, a voltage of 7 to 10 cm is applied. Here is the bootstrap minute effect.

Through the transistor 45 which is turned on, the node N
Increase the voltage to 10-odd V. After raising the voltage by more than 10 V, the AD double signal (5) in Figure 5 is added to the transistor 4.
6 is turned on, the gate potential of the transistor 45 is lowered, and the transistor 45 is turned off. If it is not turned off, the transistor 41 will be turned off later by the address Ni.
When 7z+ is turned on, a large DC current -t! flows through the entire transistor 45 from the pad 43 (to which 7~IOV is applied). x will flow. In addition, to node N
The transistor 22-1 applies the high voltage @V.
This is to enable sufficient turn-on.

If the address A'1 (TTTj/bell) were to be applied directly to the gate of the transistor 22-i, the transistor 22-i would not be turned on sufficiently, and there is a risk that the fuse would fail to blow.

Changes in the CO signal, AD scratch signal, and external address Ai (
Appears around (7) in Figure 7, r AL passes through the address buffer (35 in Figure 3) to the internal address AI,
((8) in Figure 5). Here A'2 is °“L”
If so, the transistor 22-2 is turned on, and
High voltage HV from fusing pad 21 (Fig. 5) (6)'
) R, for example 14V, is applied to the heat source 12-L, and a large current flows to fuse it.

When A' is "■work", the potential of node N decreases.

Since the transistor 22-i is turned off, such a large current does not flow, and the fuse 1z-i extends to its casing.

During normal operation of the memory, the power supply Voo is applied to the transistors connected to the unblown fuses, and a logic ``H'' signal is applied to the address comparison circuits (36-R, 36-C), and the remaining All addresses are logical
This is L”.This H”.

When the "L" bit pattern matches the bit pattern of the external address, that is, when a defective memory cell is accessed, the process jumps to the redundant memory cell.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, a semiconductor memory device is realized in which the size of a fuse ROM occupying a memory chip is significantly reduced compared to the conventional one.

[Brief explanation of the drawing]

Figure 1 shows a fuse RO provided in a semiconductor memory device.
FIG. 2 is a circuit diagram showing an example of the basic configuration of a Hi-Ni-Z ROM based on the present invention provided in a semiconductor memory device, and FIG. An overall diagram of the memory configuration for explaining the positioning of the HUNYZ ROM, FIG. 4 is a detailed diagram of the HUNYZ ROM according to the present invention.
FIG. 5 is a waveform diagram used to explain the operation of the circuit shown in FIG. 4. 12-0. 12-1 ・124-... Hughes. 20...Fuse ROM, 21...Bud for fusing. 22-0.22-1---22-n,--transistor. 23-0.23-1...2 knees 14...Address human power pad. 31...Memory cell array. 37-R, 37-C...Fuse ROM0 Patent applicant Fujitsu Ltd. Patent application agent Patent attorney Akira Ikuki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yukio Patent attorney Akiyuki Yamaguchi Figure 1 Figure 2 figure ,. Δo At An

Claims (1)

[Claims] 1. A memory cell array and a redundant memory cell to replace a defective memory cell in the memory cell array. a plurality of address input pads for receiving an address specifying a predetermined memory cell in the memory cell array; and a heater RO,M having a bit pattern identical to the address corresponding to the defective memory cell; The fuse IζOM has a configuration in which the redundant memory cell is accessed when the address that is the same as the bit pattern in the fuse ROM is received, and the fuse IζOM is connected to a plurality of fuses that form the bit pattern by blowing. ,
It consists of a transistor connected in series to one end of each fuse, and a single blowing pad commonly connected to the other end of each fuse, and the gate of each transistor is connected to the corresponding address input pad. I hope it will leak
A semiconductor memory device having l+f characteristics.