JPS6080196A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten the access time by connecting a means to each word line for its inactivation when a synchronizing signal is produced. CONSTITUTION:A word line to be selected is changed to WLm from WL0 in response to the change of a row address. This address change is detected by a detector 10 and synchronizing signals 21 and 22 of the detection output are set at high levels. Then a bit line equalizing gate 11 is conducted by a signal 21, a pull-down transistor 13 is conducted by a signal 22, and the word line voltage is set at a low level at a point near the termination of a word line. As a result, a memory cell 3a becomes inactive and the equalization of a bit line is completely performed through the gate 11. While the voltage of the line WLm rises up with a low level of the signal 22. When the signal 21 has a low level, the data on a memory cell 3b appears at the bit line. Then the 1/0 cross is detected by a sense amplifier 8, and the output Do of a buffer 9 is changed to ''1'' from ''0''.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device with short access time, and particularly to an internally synchronous static RAM.

[Prior art]

Hereinafter, a static RAM will be explained as an example of a semiconductor memory device.

In order to shorten the access time and power consumption of static RAM, a method has already been developed in which a change in an address signal is detected and a single synchronization signal is generated. A static RAM employing this method is called an internally synchronized static RAM, and an example thereof is shown in FIG. In the figure,
β is a row address signal, 1 is a row address buffer, and 2 is a row that selects only one of (m+1) word lines (WLO to W L m ) according to the output signal of row address buffer 1. Decoder, 3 is (m+1) rows, (n+1)
Memory cells arranged in a matrix of columns, 4 (n-
1-1) Pair of bit lines (Bl-0, BLO~13Ln,
BLn), 5 is a transfer gate that connects the bit line pair and I10 line pair (110°l10), and 6 is a pair of transfer gates in response to a column address signal (not shown). Column decoder that selects and conducts 5th eye, 7 is I10 line load, 8bal1
A sense amplifier 9 detects and amplifies the accumulated data of the memory cell 3 appearing on the 0 line, and 9 is an output sofa. In addition, 10 detects a change in the row address and generates a single synchronization signal (8 ddr
ESS Transition Detect (hereinafter referred to as ATD signal);
1 is a bit line equalization gate (potential balancing means) which is provided between a pair of complementary signal lines forming each of the two bit lines and receives the ATD signal as a gate input, and 12 is an ATD.
This is an I10 line equalization gate that receives a signal as a gate input.

As the address change detector 10, for example, there is a logic circuit as shown in FIG. In the figure, 10a is a delay circuit provided for each row and delays an input row address signal by a predetermined time, and 10b is a row address signal delayed by a predetermined time, which is the input row address signal and the output of the delay circuit 10a. An exclusive OR circuit whose input is I
OC is an OR circuit which inputs the output of each exclusive OR circuit 10b and outputs an ATD signal.

Next, a read operation when the row address changes and the selected memory cell changes from memory cell 3a to memory cell 3b will be described. The data stored in each memory cell is
Memory cell 3a is "0".

Assume that memory cell 3b is "1". Figure 3 shows the transient changes in each voltage. As the row address changes, the row address buffer 1 and row decoder 2 operate, and the selected word line changes from WLO to W L m. However, since the word line is generally made of polysilicon having a high sheet resistance, the response at the end where the memory cells 3a and 3b are located is slow as shown in FIG. At this time, if the ATD signal is detected by the address change detector 10, the address change detector Ili
gh, the bit line equalization game) 11 becomes conductive,
The potential difference between complementary signal lines BLn and BLn forming the pick line decreases. However, since the word line WLO is still II i Hb, a slight potential difference remains due to the memory cell 3a. Then, when the ATD signal becomes Low, the data stored in the memory cell 3b appears on the bit line, and the signal line B
The levels of Ln and BLn intersect. The sense amplifier 8 is
The l10 line (110
, l10) is detected, and as a result, the exit cover sofa 9
operates, and the output signal DO changes from 0 to 1°.

In such a device, the ATD as shown by the broken line in FIG.
Compared to the case where no signal is generated, the signal line B
It can be seen that the time at which the levels of Ln and BLn intersect becomes faster, and the access time is shortened accordingly. It is preferable that the ATD signal goes low at the same time as the levels of each word line WLO and WLm intersect; if it is later than that, the data in the memory cell 3b will not appear on the bit line. If it is earlier than that, the data in the memory cell 3a will appear on the bit line again and the equalization effect will be lost.

Conventional internally synchronized static RAM is configured as described above, and the word line selected in the previous cycle maintains the quantizer gl+ voltage for a while even after the address changes, so even if the bit line is equalized with the ATD signal, the voltage will be slightly lower. A potential difference of remains,
Furthermore, if the ATD signal is set to low, the equalization effect is lost, and the purpose of shortening the access time cannot be achieved.

[Summary of the invention]

This invention has been made to eliminate the drawbacks of the conventional ones as described above, and by providing means connected to each word line to inactivate each word line when an ATD signal is generated, the access time can be reduced. It is an object of the present invention to provide a semiconductor memory device that can shorten the length of time.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 4, reference numeral 13 indicates a transistor (word line inactivation/activation means) provided at the end of the word lines WLO to WLm as a pull-down gate, which is connected to the second internal synchronization signal (second ATD). signal) 22 is used as a gate input. Here, the area required for this transistor 13 is small. Further, the other configurations are the same as those in FIG. 1.

Next, the operation when the selected memory cell changes from memory cell 3a to memory cell 3b will be described.

FIG. 5 shows the transient changes in the voltages at various parts, and now the stored data in the memory cells 3a and 3b are "0" and "0", respectively.
1". First, as the row address changes, the selected word line changes from the word line WLO to the word line W1., m. At this time, the address change detector IO detects the address change, As a result, the first ATD signal 21 and the second ATD signal 22 output from the detector IO become the old gh.Then, the first ATD signal 21 makes the bit line equalize gate 11 conductive, and the bit line equalize gate 11 becomes conductive. The pull-down transistor 13 becomes conductive due to the ATD signal 22 of 2, and the word line voltage near the end of the word line becomes Lo.
- level. This speed is fast because the polysilicon resistance of the word line is ignored. As a result, memory cell 3a
becomes inactive, and the bit line equalization by the bit line equalization gate 11 is completed.

When the second ATD signal 22 becomes low, the voltage of the selected word line WLm starts to rise, and then when the first ATD signal 21 becomes low, the data in the memory cell 3b is transferred to the bit line (BLn). , BLn). The subsequent operation is exactly the same as the conventional one, and the sense amplifier 8 is connected to I10.
The crossing of the lines is detected, whereby the output cover sofa 9 operates and the output signal DO changes from 0 to 1.

Here, the word line voltage near the row decoder 2 is originally Lo-
The level is quickly reached, so there is no need to provide the pull-down transistor 13.

In the device of this embodiment, the pull-down transistor 13 is provided to once set the potential of each word line to a completely low level when the address changes, so that the bit line equalization is completely performed and the focus is maintained. line and I1
The time required for crossing the 0 line and inverting the sense amplifier can be significantly shortened. Furthermore, since the data in memory, reset, and 3a will not appear on the bit line again, the first
TD Shin 3? The timing at which -zi is set to Lo- can be made earlier, and the access time is shortened accordingly.

Here, since the word line voltage near the transistor 13 is also fixed to Low until the second ATD signal 22 becomes Low and the word line pull-down transistor 13 becomes non-conductive, the pulse width of the second ATD signal 22 It is desirable to set the value to the minimum value that allows the word line to be pulled down. On the other hand, since the data of the memory cell appears on the pin line only when the word line voltage becomes -1x higher than the threshold voltage of the transistor constituting the memory cell, the first ATD signal 2
Even if the timing at which 1 becomes low is later than the timing at which the second ATD signal 22 becomes low by the time required to charge the word line to the threshold voltage, the access time will not increase.

Another effect of pulling down the word line using the internal synchronization signal is the address seven sotoamp time (T
There is an improvement in su(A)). Here, this Tsu(A
) is the address change (
This is the delay time from the cycle change) to the application of the decay control signal. By pulling down the word line, the selected memory cell of the previous cycle is quickly deactivated and becomes insensitive to the write signal of the next cycle, so Tsu(A)
margin increases.

In the above embodiment, one word line pull-down transistor is provided at the end of each word line, but 11ira or a plurality of transistors may be provided between the start end (row decoder) and the end.

Furthermore, in the above embodiment, the timing for setting the first ATD signal to Low is set to be later than that of the second ATD signal. It may be done at the same time. The second ATD signals may be the same signal. Furthermore, in the above embodiment, not only a lead line pull-down transistor but also a bit line equalization gate is provided, and both of these are used to reduce access time. However, in the present invention, the read Only a line pull-down transistor may be provided, and even in this case, there is an effect of improving Tsu(A). As described above, according to the semiconductor memory device of the present invention, the word line By connecting deactivation means to each word line, each word line becomes completely deactivated once the address changes, so the access time is significantly shortened, and the address center amplifier This has the effect of increasing the time margin.

[Brief explanation of the drawings] Figure 1 shows the conventional internally synchronized static I? A block diagram showing the configuration of AM, FIG. 2 is a logic circuit diagram showing an example of the address change detector of the device, and FIG. 3 is a timing diagram for explaining the operation of the conventional internally synchronized static R,AM. , FIG. 4 is a program diagram showing the structure of an internally synchronous static RAM which is a semiconductor memory device according to an embodiment of the present invention.
FIG. 7 and FIG. 5 are timing diagrams for explaining the operation of the RAM shown in FIG. 4. 2... Row decoder, Mikawa memory cell, 1o... Address change detector, 11... Bit line equalize gate (potential balancing means), ]3... Word line pull-down gate 1. (Word line deactivation means), BLO, BLO~
B L n, B L, n-pi 1- line, W I-0 ~
WLm...Word line. In the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 2 Figure 3 Figure 4

Claims (1)

[Scope of Claims] (1) A plurality of memory cells arranged in a matrix, a plurality of bit lines provided in each column, and memory cells provided in each row are activated. A row decoder that selectively activates one of the plurality of word lines by decoding a coded row address signal; an address change detector that detects a change in an address signal and generates a synchronization signal; and word line deactivation means that is connected to each of the word lines and deactivates each of the word lines using the synchronization signal. A semiconductor memory device comprising: +21 Each of the bit lines 1 consists of a pair of complementary signal lines, and the pair of complementary signal lines are connected by potential balancing means that receives the synchronizing signal and reduces the potential difference between the complementary signal lines. A semiconductor memory device according to claim 1, characterized in that: (3) The semiconductor memory device according to claim 2, wherein the operation of the word line deactivation means ends before the operation of the potential balancing means ends.