JPS6079762A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JPS6079762A JPS6079762A JP58186705A JP18670583A JPS6079762A JP S6079762 A JPS6079762 A JP S6079762A JP 58186705 A JP58186705 A JP 58186705A JP 18670583 A JP18670583 A JP 18670583A JP S6079762 A JPS6079762 A JP S6079762A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- wiring
- aluminum
- layer
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
コノ発明は、電極技術に関し、ポンディングパッドを有
する半導体集積回路装置に適用して有効な技術に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an electrode technology, and relates to a technology that is effective when applied to a semiconductor integrated circuit device having a bonding pad.
半導体集積回路において、内部の機能回路と外部回路を
接続させるためのポンディングパッド（外部引出し端子
）の構造として、本発明者は第１図および第２図に示す
ようなものを考えた。In a semiconductor integrated circuit, the present inventor considered the structure of a bonding pad (external lead terminal) for connecting an internal functional circuit and an external circuit as shown in FIGS. 1 and 2.
すなわち、半導体基板１の主面上に形成された酸化膜（
Ｓｉｎ、膜）や窒化膜（Ｓｉ、ＩＮ、膜）あるいはＰＳ
Ｇ膜（リン・シリコン・ガラス膜）のような層間絶縁膜
２上に、アルミ配置ｓ３と連続されたポンディングパッ
ド４を形成する。つまり、層間絶縁膜２に対し、素子の
活性領域との接触をとるためのコンタクトホール（図示
省略）火形成してから、基板表面全体にアルミニウムを
蒸着させ、これをホトエツチングすることにより、形成
されるアルミ配［３と同時にポンディングパッド４を形
成しようというものである。That is, the oxide film (
Sin, film), nitride film (Si, IN, film) or PS
A bonding pad 4 continuous with the aluminum arrangement s3 is formed on an interlayer insulating film 2 such as a G film (phosphorous silicon glass film). That is, a contact hole (not shown) is formed in the interlayer insulating film 2 to make contact with the active region of the element, and then aluminum is deposited on the entire surface of the substrate and then photo-etched. The idea is to form the bonding pad 4 at the same time as the aluminum plate 3.
ところが、上記のような構造のボンディングバラドにあ
り又は、ボンディングワイヤ５とのボンディング（接続
）を可能とするため、アルミ配線３上に形成される保護
用のパッシベーション膜６に開口部７が形成され、ポン
ディングパッド４の中央部が露出される。そのため、パ
ッケージングされた後に、パッケージ内に侵入した水分
により１ポンデイングパツド４を構成するアルミニウム
が腐食されるおそれがある。特に、最近は、コストダウ
ンを図るためパッケージ材料として水が侵入し易いプラ
スチックが用いられるようになって来ているので、水に
よるポンディングパッドの腐食が起き易くなる。この場
合、第２図に斜線Ａで示すような箇所において、ポンデ
ィングパッド４の腐食が生じただけではそれほど問題は
ないが、同図斜線Ｂで示すようなパッド４と配線３との
接続部で腐食が生じると、腐食による断線等の致命的な
トラブルが発生するおそれがあることが分かった。However, in the bonding pad having the above structure, an opening 7 is formed in the protective passivation film 6 formed on the aluminum wiring 3 in order to enable bonding (connection) with the bonding wire 5. , the center portion of the bonding pad 4 is exposed. Therefore, after packaging, there is a risk that the aluminum constituting the one-pounder pad 4 will be corroded by moisture that has entered the package. In particular, recently, in order to reduce costs, plastics, which are easily penetrated by water, have come to be used as packaging materials, so that the ponding pads are more likely to be corroded by water. In this case, corrosion of the bonding pad 4 only occurs in the area shown by the diagonal line A in FIG. 2, but this is not a major problem, but the connection between the pad 4 and the wiring 3 as shown by the diagonal line B in the figure does not cause much of a problem. It has been found that if corrosion occurs, there is a risk of fatal problems such as wire breakage due to corrosion.
この発明の目的は、従来に比べて顕著な効果を奏すゐ電
極技術を提供することにある。An object of the present invention is to provide an electrode technology that exhibits remarkable effects compared to the prior art.
この発明の他の目的は、ポンディングパッドの開口部か
ら水分等が侵入してパッドを構成するアルミニウムが腐
食されても、内部回路と接続されり配線とホンディング
パッドとの間の電気的接続が遮断されないようにするこ
とにある。Another object of the present invention is to maintain electrical connection between wiring and the bonding pad so that even if moisture or the like enters through the opening of the bonding pad and corrodes the aluminum constituting the pad, the connection to the internal circuit can be maintained. The goal is to ensure that the system is not blocked.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、この発明は、配線と同時に形成されるポンデ
ィングパッドのアルミニウム層の下に、予め耐食性の良
好な金属もしくはそのような金属のシリサイド（シリコ
ン化合物）等からなる導電層を形成し℃おいて、この導
電層を介して間接的に配線とポンディングパッドとを接
続させるように構成することにより、アルミニウム層か
らなるポンディングパッドが多少腐食されても、その下
の耐食性導電層が腐食に対するストッパとなって、ポン
ディングパッドと配線との間の電気的接続が遮断されな
いようにするという上記目的を達成するものである。That is, in this invention, a conductive layer made of a metal with good corrosion resistance or a silicide (silicon compound) of such metal is formed in advance under the aluminum layer of the bonding pad that is formed at the same time as the wiring, and then the conductive layer is heated at ℃. By configuring the wiring and the bonding pad to be connected indirectly through this conductive layer, even if the bonding pad made of an aluminum layer is slightly corroded, the corrosion-resistant conductive layer underneath acts as a stopper against corrosion. This achieves the above object of preventing the electrical connection between the bonding pad and the wiring from being interrupted.
以下図面を用いてこの発明を具体的に説明する。The present invention will be specifically explained below using the drawings.
〔実施例１〕
第３図および第４図は本発明をＭＯ８集積回路における
ポンディングパッドに適用した場合の一実施例を示す。[Embodiment 1] FIGS. 3 and 4 show an embodiment in which the present invention is applied to a bonding pad in an MO8 integrated circuit.
この実施例では、特に制限されないが、シリコンのよう
なＮ型半導体基板１の表面に熱酸化により形成された比
較的厚いフィールド酸化膜２上に、接続層となる第１の
導電層９が形成されている。In this embodiment, a first conductive layer 9 serving as a connection layer is formed on a relatively thick field oxide film 2 formed by thermal oxidation on the surface of an N-type semiconductor substrate 1 such as silicon, although this is not particularly limited. has been done.
この第１の導電層９は、アルミニウムに比べて水に対し
耐食性の良好な例えば、モリブデンやタングステン、チ
タン、タンタルもしくはこれらのシリコン化合物あるい
はポリシリコンを酸化膜２上に全面的に蒸着させてから
、・ホトエツチングにより不要な部分を除去することに
よっ℃形成されている。。The first conductive layer 9 is formed by depositing molybdenum, tungsten, titanium, tantalum, silicon compounds thereof, or polysilicon on the entire surface of the oxide film 2, which has better corrosion resistance than aluminum, such as molybdenum, tungsten, titanium, tantalum, or polysilicon. , ℃ is formed by removing unnecessary parts by photo-etching. .
第４図には、そのような第１の導電層９の具体的な形状
の一例が示されている。すなわち、第１の導電層９は正
方形の一辺に補強部９ａ”ｋ有する形状にされており、
この補強部９ａにてアルミ配Ｉ！３との接触がとられる
ように図られている。FIG. 4 shows an example of a specific shape of such a first conductive layer 9. That is, the first conductive layer 9 has a square shape with a reinforcing portion 9a''k on one side,
Aluminum arrangement I at this reinforcement part 9a! It is designed to make contact with 3.
また、上記第１の導電層９の上には、これよりも−回り
寸法の小さなホンディングパッドとしての第２の導電層
４が形成されている。この第２の導電層４は、前述した
ように配線３ケ構成するアルミ層によって、配線３と同
時に形成されるようになっている。ただし、配線３と第
２の導電層４とは切り離され、第１の導電層９を介して
互いに電気的に接続されている。Further, on the first conductive layer 9, a second conductive layer 4 serving as a bonding pad having a smaller circumferential dimension than the first conductive layer 9 is formed. This second conductive layer 4 is formed at the same time as the wiring 3 by using an aluminum layer that constitutes the three wirings as described above. However, the wiring 3 and the second conductive layer 4 are separated and electrically connected to each other via the first conductive layer 9.
そして、このように、第１の導電層９と第２の導電層４
の積層構造にされたポンディングパッドの上にパッシベ
ーション膜６が被覆され、中央部に開口部７が形成され
る。In this way, the first conductive layer 9 and the second conductive layer 4
A passivation film 6 is coated on the bonding pad having a laminated structure, and an opening 7 is formed in the center.
従って、ボンディングワイヤ５が直接ボンディングされ
る第２の導電層４と配線３との間には、パッシベーショ
ン膜６’＆構成するＳｉＯ２等の材料が介在されること
になる。そのため、実施例のように、ポンディングワイ
ヤ５との接触抵抗を減らし、かつ接着性を良くするため
にアルミニウムによって第２の導電層４を形成した場合
、水に弱いアルミニウムから第２の導電層４が、開口部
７から侵入した水分によって第４図斜線Ａ、Ｈのように
腐食されたとしても、パッシベーション材料によってあ
まり奥までは腐食されなくなる。その結果、第１の導電
層９とアルミ配線３との接触部（補強部９ａ）への腐食
の進行を防止することができ、腐食による断線が防止さ
れる。Therefore, between the second conductive layer 4 to which the bonding wire 5 is directly bonded and the wiring 3, a passivation film 6' and a material such as SiO2 forming the structure are interposed. Therefore, when the second conductive layer 4 is formed of aluminum in order to reduce the contact resistance with the bonding wire 5 and improve adhesiveness as in the embodiment, the second conductive layer 4 is formed of aluminum, which is weak against water. 4 is corroded as shown by diagonal lines A and H in FIG. 4 due to moisture entering through the opening 7, the passivation material prevents the corrosion from going very far. As a result, progress of corrosion to the contact portion (reinforced portion 9a) between the first conductive layer 9 and the aluminum wiring 3 can be prevented, and disconnection due to corrosion can be prevented.
なお、上記の場合、ポンディングパッド下層の第１の導
電層９は、回路を構成するＭＯＳＦＥＴのゲート電極１
０と同一材料を用いて同時に形成させることができる。In the above case, the first conductive layer 9 under the bonding pad is the gate electrode 1 of the MOSFET forming the circuit.
0 and 0 can be formed at the same time using the same material.
最近のＭＯ８集積回路のプロセスでは、ゲート電極とし
てポリシリコンが使用されることが多いのでその場合に
はポンディングパッドの第１の導電層９もポリシリコン
によって形成してもよい。また、この場合、ゲート電極
１０の上にはＰＳＧ膜（リン・シリコン・ガラス膜）の
ような層間絶縁膜１１が形成されるので、ポンディング
パッドの部分では、ＭＯＳＦＥＴのソースおよびドレイ
ン電極を形成するためのコンタクトホールの形成と同時
に、同一のマスクでＰＳＧＷＸＹ除去してやって、配線
用のアルミ蒸着時に第１の導電層９の上に直接第２の導
電層４か積層されるようにするのがよい。In recent MO8 integrated circuit processes, polysilicon is often used as the gate electrode, and in that case, the first conductive layer 9 of the bonding pad may also be formed of polysilicon. Furthermore, in this case, since an interlayer insulating film 11 such as a PSG film (phosphorus silicon glass film) is formed on the gate electrode 10, the source and drain electrodes of the MOSFET are formed at the bonding pad portion. At the same time as contact holes are formed for the wiring, PSGWXY is removed using the same mask, so that the second conductive layer 4 can be laminated directly on the first conductive layer 9 during aluminum evaporation for wiring. good.
さらに、最近のＭＯＳプロセスにおいては、ゲート電極
としてタングステン等の金属を用いることが提案されて
いるので、その場合にはポンディングパッド下層の第１
の導電層９を、ゲート電極１０と同じ金属材料を用いて
構成することができる。Furthermore, in recent MOS processes, it has been proposed to use metal such as tungsten as the gate electrode, so in that case, the first
The conductive layer 9 can be formed using the same metal material as the gate electrode 10.
〔実施例２〕
次に、第５図および第６図は、本発明の他の実施例を示
すものである。この実施例では、第１の導電層９に配線
３との接続のための補強部９ａ１ｇ！：設ける代わりに
、第１の導電層９は略正方形とし、配線３の端部に第１
の導電層９よりも−回り小さな正方形の枠状の接続部３
ａを形成するとともに、この枠状の接続部３ａよりも更
に−回り寸法の小さな略正方形の導電層４を、配線３と
同一のアルミニウム層によって構成しである。[Embodiment 2] Next, FIGS. 5 and 6 show another embodiment of the present invention. In this embodiment, the first conductive layer 9 has a reinforcing portion 9a1g for connection with the wiring 3! : Instead of providing the first conductive layer 9, the first conductive layer 9 is approximately square, and the first conductive layer 9 is formed at the end of the wiring 3.
A square frame-shaped connection portion 3 whose circumference is smaller than that of the conductive layer 9 of
The conductive layer 4 is made of the same aluminum layer as the wiring 3.
このような構成によれば、ポンディングパッド上層部の
第２の導電層４と配線３とは互いに接触されず第１の導
電層９を介して電気的に接続されるとともに、第２の導
電層４の周囲と枠状の接続部３ａとの間に生じた間隙内
に、パッシベーション膜６が形成されるとき、その材料
の一部が充填される。そのため、第２の導電層４はその
周囲を完全にパッシベーション材料によって囲繞され、
配線３端部の接続部３ａと離間されるようになり、アル
ミニウムからなる第２の導電層４が開口部７から侵入し
た水によって多少腐食されても、第１の導電層９と配線
３端部の接続部３ａとの接触部まで腐食が進行するのが
防止され、腐食による断線も生じに（くなる。According to such a configuration, the second conductive layer 4 and the wiring 3 in the upper layer of the bonding pad are not in contact with each other and are electrically connected via the first conductive layer 9, and the second conductive layer When the passivation film 6 is formed, a portion of the material is filled in the gap created between the periphery of the layer 4 and the frame-shaped connection portion 3a. Therefore, the second conductive layer 4 is completely surrounded by the passivation material,
Even if the second conductive layer 4 made of aluminum is slightly corroded by water that has entered through the opening 7, the first conductive layer 9 and the end of the wiring 3 are separated from the connection part 3a at the end of the wiring 3. Corrosion is prevented from progressing to the contact portion with the connecting portion 3a, and disconnection due to corrosion is also prevented.
この実施例においても、ポンディングパッド下層部を構
成する第１の導電層は、ＭＯ８Ｆ’ＥＴのゲート電極と
同一の金属もしくはシリサイドあるいはポリシリコン等
を用いて構成することができる。In this embodiment as well, the first conductive layer constituting the lower layer of the bonding pad can be made of the same metal, silicide, polysilicon, or the like as the gate electrode of the MO8F'ET.
さらに、上記実施例ではＭＯ８集積回路におけるポンデ
ィングパッドの構成例として説明されているが、この発
明はバイポーラ集積回路におけるポンディングパッドの
構成にも適用できることは勿論である。また、最近バイ
ポーラ集積回路では、ベース、エミッタ、コレクタ等の
電極をタングステン等の金属のシリサイドとアルミニウ
ムとの多層電極構造とすることにより接触抵抗の低減等
を図ることが提案されているが、その場合にはベース、
エミッタ等の電極を構成する金属もしくはそのシリサイ
ド等と同時に上記ポンディングパッド下層の第１の導電
層を形成するようにしてもよい。Further, although the above embodiment has been described as an example of the structure of a bonding pad in an MO8 integrated circuit, it goes without saying that the present invention can also be applied to a structure of a bonding pad in a bipolar integrated circuit. Furthermore, in recent years, it has been proposed for bipolar integrated circuits to reduce contact resistance by forming the base, emitter, collector, etc. electrodes into a multilayer electrode structure of metal silicide such as tungsten and aluminum. base in case,
The first conductive layer below the bonding pad may be formed at the same time as the metal or its silicide constituting the electrode such as the emitter.
（１）、配線と同時に形成されるポンディングパッドの
アルミニウム層の下に、予め耐食性の良好な金属もしく
はそのシリサイド等からなる導電層を形成しておいて、
この導電層を介して間接的に配線とポンディングパッド
のアルミニウム層とを接続させるよう忙したので、ポン
ディングパッド表面のアルミニウム層が多少腐食されて
もその下の耐食性導電層およびアルミニウム層周辺のノ
（ツシベーシミン材料が腐食に対するストッパとなると
いう作用により、アルミニウム層の腐食の進行が抑えら
れ、ポンディングパッドと配線との間の電気的接続が遮
断されないようになるという効果がある。(1) A conductive layer made of a metal with good corrosion resistance or its silicide is formed in advance under the aluminum layer of the bonding pad that is formed at the same time as the wiring,
Since the wiring and the aluminum layer of the bonding pad are indirectly connected through this conductive layer, even if the aluminum layer on the surface of the bonding pad is slightly corroded, the corrosion-resistant conductive layer underneath and around the aluminum layer will be protected. The action of the TSHIBESIMIN material as a stopper against corrosion suppresses the progress of corrosion of the aluminum layer and prevents the electrical connection between the bonding pad and the wiring from being interrupted.
（２）、配線と同時に形成されるポンプイングツくラド
のアルミニウム層の下に、予め耐食性の良好な金属もし
くはそのシリサイド等からなる導電層を形成し℃おいて
、この導電層を介して間接的に配線とポンディングパッ
ドのアルミニウム層とを接続させるようにしたので、ボ
ンディングに際し、ボンディング装置のヘッド（キャピ
ラリ）がアルミニウム層に圧接されたときに、第１の導
電層が緩衝材となるという作用により、ボンディングの
際のチップに対する衝撃を和らげパッド下方の絶縁膜や
基板の損傷ｌ防止するという効果もある。(2) A conductive layer made of a metal with good corrosion resistance or its silicide is formed in advance under the aluminum layer of the pumping layer, which is formed at the same time as the wiring. Since the wiring and the aluminum layer of the bonding pad are connected, when the head (capillary) of the bonding device is pressed against the aluminum layer during bonding, the first conductive layer acts as a buffer material. It also has the effect of softening the impact on the chip during bonding and preventing damage to the insulating film and substrate below the pad.
また、上記第１の導電層ケ回路を構成する素子の電極の
少なくとも一部と同一の材料により同時形成することに
より、プロセスを変更することなく上記効果を奏するポ
ンディングパッドｌ構成することが可能である。In addition, by simultaneously forming the first conductive layer and at least part of the electrodes of the elements constituting the circuit using the same material, it is possible to construct a bonding pad that achieves the above effects without changing the process. It is.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨ケ逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
例えば、上記実施例ではポンディングパッドがアルミニ
ウム層と耐食性の良好な導電層の２層構−造となってい
るが、上層部はアルミニウムに限定されるものではなく
、また、上層のアルミニウム層がＬＳＩの多層配線技術
に対応して多層構造にされているものであってもよい。For example, in the above embodiment, the bonding pad has a two-layer structure of an aluminum layer and a conductive layer with good corrosion resistance, but the upper layer is not limited to aluminum. It may have a multilayer structure compatible with the multilayer wiring technology of LSI.
以上の説明では主として本発明者によってなされた発Ｂ
Ａヲその背景となった利用分野である半導体集積回路に
おける電極技術について説明したが、それに限定される
ものではなく、たとえば、配線基板における電極技術な
どにも適用できる。The above explanation mainly focuses on the statement B made by the inventor.
A. Although the explanation has been made regarding the electrode technology in semiconductor integrated circuits, which is the field of application behind the invention, the present invention is not limited thereto, and can also be applied to, for example, electrode technology in wiring boards.
第１図は半導体集積回路におけるポンディングパッドの
一構成例を示す断面図、
第２図は同じくその平面図、
第３図は本発明をＭＯ８集積回路におけるポンディング
パッドに適用した場合の一実施例を示す断面図、
第４図はその要部の平面図、
第５図は本発明の他の実施例を示す断面図、第６図は同
じくその平面図である。
１・・・半導体基板、３・・・配線、４・・・第２導電
層（アルミニウム層）、５・・・ボンディングワイヤ。
６・・・バッジベージ田ン膜、７・・・開口部、９・・
・第１導電層、１０・・・ゲート電極。
第 １ 図
第 ２ 図
第 ３ 図
第 ５ 図
第 ６ 図
ＪユFIG. 1 is a cross-sectional view showing an example of the configuration of a bonding pad in a semiconductor integrated circuit, FIG. 2 is a plan view thereof, and FIG. 3 is an embodiment in which the present invention is applied to a bonding pad in an MO8 integrated circuit. FIG. 4 is a sectional view showing an example, FIG. 4 is a plan view of the main part thereof, FIG. 5 is a sectional view showing another embodiment of the present invention, and FIG. 6 is a plan view thereof. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... Wiring, 4... Second conductive layer (aluminum layer), 5... Bonding wire. 6... Badge page membrane, 7... Opening, 9...
- First conductive layer, 10... gate electrode. Figure 1 Figure 2 Figure 3 Figure 5 Figure 6 Figure J
Claims (1)
材料からなる第１の導電層の上に、上記配線と直接接触
されないようにされ上記第１の導電層を介して上記配線
と電気的に接続された第２の導電層が形成されてなるこ
とを特徴とする電子装置。 ２、上記第２の導電層が、上記配置を構成するアルミニ
ウム層と同一のアルミニウム層によって構成されたアル
ミニウム導電層であることを特徴とする特許請求の範囲
第１項記載の電子装置。 ３、上記第１の導電層が絶縁ゲート型電界効果トランジ
スタのゲート電極と同一の材料で同一のプロセスによっ
て形成されてなることを特徴とする特許請求の範囲第１
項もしくは第２項記載の電子装置。[Claims] 1. On the first conductive layer made of a conductive material with good corrosion resistance and in contact with the wiring of the internal circuit, the first conductive layer is placed so as not to be in direct contact with the wiring. An electronic device comprising: a second conductive layer electrically connected to the wiring via a second conductive layer. 2. The electronic device according to claim 1, wherein the second conductive layer is an aluminum conductive layer made of the same aluminum layer as the aluminum layer constituting the arrangement. 3. Claim 1, characterized in that the first conductive layer is formed of the same material and by the same process as the gate electrode of the insulated gate field effect transistor.
The electronic device according to item 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58186705A JPS6079762A (en) | 1983-10-07 | 1983-10-07 | Electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58186705A JPS6079762A (en) | 1983-10-07 | 1983-10-07 | Electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6079762A true JPS6079762A (en) | 1985-05-07 |
Family
ID=16193188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58186705A Pending JPS6079762A (en) | 1983-10-07 | 1983-10-07 | Electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6079762A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183326A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Bonding pad and formation thereof |
-
1983
- 1983-10-07 JP JP58186705A patent/JPS6079762A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183326A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Bonding pad and formation thereof |
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