JPS60778B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a high-speed switching transistor.

In this invention, a two-layered surface-stabilized suppuration is formed on the surface of a semiconductor substrate in advance, and an impurity diffusion process is performed using a vacuum sealed tube diffusion method (ampule diffusion method) using the film as an impurity selective diffusion mask. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can stabilize the surface of an element, eliminate the need for a washing process after impurity diffusion treatment, and allow electrode attachment to be performed immediately.

Generally, in high-speed switching transistors,
In order to increase the switching speed, efforts are being made to reduce the area occupied by the base and emitter.

In this case, in the photoresist technique using a photomask, it is difficult to reduce the emitter size to about several r or less due to limitations in photomask accuracy, the influence of diffracted light during exposure, and the like. Therefore, as a solution to this technical problem, a washed emitter method has been proposed, which simplifies the process of drilling holes in the insulating film for emitter contacts. The washed emitter type is a phenomenon in which impurities diffused into a semiconductor substrate diffuse not only vertically but also horizontally within the substrate, resulting in the impurity diffusion region on the substrate surface being larger than the impurity diffusion hole. The focus is on

The feature of this method is that in the process of diffusing emitter impurities, the thin insulating film formed on the surface of the emitter region is completely washed away with an etching solution, and the emitter impurity diffusion holes formed in the previous process are directly connected to the emitter contact. The point is that it is used as a hole. Therefore, the washed emitter method has the advantage that it is possible to easily form a transistor having an extremely small emitter, since it is only necessary to make a hole for the base contact using photoetching technology. However, in this type of conventional method, as with other ordinary transistors, an insulating film initially formed on the surface of a semiconductor substrate is used as a mask for impurity diffusion, and this is used as a mask for the final transistor. Since it was used as a surface stabilizing protective film for Z-distor, it had the following drawbacks.

For example, when obtaining an NPN type silicon transistor, it is common to use phosphorus (P) as an emitter forming impurity, but as is well known, phosphorus is diffused into a substrate having a silicon oxide film (Si02) on the surface. Then, phosphorus combines with the silicon oxide film to form phosphorus glass on the surface of the silicon oxide film. Since this phosphorus glass layer has an extremely effective effect on stabilizing the surface of the transistor, it is desirable to leave it as it is. However, in the conventional method, the above-mentioned effective glass layer is removed in the washing step after the emitter impurity diffusion, and the surface stabilizing effect is lost. Therefore, as a method to further eliminate the above-mentioned drawbacks,
7-40993, after completing the base impurity diffusion treatment, the mask film remaining on the substrate surface is removed, and in its place, a new phosphorus glass (PSG)-silicon oxide film (Si02) is grown using the vapor phase growth method. A method has been proposed in which an insulating film is formed as a layer, and then emitter impurities are diffused using the insulating film as a mask.

However, in this case, there is a risk that the upper phosphor glass layer of the insulating coating may be etched and removed by the washing step performed after the emitter impurity diffusion treatment.

For this reason, the method described above has the drawback that the phosphorus concentration in the phosphorus glass layer must be reduced, making it difficult to enhance the surface stabilizing effect. The present invention eliminates each of the above-mentioned drawbacks, and one embodiment thereof will be described below with reference to the drawings. FIGS. 1 to 6 are cross-sectional views of a semiconductor device in the process of being manufactured, respectively, for explaining each manufacturing process when manufacturing an NPN transistor using the manufacturing method of the present invention. After the base impurity diffusion treatment, as shown in FIG. 1, a base region 2 is formed in the N-type silicon substrate 1, and a silicon oxide film 3 is formed on the base region 2 and the surface of the silicon substrate 1. has been done.

The semiconductor substrate in such a state is first etched with hydrofluoric acid or the like to remove the silicon oxide film 3. As a result, as shown in FIG. 2, the surfaces of the silicon substrate 1 and base region 2 are exposed. Thereafter, as shown in FIG. 3, a two-layer insulating film 6 consisting of phosphorus glass (PSG) 4 and silicon oxide film (S02) 5 is formed on the exposed surface by chemical vapor deposition as in the conventional method. .

Next, as shown in FIG. 4, a part of the insulating film 6 is bored by photoetching to form an emitter impurity diffusion hole 7 on the base region 2. At this time, a collector contact hole (not shown) is formed at the same time, and an N+ region, which is widely used in ICs, can also be formed by emitter impurity diffusion treatment, which will be described later.Next, emitter impurity diffusion treatment This diffusion process is carried out using a vacuum sealed tube diffusion method (ampule diffusion method), and phosphorus (P), which is the same as the conductive impurity contained in the glass layer 4, is used as the emitter impurity. .

That is, as shown in FIG. 5, the semiconductor substrate 8 which has undergone the emitter impurity diffusion hole drilling step (FIG. 4) is first placed on a mounting table 10 in a quartz tube 9. As shown in FIG. One end 9 of the quartz tube 9
a is closed, and doped silicon or red phosphorus 11 doped with a high concentration of phosphorus, which is a diffusion source of the emitter impurities, is previously placed in a quartz boat 12. Subsequently, the inside of the quartz tube 9 is evacuated to a predetermined degree of vacuum of approximately 1×10-6 To
In the state in which the quartz tube reaches m, the entrance end 9b of the quartz tube is sealed.
After this, the quartz tube 9 is placed in an electric furnace to a desired temperature, e.g.
Heat for 0.00-95 and 0.40-80 minutes. This results in
Phosphorus (P) is diffused from the diffusion source 11 into the semiconductor substrate 8.
An emitter region 13 is formed therein as shown in FIG. At this time, since there is no oxidizing atmosphere inside the quartz tube 9, no oxide film is formed on the surface of the emitter region 13. Therefore, after the emitter impurity diffusion process, there is no need to perform a wash process, which was required in the past, and electrodes can be attached immediately after forming the base contact hole. Note that the emitter region 13
The formation can also be performed by ion implantation, but in this case, the impurity region must be expanded and wrapped under the silicon oxide film 5 by heat treatment (annealing) after implanting the impurity.

In the case of a PNP transistor, boron (B) can be used as an emitter impurity, and poron silicate glass (BSG) can be formed as a surface stabilizing film. Furthermore, after the base impurity diffusion treatment, a glass layer containing conductive impurities can be formed on the silicon oxide film 3 without removing the silicon oxide film 3.

It goes without saying that the present invention can be applied to a wide range of applications such as diodes, transistors, ICs, and LSIs.

As mentioned above, "According to the method of manufacturing a semiconductor device according to the present invention," after completing the base impurity diffusion treatment, the mask film remaining on the substrate surface is removed, and in its place, a new surface-stabilized pus consisting of two layers is added. Since the conductive impurities contained in the upper glass layer of the surface stabilizing film and the emitter impurities are the same, the emitter impurity diffusion profile is Furthermore, since the emitter impurity treatment is performed using the vacuum sealed tube diffusion method, no oxide film is formed on the surface of the emitter region during this treatment, thus eliminating the need for the conventional washing process. It has the advantage that electrodes can be attached immediately.

[Brief explanation of the drawing]

FIGS. 1 to 6 each show a method of manufacturing a semiconductor device of the present invention.
FIG. 3 is a cross-sectional view of a semiconductor element in each manufacturing process when manufacturing a semiconductor device according to an example. 1... Silicon substrate, 2... Base region, 3...
Silicon oxide film, 4... Phosphorous glass, 5... Silicon oxide film, 6... Insulating film, 7... Emitter impurity diffusion hole, 8... Semiconductor base, 9 Screaming quartz tube, 11・
... Impurity diffusion source, 13... emitter region. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. Forming an insulating film on the surface of a semiconductor substrate, the upper layer of which is a glass layer containing a predetermined conductive impurity, and using the insulating film as a mask to implant conductivity-determining impurities by ion implantation using an oxidizing atmosphere. a step of introducing the ion implantation hole into a semiconductor substrate, and a step of connecting an electrode by using the ion implantation hole as a contact hole, and the method of manufacturing a semiconductor device is characterized in that the insulating film remains as a surface stabilizing film of the element. .