JPS6073578A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention is provided with a display surface made up of a large number of picture elements arranged in a matrix, and has a pyroxene gradation level in an image to be displayed on the display surface. The present invention relates to a display device that controls the pulse width of the light output of each picture element according to the pulse width and displays C1 still images, moving images bt, < is characters, etc., or a color or monochrome image consisting of a combination thereof.

(Background of the invention) Conventionally, this type of device was used in television receivers, etc.

In place of the widely used cathode ray tube (CRT), a display screen is known in which a large number of picture panels made of light sources such as incandescent lamps, fluorescent lamps, and light emitting diodes are arranged in a matrix. Such display devices are used, for example, as scoreboards in baseball stadiums, stadiums, amusement parks, etc., and large display devices for various displays or outdoor advertisements.

By the way, when a discharge lamp (lamp) is used as a picture element of such a display, it is necessary to perform dimming lighting based on a video signal. Conventionally known dimming methods include a dimming method by controlling the phase of a commercial power source, and a DC point pair dimming method by controlling the pulse width of a DC power source.

However, the former is not preferable because the stabilizer is relatively large and heavy, and it is difficult to achieve the desired reduction in size and weight, especially when the stabilizer is installed in multiple stages corresponding to the number of display pixels. on the other hand,
The latter uses resistance as the current limiting element, so 10 arrows are large;
There are also disadvantages such as the need for a special lamp for direct current lighting.

Therefore, in order to eliminate these drawbacks, a method has been proposed that uses a DC power supply and uses an inverter to turn on the low frequency light to compensate for the shortcomings of the above two methods.However, in this method, when the dimming is deep, the high frequency Since the isometric frequency of the dimming pulse width is similar to the stipple frequency of the stipple, simple pulse width control has the disadvantage that lamp flickering occurs due to a phase shift.

(Object of the invention) The object of the present invention is to solve the problems of the conventional type described above.
In a display device that uses a discharge lamp as a light source pixel, the C1 discharge lamp is lit at high frequency and the relationship between the dimming signal corresponding to the video signal and the discharge lamp lighting frequency is improved based on the idea of improving the compactness and weight of the device. The objective is to reduce flicker and prevent flickering of the lamp.

(Structure of the Invention) In order to achieve the above object, the present invention provides a display surface C in which a large number of discharge lamps as light source picture elements are arranged, and each discharge lamp is dimmed by controlling the pulse width to display the above-mentioned display. A display device that displays an image on the screen is placed on the screen, the discharge lamp is lit at high frequency, and this high frequency horn is connected to the display device.
The present invention is characterized in that the above pulse width control is synchronized.

(Explanation of Examples) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows the overall configuration of a display device according to an embodiment of the present invention. Further, FIG. 2 shows waveforms of various parts in the apparatus of FIG. 1. In FIG. 1, a received signal received by an antenna 1 is high-frequency amplified by a radio amplifier 2, and then detected by a video detection circuit 3 to extract a video signal. This video signal is amplified by the video amplifier 4, and A'/
The signal is supplied to the D conversion circuit 5 and the synchronous separation circuit 6. A/
The D converter circuit 5 samples the video signal from the video amplifier 4 at a timing corresponding to the position of each picture element arranged on the display surface, and converts this sampling signal from A/D to 6 bits (0 to . 63) gradation data KD is generated. On the other hand, the synchronization separation circuit 6 extracts the vertical synchronization signal SV of 50 or 60H2 from the video signal from the video amplifier 4, and the address setting circuit 7 outputs the gradation data in synchronization with the synchronization signal SV from the synchronization separation circuit 6. Pulse width generation circuit 8 (8-+, 8-2,...
. , 5-n) address data ADR are generated sequentially. The pulse width generating circuit 8 performs A/D conversion when the address data ADR output from the address setting circuit 7 matches its own address.

In the device shown in FIG. 1, since the switch 94 is controlled by synchronizing the dimming pulse DP with the oscillation frequency of the inverter 92, the lamp energizing voltage V2 is controlled as shown in FIG.
always rises from the same voltage, for example OV, so that the point versus time of the lamp 95 for the same gradation data, that is, the dimming level is constant, and no flickering occurs. Incidentally, when the conventional switch 94 is turned on at random, the rise of the lamp energizing voltage 2, that is, the ignition timing of the lamp 95, differs for each pulse, so that the dimming level of the lamp 95 for the same gradation data is different. This is what appeared as flickering in the image.

FIG. 3 shows the main parts of FIG. 1 more specifically. In the figure, a known constant current push-pull inverter is used as the inverter 92, and a ballast inductor is used as the current limiting element 93. In addition, the AC switch 94 that turns on and off the high frequency lamp current is a diode bridge 941.
It is composed of J:j, a transistor 942, and the like.

In FIG. 3, while the DC power supply 91 is turned on, the inverter 92 oscillates, high frequency voltage is induced in each winding of the output transformer 921, and the discharge lamp 95
The filament is preheated by the filament power supplied from the filament winding 921f of No. 21.

In addition, the start-up circuit 96 detects the level of the full-wave rectified voltage from the synchronous output winding 5j1921c of the output transformer 921 of the inverter 92 through the diode bridge 922 through the transistor 961'c, and outputs the voltage from the capacitor 962, resistor 963 and Transistor 9 by diode 964
61 differentiates the rise of the collector voltage after Δ and applies it to the transistor 965, and this ]・Raran jitter 9
The oscillation synchronization signal SY is generated as the collector voltage of 6.

Note that this oscillation synchronizing signal SY has the phase inverted from that shown in FIG.

FIG. 4 shows details of the delay circuit 10 portion of FIG. 1.

Further, FIG. 5 shows the operation timing of each part of the circuit of FIG. 4.

The dimming pulse CP is sent from the pulse width generation circuit 8 to the delay circuit 10.
When the pulse width signal @CP shown in FIG. 5 is at a torque level, the latch circuit 101 is supplied with a ret signal of 1" level from the inverter 102, and the output horn is raised to level 1. .

Further, the output of the up/down counter 103 is 0 count, and the output of the O-power/clock circuit 104 is a torque signal.
The output of 04 is supplied to one terminal of the inverter 10 (3), and the torque signal inverted is supplied to one terminal, and the C output becomes the torque.
A torque signal is supplied from the ND gate 105, the output becomes a torque signal, and no dimming pulse DP is generated.

Next, when the pulse width generation circuit 8 generates the dimming pulse CP, the AND gate 108 applies the dimming pulse CI) of this torque to one input terminal, and the torque pulse of the latch circuit 101 to the other input terminal. Output to inverter 109
The inverted torque signal is applied, and the torque is output. As a result, the counter 103 is controlled by the clock circuit 110.
Start the up-run 1 of the clock pulse that occurs. In this case, the output of the O output 1 Kunt comparator circuit 104 becomes a trubel, and 1-rubel ig is applied to one input terminal of the AND gate 105 via the inverter 106; A torque signal obtained by inverting the dimming pulse CP by the inverter 102 is applied to the input terminal of
It remains as a bell. Further, the output of the latch circuit 101 becomes the output of the inverter 102 and the reset is canceled, but since the output of the AND gate 111 is the torque, the latch circuit output remains at the torque. Therefore, at this point, the output of the OR gate 107, that is, the delay circuit output DP, remains at the torque level.

In this state, when the inter-oscillation m signal SY is further input, A
N1) When both the inter-oscillation signal SY and the dimming pulse CI-111 reach the 1'' level, the latch circuit 101 latches the torque output. Due to the torque output from the latch circuit 101, the OR circuit 107 outputs a torque, that is, one dimming pulse D. Further, the counter 103 is prohibited from counting, and the AND circuit 108 outputs the torque by applying the torque to the other terminal via the inverter 109, thereby causing the counter 103LJ dimming pulse CP
The time td is measured until the oscillation synchronization signal SY is input manually from the input C, and the down cycle 1~ state is reached.
-C Stop. In this state, the pulse width signal C
P continues for the duration of the trubel.

When the dimming pulse CP ends and the pulse width signal CP reaches the positive level, the output of the inverter 102 becomes 1 lvl.
The latch' circuit 101 is reletted and the output becomes a trubel. However, since the torque signal from the inverter 702 is applied to one input terminal of the AND groups 1 to 105, the force C controller 103 increases the delay time td by 5
If it is 1 o'clock, the 1'' level signal obtained by inverting the output of the O count comparison circuit 104 to the inverter 106 r is ANDed.
This A is applied to the external force input terminals of Goo 1 to 105.
The output of the ND gate 105 becomes 1-level, and the 1-107 continues to output the dimming pulse DP of the level. Further, as a result of the output of the rack circuit 101 becoming 1-level, the counter 103 is disabled from counting.
Jζ retown counter 1- is started on the output of AND goo 1 to 108.

Furthermore, after the delay time (d has elapsed, Ii of the counter 103
When the output reaches l number of outputs, the outputs of O-column 1 to comparison circuit 104 become torbel. This allows ANI) Goo 1 to 10
5 is supplied with the torque input via the inverter 106, and the output becomes the torque. This ending, OR goo 1~107
Output DP: becomes bL level. Also, AND goo 1~
1 by inverting the torque output of 108 with inverter 112.
- The output of the AN[) group h113 is set to the F level by the 1 level signal and the 1 level signal of the O count comparison circuit 104, and this torque signal is applied to the counter 103's number 1~
Input to the terminal to inhibit counting.

As described above, when the dimming pulse CP is generated from the pulse width generation circuit 8, the delay time d3 in the delay circuit 10 is delayed until the oscillation synchronization signal SY is sent from the dimming ballast 9. While waiting for the output DP, the time from when this dimming pulse CP is generated until the oscillation synchronizing signal SY is sent from -C, that is, the delay time td of the output DP, is measured, and after the dimming pulse CI-' is completed. Also, the time delay output DP corresponding to the delay time [d is continued at U. Therefore, the dimming pulse C1-) and the delayed output DP have the same pulse width,
And the asynchronous dimming pulse CP is the same as the oscillation synchronization signal SY.
y'' can be converted into a delayed output DP.

FIG. 6 shows a circuit of a dimming ballast according to an embodiment of the present invention. The ballast shown in the same figure is different from the one shown in Fig. 3 by replacing the inverter 92 with a separately excited type, and further, in the ballast shown in Fig. 3, the inverter is allowed to run freely and the oscillation synchronization signal SY is extracted from its oscillation output. , the dimming pulse CP from the pulse width generating circuit 8 was delayed by the delay circuit 10 and synchronized with the oscillation synchronizing signal SY. The oscillation output of the inverter 92 is connected to the CP. I'm letting you do IJ. Therefore, the first
Also, the oscillation synchronization circuit 96 shown in FIG. 3 is not necessary. Furthermore, in the apparatus shown in FIG. 1, the delay circuit 10 is removed and the dimming pulse CP from the pulse width generating circuit 8 is input directly to the switch 94, and the leading edge of the dimming pulse CI) and the trigger are A one-shot multi-vibrator 11 is added to provide the one-shot pulse 11, and the output of this one-shot pulse 11 is applied to a j-inverter 92 as a synchronizing signal.

That is, in FIG. 6, at l13, the inverter 92 is equipped with an astable multi-by-break 923, and the rectangular wave output of this astable multi-byte 923 drives the output transistor 924, and the primary winding 921p of the output transformer 921 is By switching the current, a high frequency output is generated in the secondary winding 9218, etc.

As shown in FIG. 7, when the C dimming pulse CP is generated in the pulse width generating circuit 8, the one-shot pulse 11 is triggered from 1 to 1 at the leading edge of this dimming pulse CP to generate a one-shot pulse. . This one-shot pulse turns on the astable multiplier 9231 to trigger transistor 925, initializes the pJ stable multiplier 923, and immediately starts new oscillation as soon as the one-shock 1 to pulse reaches A. This output is applied to the C lamp 95 via the output transistor 924d3, the output transistor 925, and the switch circuit 94 which is turned on by the dimming pulse CP, energizing the lamp as shown in the bottom row of FIG. Ru.

(Of course of the invention) According to the present invention, since the discharge lamp is connected to the high frequency point, the size and weight of the device can be reduced. Since the leading edge of the pulse and the high frequency output for point pairing are synchronized, it is possible to prevent variations during actual lighting for the same gradation, and especially to prevent lamp flickering at deep dimming levels. Therefore, a display device with good display stability can be provided.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a display device according to an embodiment of the present invention, FIG. 2 is an operational waveform diagram of each part of the device in FIG. 1, and FIG. 3 is a diagram of a dimming ballast in the device in FIG. In response to a specific example, Figure 15 shows the circuit diagram of the delay circuit part of the device shown in Figure 1, Figure 5 shows the operation timing of the delay circuit shown in Figure 4, and Figure 6 shows the circuit diagram of the delay circuit of the device shown in Figure 4. FIG. 7 is a partial circuit diagram showing the main parts of a display device according to another embodiment, and FIG. 7 is an operation waveform diagram of each part of the device shown in FIG. 6. 8...Pulse width generation circuit, 9...Dimmer ballast, 1
0...Delay circuit, 92...Inverter, 94...Lamp, 96...Oscillation synchronization circuit. Patent applicant: Toshiba Electric Materials Co., Ltd. Attorney: Patent attorney: Tatsuo Ito Attorney: Tetsuya Ito

Claims (1)

[Scope of Claims] A display surface is provided with a large number of discharge lamps arranged as light source picture elements, and each discharge lamp is dimmed by controlling the pulse width of each discharge lamp, thereby displaying ll! on the display surface. 17. A display device for displaying 17 images, characterized in that the above electric lights are turned on at a high frequency, and the high frequency output and the above pulse width control are synchronized.