JPS6072399A - Remote control device - Google Patents

Abstract

PURPOSE:To simplify circuit configuration and increase processing speed by making interruption to a CPU for load control by a start signal and making the CPU execute processing of a transmission signal as interruption processing. CONSTITUTION:Plural home controllers (slave machine) 4-1-4-n are connected to the common gateway machine (master machine) of a remote control device through a transmission line 2. A CPU43 is connected to load (object of control) 44 of home controllers 4-1-4-n, and an address setting section 45 is connected to the CPU. A counter 46 and a clock generator made up of a crystal oscillator and capacitor 48, 49 are connected between the transmission line 2 and CPU43. Clock is supplied from the generator to the counter 46 and CPU43, and time of L level period on the transmission line 2 is counted by the counter 46. Interruption is made to the CPU43 by a start signal, and the CPU43 executes processing by processing of a transmission signal. Thus, processing speed is increased by simple configuration.

Description

Detailed Description of the Invention (Field of the Invention) The present invention connects a base unit and a plurality of slave units via one transmission line, and transmits signals in a time-sharing cyclic manner between the base unit and each slave unit. The present invention relates to a remote control device that remotely controls a control object connected from a base unit to each slave unit without transmitting information.

(Background of the Invention) FIG. 1 is a connection diagram of an interbon device for an apartment complex as an example of this type of remote control device.

This intercom device is used in housing complexes such as Yangshon for visitors to make calls by extending 37 hours from the common entrance to the resident's unit. In the figure, reference numeral 1 denotes a common entrance machine that is left over at the common entrance, and a calling (transmission) line 2 and a speech (voice) line 3 are connected to this common entrance machine 1, and these 11 and f output signal lines are connected to the common entrance machine 1. 2 and the communication line 3 are connected to the Baumecon 1-Roller 4 (4-1, 4-2, ..., 4-
n) is connected using a multi-drop method.

These communal entrance machine 1 and home controller 4 are
Both are central processing units consisting of micro processors, etc.
They each have a CPU (CPU) and mutually transmit data via a transmission line 2 under the control of each CPU. As shown in Figure 2, 1 ml of common entrance of Tsunawano 5, main unit and C is star 1~<s % s v, communication partner's home ni! nt[''
-A (address signal that specifies slave unit > 4-k)
l) Rk, child II to 4-1trr) control signal CT
Sending 18 months consisting of IX etc. with F to each handset 4-1.4-2
．． ....

4-1), and on the other hand, the address signal ADRkT-designated IC slave unit 4-1 (takes in the control signal C7rRk from the transmission line 2 and sends the IC slave unit 4
-1( is connected to the control 3/j event and sends it as a reply to the C transmission line 2 as a reply, etc.), and performs the commanded operation using the control signal C''I Rk'c. .

The return (H signal RE P k sent from the slave device 4-1) is received by the base device 1. In this case, immediately after the address signal △DR, the control signal 3 CTR, and the reply signal @RFP, The inverted signals ADπ, CTR and RIEP of each signal are sent out to make the signals redundant and improve the reliability of signal transmission.

FIG. 3 shows the main parts of the home controller 4 (.

In the figure, the Baume controller 4 includes an input/output interface 41, a serial/parallel conversion circuit 42, a CP'U 43, a negative section (control object) 44, etc., and a transmission line 2 via the input/output interface 41. It is connected to the.

The serial/parallel conversion circuit 42 multiplies the signal on the transmission line 2 by i'' through the input/output interface, and outputs the signal to the parent P31.
Detection of the star l-signal ST sent from the serial address signal ADR and control @CT
R is converted into a parallel signal and supplied to the CPU 43. Further, the control signal CTR is received from the control signal CTR, and the supervisory signal given from the CPU 43 is converted into a parallel signal, and immediately after that is converted into a serial signal and sent as a reply signal REP to the transmission line 2 via the C input/output interface 2[- 41]. Send to.

The CPU 43 receives the address signal ADR supplied from the serial/parallel conversion circuit 42 and the address setting key 4.
5, the CTR is checked against the preset self-address ('), and the subsequent system 91 No. 3 CTR is decoded. In addition, the receiver 44 is connected to a handset, an audio amplifier, a ring tone generation circuit, and It consists of a voice processing circuit consisting of a hook switch, etc., a line connection switch that connects the communication line 3 and the voice processing circuit, a switch that connects and disconnects each part in the voice processing circuit, etc., and the CPU 43 controls the operation of this voice processing circuit, for example. Controls the generation of ringtones and connection of telephone lines.

The common entrance unit 1 is equipped with a numeric keypad for selecting the door to be served (not shown), a dial key, etc.
11. il 41.

Next, the operation 1!1- of this intercom 44 will be explained.

When a visitor or the like selects a called residential unit using the called residential unit selection numeric keypad and presses the -c generation key, the common entrance unit 1 outputs an address signal Δl of Baumecon 1-○-ra 4-1 (of the selected residential unit). ) Issuing as a control signal C1-Rk following Rk n
f signal to the transmission line. Home computer I・1”-La 4
In response to the calling signal of L=, the CPU 43 of ~1() generates a ring tone from the voice processing circuit, and when the handset is hooked up in response to this discharge tone, the line connection relay is closed. and connects the voice processing circuit to the telephone line 3, thereby connecting the common entrance unit 1 and the home computer 1- of the called residence.
A telephone line to 〇-ra 4- is established. When the call ends and the handset is hooked down to the home controller 4-1, the Baum controller 4-1 sends out this hook town signal as a reply signal REPk, and the communal entrance unit 1 sends this reply signal REPk. When k is received, the control signal CTRk indicates the end of the call and sends a signal or a signal with no command.When Baumcon 1 to Roller 4-1t receive this call end signal @, etc., they open the line connection relay, etc. Return the processing circuit to standby state.

By the way, in such intercom devices, transmission processing such as serial/parallel conversion is performed separately from voice processing by an external circuit using a specialized IC or CPU, which makes the circuit configuration complicated and expensive. There was an inconvenience.

(Object of the Invention) The present invention has been made in view of the problems of the conventional type described above, and provides 11-bit data transmission between a base unit and a plurality of slave units in a time-sharing C-like manner. In the current remote control device, the circuit configuration was designed based on the idea that the processing CPU would perform interrupt C transmission processing in response to the star signal from the base unit. The purpose is to simplify and reduce the cost of the device.

(Structure of the Invention) In order to achieve the above object, the present invention is equipped with a base unit and a plurality of slave units connected to the base unit via a transmission line and each having one or more control objects connected thereto. Then, from the master unit to Star No. 1-46, slave unit address signal J3 and control 211
The transmission signal including the signal is sent to the transmission line, and the
When the handset address matches the self address, the control signal is captured, and the control DI + target monitoring (
By returning i'4), the parent performs time-division C transmission with each child device in sequence, and each child device performs the control based on the control 8. i1+'
At the remote control device controlling the object, -
Each of the above-mentioned slave units is responsible for controlling the above-mentioned controlled objects! l! The device is equipped with means for detecting the star signal, and the detection signal generated by the detection means interrupts the central processing unit controlling the controlled object, and the central processing unit verifies the address signal. and transmission processing including control signal acquisition.

(Explanation of Examples) The present invention will be described in detail below with reference to the drawings.

Note that parts common to or corresponding to those of the prior art are denoted by the same reference numerals.

FIG. 4 shows a child +! according to an embodiment of the present invention. ! The block configuration of (Baumcon) to roller 4) is shown. The home computer 1 and roller 4 in the same figure are different from the one in FIG. 3 by removing the input/output interface 41J3J: and the serial/parallel conversion circuit, and replacing it with the transmission &i! A counter 46 is connected to count the period during which the signal on 2 is at the 1-level to 4 o'clock. As this counter 4G, for example, a 7-stage binary counter can be used. Numeral 41 is a crystal oscillator for generating clocks for the CPU 43 and counter 46 together with capacitors 48 and 49.

This home page is on U-LA (+-10) 4.

The counter 46 constantly monitors the signal on the transmission line 2 and
J43 normally executes the 1-IC control main routine 11) in FIG. 5, that is, the load 44 control routine.

The counter 46 sends an address signal @A D to the transmission line 20.
Issues in which R1 control signal CT RJ3 return response F3 RE P etc. are sent are cleared by the H level signal part that forms these signals. When the start signal ST consisting of an L level signal is sent out, the clearing is canceled and counting of U-tsuku is started. Then, this 1-level (the duration of g is shorter than the start signal ST, but other (5 bows do not exist; a constant count corresponding to a fairly long time) ~
Start input signal from transmission line 2 (3)
No. S1 is determined and an interrupt is issued to Cl)U 43. As a result, the CPU 43 switches to the 5th CPU, as shown in FIG.
For example, the main routine of the HC1ltII shown in the figure interrupts the audio processing operation described above and moves to the transmission processing routine shown in Fig. 6. Following the start signal ST, the serial address signal manually generated from the transmission line 2 is converted into a parallel signal. , performs a check against its own address. Here, if the input address AD]R does not match its own address, then
), the main routine is returned to, and if the input address ADR and the self address match, the process returns as shown in FIG. 7(b).
As shown in FIG. 5, this transmission signal processing routine is further continued to convert and store the manually input serial control signal CTR following the address signal MADR into a parallel signal, and then store it in the main routine shown in FIG. After sending out the monitoring signal etc. as a reply signal RFP to the C serial, the process returns to the main routine shown in FIG.

(Effects of the Invention) As described above, according to the present invention, the load control CPU is interrupted by the star 1 signal and the transmission signal processing is caused to be executed by this CPU as an interrupt process. In place of the transmission processing circuit of Since it immediately returns to the main routine and performs load control, CF)U
C is a problem in cases where processing speed is not required, such as voice processing in 1'1. No.

[Brief explanation of drawings]

Figure 1 is a connection diagram of an interbon installation for an apartment complex, Figure 2 is a matte diagram of the signals sent to the transmission line in Figure 1,
FIG. 3 is a block diagram of the conventional home computer 1 to [1-ra partial block 1'' shown in FIG. 1, and FIG. Figures 5, J and 6 show the operation of the CPU in the Baume Comte 1 chorus of Figure 4. The figure shows the relationship between the transmission signal and the operation in the CPU. 1...Common entrance +1 (Parent I), 2...Transmission line,
4... Baume Comte 1-A (Ryo [Iku)], 43...
CPU, 44...load, 45...address setting section,
46...Counter. Patent Applicant Toshiba Electric Materials Corporation Attorney Patent Attorney Tatsuo Ito Attorney Patent Attorney Tetsuya Ito Figure 1 S ADF? ADF? CTF? CTRREP City fST
ADRiFigure 3 5 5

Claims (1)

[Claims] The main unit and this! 31 connected via a transmission line and (
One or more control pairs 11 are connected to each f2 number of children (1ia L/), and a transmission signal including a start signal, a slave address signal, and a control signal is transmitted from the base unit to the above 1.
When the slave device address matches its own address, each r device takes in the control signal and sends back the I!u congratulations message for the 4-open control 211. Transmission is carried out in cyclic 11.1 divisions between the recorder 1 and each child unit, and furthermore, each of the child units is based on the control signal. In the device "1", the above 8 children 1jl are the central processing unit ζl which controls the above control object and the -1-star I-1.
The first stage of detection (ffi) interrupts the medium heat processing unit that is controlling the control object, and the central processing unit verifies and performs the verification of the address signal. A remote control device characterized by performing transmission processing including control signal capture.