JPS6072051A - Interruption unifying device - Google Patents

Abstract

PURPOSE:To reduce the load or a CPU by outputting an interruption unifying signal, in case the output of a state variation counter is larger than the output of generating device of a threshold level which decreases gradually as a time elapses from an initial state, and initializing the counter and the generating device. CONSTITUTION:When process in formation 1 is received by a DMA5 through a CDT master station 4, etc. and processed between the DMA and a CPU7, an interruption unifying device 14 is constituted of a state variation counter 15, threshold level generating device 16 and a comparator 17, and connected between the DMA5 and a state variation receiving device 13 in the CPU7. In this state, the interrupting signal 18 from the DMA5 is counted by the counter 15, an accumulation state variation number 19 from an initial state is outputted, a threshold level 20 which decreases gradually as a time elapses from the initial state is outputted by the device 16, both the outputs are compared by the comparator 17, and in case when the number 19 is larger or equal, an interruption unifying signal 21 is applied to the device 13, the device 16 is initialized, and the overhead is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an interrupt integration device, particularly a information transmission device (CDT).
) to a direct memory access device (DM
This invention relates to an interrupt integration device that reduces the load on a computer (CPU) when an input is made to the computer (CPU) via A).

[Technical background of the invention]

The conventional technology will be explained with reference to FIG. FIG. 1 shows an arrangement for introducing information from a process into a CPU.

That is, the information indicating the status of Zorocess information 1 is transmitted to CDT slave station 2.
The data is transmitted from the CDT master station 4 via the transmission path 3. When the DMA 5 receives the CDT data 6 from the master station 4, the DMA 5 stores the CDT data old value area 8 in the CPU 7.
Corresponding data 9 is extracted. FIG. 2 is a configuration diagram of CDT data, the CDT data has a word address W as a data identification code, and the CDT data for this has a word address W as a data identification code.
A data old value binary area 8 and the word address W doubling area are prepared.

Therefore, when CDT data 6 is input, DMA 5
retrieves corresponding data 9 from the CPU.

FIG. 3 is a binary diagram of CDT data old values, and corresponding data 9 includes (1) whether or not data state change detection is necessary (S);
(2) Binary value (DATA') corresponding to cDT data 6
It contains two pieces of information: If state change detection is required (S=1), DMA 5 outputs CDT data 6 and corresponding data 9.
The CDT data 6 is compared with the old value corresponding to the CDT data, and if they are different, the CDT data 6 is written to the status change list 11 as the status change data 10, and an interrupt 12 is given to the CPU 7. In the CPU 7, the status change reception device 13 is driven by this interrupt 12.

After performing the state change processing described later, the state change reception device 13 extracts the CDT data 6 from the state change data 10 in the state change list 11 and transfers it to the CDT data 6 corresponding to the CDT data 6.
Write data to the old value binary area 8 informally determined area. This is updating the old value.

Here, the status change processing by the status change reception device 13 refers to lamp display on the system monitoring panel, alarm operation, and the like. Also, corresponding data 9
If no change is detected (S=0), DMA 5 is CDT
Data 6 is stored in the corresponding area of CDT data old value binary area 8.

[Problems with background technology]

In the conventional system with the above configuration, a state change is detected in word units and an interrupt is given to the CPU.
The overhead of processing within the status change reception device was large. Therefore, if the status change reception device is driven periodically to reduce this overhead, there is a drawback that it takes time from the occurrence of the status change to the status change processing.

[Purpose of the invention]

The present invention has been made to solve the above problems, and an object of the present invention is to provide an interrupt integration device that can reduce the load on the CPU.

[Summary of the invention]

In the present invention, an interrupt integration device is provided between the DMA and the status change reception device, and the generation of an interrupt signal to the status change reception device is controlled based on the relationship between the elapsed time since the previous interrupt occurrence and the cumulative state variable. It is. In other words, if one condition has changed after a predetermined period of time has elapsed since the previous interrupt signal was generated, the interrupt signal is output to the condition change acceptance device without any change, and in the case of multiple condition changes, the first When an interrupt signal is generated after a predetermined time has elapsed since the previous interrupt integrated signal was generated, only the first interrupt signal is passed through and output to the status change acceptance device, and the interrupt signal after that is In other words, cumulative variables are collected using a state change counter and output at once after a predetermined period of time.

[Embodiments of the invention]

Examples will be described below with reference to the drawings. FIG. 4 is a block diagram of an embodiment of the interrupt integration device according to the present invention. Reference numerals 1 to 11 and 13 in the figure correspond to those in FIG. 14
is an interrupt integration device that is provided between the DMA 5 and the status change reception device 13 in the CPU 7, and is used to calculate the relationship between the elapsed time since the previous interrupt occurrence and the cumulative status variable (unprocessed status variable). (as a result, depending on the load on the status change monitoring device H9-) controls the generation of an interrupt signal. This point will be discussed later.

The interrupt integration device 14 then uses the status change counter 15. It is composed of a threshold value generator 16 and a comparator 17. The status change counter 15 counts the interrupt signal 18 from the DMA 5,
The number of interrupt signals from the initial state is output to the comparator 17 as a cumulative variable 19. The negative value generator I6 generates a threshold value 20 that gradually decreases with time from the initial state and outputs it to the comparator 17.

FIG. 5 is a characteristic diagram showing the functionality of the threshold value generating device. In reality, the curve is not smooth as shown in FIG. 5, but changes stepwise as time t passes, as shown in FIG. 6.

FIG. 7 is a flowchart for explaining the operation. Information indicating the status of process information 1 is stored in the CDT slave station 2. DMA 5 via transmission line 3 and CDT master station 4
is input. The method for detecting changes in the condition of the fog MA 5 is also the same as the conventional method.

First, in step S1, the CDT data is received and the corresponding data 9 of the CDT data old value binary area 8 is taken out, and compared in step s2. As a result, if they are equal, the process returns to step s1, and if they are different, the process proceeds to step s3 where the interrupt signal ts6 is output to the interrupt integration device 14 and the CDT data 6 is written to the status change list 11 as the status change data 1o. In step s4, the interrupt signal 18 is detected by the state change counter in the interrupt integration device 14.
count up. In step S5, the cumulative variable 19 from the condition change counter 15 and the threshold value 2o from the threshold value generator 16 are compared, and the cumulative variable 19 is equal to the threshold value 2o.
If it is greater than or equal to iσ, proceed to step S6 and iσ
Immediately, the interrupt integration signal 21 is outputted and given to the status change reception device 13, and the status change counter 15 and the full light generation device 61 are output.
6 Initialize.

In this case, the cumulative state change iI, which is the output of the state change counter 15, becomes zero due to initialization, and the threshold value generator 1
The threshold value S, which is the output of 6, becomes infinite. Note that step S
In step 7, in response to the interrupt integration signal 21 from step 5elC, a new CDT is placed in the CI) T data + 11-1 value area 8.
The data includes 'A' and the process returns to step S1. The status change inquiring device 13 is driven by the interrupt integrated signal 21 and performs processing for the status change when the status change list 11 is about to become exhausted. It should be noted that the processing for a change in status includes a lamp display on the system monitoring panel, a bell alarm, etc., as in the past.

As described above, the threshold value generator 16 generates the li!f:I signal 20 which gradually decreases with the passage of time from the initial state k(]. Therefore, the previous interrupt integrated signal 2
If a sufficient period of time between I+ and 'I' has passed since the occurrence of 1, that is, if the interrupt signal 18 is input at a time interval wider than a in FIG. Even if the cumulative variable from the counter 15 is 1, the threshold value is 1, so the process moves to step S9 and immediately outputs the interrupt integration signal 21.

Next, the occurrence of multiple deterioration will be explained. In this case also D
If the first interrupt signal 18 from MA 5 is more than a time elapsed since the previous generation of the interrupt integrated signal, the interrupt integrated signal 21 is immediately generated as described above. However, at that time, the threshold value generator 16 is initialized and the threshold value 20 becomes infinite, so that the second and subsequent interrupt signals other than the first are stored in the state change counter 15. Next, the interrupt integrated signal 21 is generated either when the cumulative variable exceeds the threshold value over time, or when the threshold value falls below the cumulative change over time.

First, step S1. , the subsequent cumulative variable is counted, and if the cumulative variable is larger than the threshold, the process moves from step Sll to step S12, and the interrupt is integrated after the time required for the cumulative variable to rise above the threshold. Generate a signal. Similarly, in step S+3, the time during which M decreases by 1 is counted, and after the time required for the threshold value to divide the cumulative variable by T1, the process moves from step S14 to step 81B, and an interrupt integration signal is generated. In this case as well, the CDT data old value binary area is included, and then the process returns to step S1, as described above.

Here, the time a during which the threshold gradually decreases from the initial state to 1 (state change) must be shorter than the transmission cycle time of the CDT. In addition, the relationship between the threshold value and time is determined by the processing capacity of the status change reception device or the CPU. That is, if the processing capacity is sufficient, 1. The iξ1 value may drop rapidly over time. On the other hand, if the processing capacity is insufficient, the relationship must be determined so that the threshold value decreases slowly.

FIG. 8 is a time chart showing the difference in interrupt generation between the conventional method and the method of the present invention.

(2) shows how an interrupt occurs in a conventional method in which an interrupt occurs immediately upon occurrence of a status change. In this method, since there is no time lag between the occurrence of a state change and the occurrence of an interrupt, the occurrence of a state change can be quickly known, but it has the disadvantage that system overhead increases when multiple state changes occur.

(2) is a different conventional method in which interrupts are generated periodically. This method does not increase system overhead even when multiple conditions change, but interrupts are generated (processed) from the occurrence of a condition change.
There is a time lag.

This is a fatal drawback when considering the occurrence of multiple situations due to accidents, etc.

(2) shows how an interrupt occurs in the case according to the present invention.

For sporadic occurrences of status changes during normal times, interrupts are immediately generated (processed). In addition, in the case of multiple occurrences due to accidents, etc., it is necessary to notify (or hint) of the occurrence of accidents, etc.
For the first situation, an interrupt is immediately generated (processed),
For multiple subsequent conditions, interrupts are generated and processed in an appropriately integrated manner so as not to increase system overhead.

〔Effect of the invention〕

As explained above, according to the present invention, sporadically occurring conditions are handled without time delay, and when multiple conditions occur due to an accident, the first of the multiple conditions is immediately treated. Since the system is structured so that multiple status changes are processed at the same time for subsequent status changes, not only does the overhead within the status change reception device become smaller, but the time from the occurrence of a status change to the status change processing is also fixed periodic. It is possible to provide an interrupt integration device that can be made shorter than that of , and that can quickly receive the first report in the event of a multiplex event.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a conventional system, Fig. 2 is a configuration diagram of CDT data, Fig. 3 is a CDT old value binary composition corresponding to CDT data, and Fig. 4 is an illustration of an interrupt integration device according to the present invention. Embodiment configuration diagram, FIGS. 5 and 6 are characteristic diagrams showing the functions of the threshold value generating device, FIG. 7 is a flowchart for explaining fJ'+1, and FIG. 8 is a diagram showing the distribution by the conventional method and the present invention method. This is a time chart that compares and shows differences in the occurrence of such charges. ■...Process information, 2...CDT slave station, 3...
・Transmission path, 4...CDT master station, 5...DMA,
6...CDT data, 7...CPU, 8...
・CDT data old value binary area...corresponding data, 1
0... Condition change data, 11... Condition change list, 12.1
8... Interrupt signal, 13... Status change reception device, 14...
- Interrupt integration device, 15... Status change counter, 16...
Threshold generator, 17... Comparator, 19... Cumulative variable, 20... Threshold, 21... Interrupt integrated signal. Patent applicant: Tokyo Shibaura Tunke Co., Ltd. Agent: Patent attorney Nori Ishii

Claims (1)

[Claims] An interrupt device that introduces input information from an information transmission device into a computer and performs interrupt processing using an interrupt signal when the state of the input information changes, includes a state change counter that counts input interrupt signals, and an initial state. and a comparator that compares the output of the condition change counter with the output of the threshold value generation device 1, respectively. An interrupt integration device characterized by outputting an interrupt integration signal when the output is larger than an output from a threshold value generation device, and initializing the state change counter and the threshold value generation device.