JPS607128A - Formation of resist pattern - Google Patents
Formation of resist patternInfo
- Publication number
- JPS607128A JPS607128A JP58113755A JP11375583A JPS607128A JP S607128 A JPS607128 A JP S607128A JP 58113755 A JP58113755 A JP 58113755A JP 11375583 A JP11375583 A JP 11375583A JP S607128 A JPS607128 A JP S607128A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- resist film
- patterns
- resist
- drawn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electron Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はレジストパターンの形成方法に関し、特にラス
ク型電子ビーム露光装置で露光し、現像処理してアドレ
スユニットの整数倍以下の寸法補正がなされたレジスト
パターンの形成方法に係る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for forming a resist pattern, and in particular, the present invention relates to a method for forming a resist pattern, and in particular, the resist pattern is exposed using a rask-type electron beam exposure device, and developed to correct dimensions of an integer multiple or less of an address unit. The present invention relates to a method of forming a resist pattern.
ラスク型電子ビーム露光装置では、0.25μm。 In a rask type electron beam exposure device, it is 0.25 μm.
0.5μm或いは1.0μmというようにステップ可変
のアドレスユニットが採用されている。例えば0.5μ
mのアドレスユニットが採用されると、・ソターンデー
タは0.5μm単位で表現され、従ってそれに基づくラ
スタ方式の描画は第1ν1のモデル図に示す如く0.5
μmのビーム径、0.5μmのインクリメントでなされ
、描画されたノリーン寸法は0.5μmの整数倍のもの
として得られる。An address unit with variable steps such as 0.5 μm or 1.0 μm is used. For example 0.5μ
When an address unit of m is adopted, the soturn data is expressed in units of 0.5 μm, so the raster method drawing based on it is 0.5 μm as shown in the model diagram of the first ν1.
This is done with a beam diameter of .mu.m and an increment of 0.5 .mu.m, and the drawn Noreen dimensions are obtained as integral multiples of 0.5 .mu.m.
しかしながら、あるマスクは1.8μmの線幅を持つも
のであったジ、別のマスクは243μmの線幅を持つも
のであったシ、所望の・母ターン寸法は必ずしもアドレ
スユニットの整数倍のものであるとは限らない。このよ
うな場合はアドレスユニットの整数倍以下の寸法補正を
行なう必要がある。However, since one mask had a line width of 1.8 μm and another had a line width of 243 μm, the desired mother turn dimension is not necessarily an integer multiple of the address unit. Not necessarily. In such a case, it is necessary to perform dimension correction of an integral multiple or less of the address unit.
ところで、従来、アドレスユニットの整数倍以下の寸法
補正がなされたレジストパターンを形成する方法として
は、電子ビーム露光装置によ如露光したレジスト膜の現
像時間を変えてパターン寸法を制御する方法が行なわれ
ている。By the way, conventionally, as a method of forming a resist pattern whose dimensions have been corrected by an integral multiple of the address unit or less, the pattern dimensions are controlled by changing the development time of a resist film exposed by an electron beam exposure device. It is.
しかしながら、かかる方法にあっては、レジストパター
ンの幅がどれだけ寸法補正されたかを検出することが困
難であシ、再現性よく寸法補正されたレジストパターン
を形成することができない。However, with this method, it is difficult to detect how much the width of the resist pattern has been corrected, and it is not possible to form a resist pattern whose size has been corrected with good reproducibility.
このようなことから、本発明者らは既にラスタ型電子ビ
ーム露光装置による露光に際し、ビーム径、ビーム電流
等の電子鏡筒系のパラメータを調整してドーズ量を変化
させることによってアドレスユニットの整数倍以下の寸
法補正がなされたレジストパターンの形成方法を提案し
た(特願昭57−1369号)。この方法によれば描画
パターンが一定の場合には再現性よく寸法補正を実現す
ることが可能である。しかしながら、この方法では異種
パターンに対してはプロセス条件をわずかにシフトする
必要があり、操作が煩雑化する。しかも、プロセス条件
が一定でも、電子光学筒系のパラメータのばらつき、レ
ノスト特性のロット間のばらつきなどが寸法補正を実現
する上での再現性に悪影響を及はす。For this reason, the present inventors have already developed an integer number of address units by adjusting the parameters of the electron lens barrel system such as the beam diameter and beam current to change the dose amount during exposure using a raster type electron beam exposure system. We have proposed a method for forming a resist pattern whose dimensions have been corrected by less than double (Japanese Patent Application No. 1369/1982). According to this method, when the drawing pattern is constant, it is possible to realize dimension correction with good reproducibility. However, with this method, it is necessary to slightly shift the process conditions for different types of patterns, making the operation complicated. Moreover, even if the process conditions are constant, variations in the parameters of the electron optical barrel system, variations in Rennost characteristics between lots, etc. have a negative effect on the reproducibility in realizing dimensional correction.
本発明はアドレスユニットの整数倍以下の寸法補正がな
されたレジストパターンを簡単かつ再現性よく形成し得
る方法を提供しようとするものである。The present invention aims to provide a method for easily and reproducibly forming a resist pattern whose dimensions have been corrected by an integral multiple or less of the address unit.
本発明は基板上のレジスト膜にラスタ型電子ビーム露光
装置を用いて等間隔のアドレスユニットで電子ビームを
オン、オフさせてパターン描画を行なった後、現像処理
を施してアドレスユニットの整数倍以下の寸法補正がな
されたレジストパターンを形成するに際し、前記レジス
ト膜に電子ビームによシ・千ターン描画を行なうと共に
、該・リーン描画領域以外のレジスト膜領域にコーナが
臣にX方向及びY方向にアドレスユニットの整数倍以下
の距離で離間した一対の寸法補正検出用ノfターンを点
対称的に描画する工程と、このレジスト膜を現像液によ
シ前記一対の寸法補正検出用ノ量ターンのコーナ同志の
接触時点が終点となるように現像処理する工程とを具備
することによって、既述したレジストパターンを形成す
ることを骨子とするものである。The present invention uses a raster-type electron beam exposure device to draw a pattern on a resist film on a substrate by turning the electron beam on and off with address units at equal intervals, and then develops the resist film so that it is not more than an integer multiple of the address unit. When forming a resist pattern whose dimensions have been corrected, the resist film is written with a thousand turns using an electron beam, and the corners of the resist film area other than the lean writing area are aligned in the X and Y directions. a step of point-symmetrically drawing a pair of dimensional correction detection no.f turns separated by a distance equal to or less than an integral multiple of the address unit; The gist of this method is to form the above-mentioned resist pattern by including a step of developing so that the end point is the point of contact between the corners of the resist pattern.
5− 〔発明の実施例〕 以下、本発明の詳細な説明する。5- [Embodiments of the invention] The present invention will be explained in detail below.
まず、ブランクマスク上にボッ型レジスト、例えばポリ
メチルメタクリレ−) (PMMA)を回転塗布し、乾
燥、グリベーク処理を施して厚さ0.5μmのポジ型レ
ジスト膜1を形成した。First, a blank resist such as polymethyl methacrylate (PMMA) was spin-coated on a blank mask, dried, and subjected to a glybake treatment to form a positive resist film 1 having a thickness of 0.5 μm.
次いで、レジスト膜1上にラスタ型電子ビーム露光装置
を用いてアrレスユニッ)0.5μm、加速電圧20
keV、ドーズ量9.2μch2の条件にてデータ上1
0μm角のパターン(図示せず)を描画した。つづいて
、該・母ターン領域以外のレジスト膜1の領域に同様な
条件にてデータ上4μm×16μmで、特定のコーナ部
の座標が(x1+y1 ) + (X2 +y;)の2
つの矩形状をなす寸法補正検出用パター721.22
を描画した。Next, on the resist film 1, using a raster type electron beam exposure device, an arless unit (Arres unit) of 0.5 μm and an accelerating voltage of 20
1 on the data under the conditions of keV and dose amount 9.2μch2
A 0 μm square pattern (not shown) was drawn. Next, under the same conditions, the area of the resist film 1 other than the main turn area is 4 μm x 16 μm in data, and the coordinates of a specific corner are (x1 + y1) + (X2 + y;) 2
Dimensional correction detection putter 721.22 having a rectangular shape
was drawn.
ひきつづき、前記パターン21+22の描画開始位置を
アドレスユニットの整数倍以下の量だけずらせてコーナ
部に対応する座標が下記式に示す(XIZ 7+’)
+ (x2’+yz’)でデータ上4.c+mX16μ
mの矩形状をなす寸法補正検出用パターン−6=
21’、22′を描画した(第2図図示)。Continuing, the drawing start position of the pattern 21+22 is shifted by an amount less than an integral multiple of the address unit, and the coordinates corresponding to the corner part are shown in the following formula (XIZ 7+')
+ (x2'+yz') on the data 4. c+mX16μ
A dimension correction detection pattern-6=21', 22' having a rectangular shape of m was drawn (as shown in FIG. 2).
xl’=x1−ΔL−(aXi)
y重′=y1+ΔL−1−(bXg)
X2’=12−ΔL−(aXr)
72””)’2+ΔL+(bXa)
但し、ΔL−アドレスユニットの整数倍以下の寸法補正
値、例えば0.6μm、
a−X方向パターン幅(4μm)、
b=y方向・やターン長さく16μm)、S=ニスケー
ルファクタ例えば1.2)。xl'=x1-ΔL-(aXi) y weight'=y1+ΔL-1-(bXg) dimensional correction value, for example 0.6 μm, a-X direction pattern width (4 μm), b=y direction/turn length 16 μm), S=niscale factor (for example 1.2).
上述した電子ビーム露光によシ同第2図に示した如く互
にコーナ部自+C1′及びC2+C11′がアドレスユ
ニットの整数倍以下の寸法補正値(データ上0.6μm
)の距離で離間した点対称的な二対の矩形状をなす寸法
補正検出用パターン21.21’及び22.22’が描
画された。By the electron beam exposure described above, as shown in FIG.
Two pairs of point-symmetric rectangular dimension correction detection patterns 21.21' and 22.22' separated by a distance of ) were drawn.
次いで、電子ビーム描画後のレジスト膜をメチルイソグ
チルケトン(現像液)によ#)現像処理した後、第3図
(、)に示す如く寸法補正検出用ノ平ターン21 r
21’ + 22 + 22’の現像により形成された
2組の対をなす検出用レジスト・母ターン31+31’
及び3z+、9jのコーナ部C1。Next, after developing the resist film after electron beam drawing with methyl isobutyl ketone (developer), a flat turn 21 r for dimension correction detection is formed as shown in FIG.
Two pairs of detection resist/mother turns 31+31' formed by developing 21'+22+22'
and corner portion C1 of 3z+, 9j.
C1′及びC2+C2’が接触した時に現像を停止させ
ブランクマスクの79ターン形成領域にレジストパター
ン(図示せず)を形成した。When C1' and C2+C2' came into contact, development was stopped and a resist pattern (not shown) was formed in the 79 turn formation region of the blank mask.
しかして、本実施例によ多形成されたレジストパターン
の寸法を測定したところ、以下に示す式の如(12,8
μm角であった。When the dimensions of the resist pattern formed in this example were measured, it was found that the following equation (12, 8
It was μm square.
10×S+ΔL=10 Xl、2X0.6=12.8(
μm)
この測定結果よシ明らかな如く、アドレスユニットの整
数倍以下の寸法補正(ここでは0.6μm)がなされた
レジストパターンを形成できることがわかる。なお、前
記現像工程において、第3図(b)に示す如く寸法補正
検出用・母ターン2I + 21Z 22 * 22’
の現像によ多形成された2紹の対をなす検出用レジスト
膜やターン41 。10×S+ΔL=10Xl, 2X0.6=12.8(
.mu.m) As is clear from the measurement results, it is possible to form a resist pattern whose dimensions are corrected by an integral multiple or less of the address unit (here, 0.6 .mu.m). In addition, in the development process, as shown in FIG. 3(b), the main turn 2I + 21Z 22 * 22' for size correction detection is used.
Two pairs of detection resist films and turns 41 were formed by the development of the film.
41′及び’2+42′のコーナ部C1、C,’及びC
8+C2’が接触しない状態で現像を停止したところ、
目的とする寸法補正値よp 0.15μm不足した寸法
をもつレジストパターンがブランクマスク上に形成され
た。41' and '2+42' corner parts C1, C,' and C
When development was stopped with 8+C2' not in contact,
A resist pattern having a dimension p0.15 μm short of the target dimension correction value was formed on the blank mask.
したがって、本発明によればレジスト膜のパターン形成
領域とは別の領域にアドレスユニットの整数倍以下の寸
法補正値に対応した距離だけ離間して配置した対をなす
寸法補正検出用パターンを形成し、現像工程での現像終
了を、これらパターンの検出用レジストパターンのコー
ナ部の接触時点で判定することによって、前記ノ4ター
ン形成領域にアドレスユニットの整数倍以下の寸法補正
がなされたレジスト・母ターンをブランクマスク上に再
現性よく、かつ簡単に形成できる。Therefore, according to the present invention, a pair of dimension correction detection patterns are formed in a region different from the pattern formation region of the resist film and are spaced apart by a distance corresponding to a dimension correction value that is an integral multiple of the address unit or less. By determining the end of development in the development process at the time when the corner portions of the resist patterns for detection of these patterns come into contact with each other, a resist/matrix whose dimensions have been corrected by an integer multiple or less of the address unit in the 4-turn formation area is obtained. Turns can be easily formed on a blank mask with good reproducibility.
なお、上記実施例では基板としてブランクマスクを用い
たが、これに限定されず、例えばウェハを用いてもよい
。Note that although a blank mask was used as the substrate in the above embodiment, the substrate is not limited to this, and for example, a wafer may be used.
上記実施例ではレジスト膜としてPMMAを用いたが、
これに限定されず、他のポジ型レジスト或いはネガ型レ
ジストも同様に用いることができる。In the above example, PMMA was used as the resist film, but
The present invention is not limited thereto, and other positive resists or negative resists can be used as well.
9−
上記実施例では先に寸法補正検出用・fターン21+2
2を描画し、描画開始位置をアドレスパターン21’
+ 22’を描画したが、ユニットの整数倍以下の量だ
けずらせて偏向開始位置をずらすようにしてもよい。9- In the above embodiment, the f-turn 21+2 for dimension correction detection is first
2, and set the drawing start position to address pattern 21'
+22' is drawn, but the deflection start position may be shifted by an amount equal to or less than an integral multiple of the unit.
以上詳述した如く、本発明によればアドレスユニットの
整数倍以下の寸法補正がなされたレジストパターンを簡
単かつ再現性よく形成し得る方法を提供できる。As described in detail above, according to the present invention, it is possible to provide a method for easily and reproducibly forming a resist pattern whose dimensions have been corrected by an integer multiple or less of the address unit.
第1図はマスク型電子ビーム露光装置を用いて0.5μ
mのアドレスユニットデータにより描画した状態を示す
観明図、第2図は本発明の実施例においてレジスト膜に
描画された寸法補正検出用パターンを示す平面図、第3
図(a) 、 (b)は同実施例のレジスト膜を現像し
た時の検出用レジスト・クターンを示す平面図である。
1・・・ポジ型レジスト膜、21.2..21’・・・
パターン、31 + 32 + JIZ 32’+41
+10−
42 r 41’142’・・・レジストパターン。
−11−
第1 図
第2図
C)
句
^ 寸
、0Figure 1 shows a 0.5 μm exposure using a mask-type electron beam exposure system.
FIG. 2 is a plan view showing a dimension correction detection pattern drawn on a resist film in an embodiment of the present invention; FIG.
Figures (a) and (b) are plan views showing detection resist patterns when the resist film of the same example is developed. 1... Positive resist film, 21.2. .. 21'...
Pattern, 31 + 32 + JIZ 32'+41
+10- 42 r 41'142'...Resist pattern. -11- Fig. 1 Fig. 2 C) haiku ^ sun, 0
Claims (1)
いて等間隔のアドレスユニットで電子ビームをオン、オ
フさせてパターン描画を行なった後、現像処理を施して
アドレスユニットの整数倍以下の寸法補正がなされたレ
ジストパターンを形成するに際し、前記レジスト膜に電
子ビームによりパターン描画を行なうと共に、該パター
ン描画領域以外のレジスト膜領域にコーナが互にX方向
及びY方向にアドレスユニットの整数倍以下の距離で離
間した一対の寸法補正検出用・母ターンを点対称的に描
画する工程と、このレジスト膜を現像液によシ前記一対
の寸法補正検出用パターンのコーナ同志の接触時点が終
点となるように現像処理する工程とを具備したことを特
徴とするレジスト・母ターンの形成方法。 (2)一対の寸法補正検出用・そターンが矩形状をなす
ことを特徴とする特許請求の範囲第1項記載のレジス)
1+ターンの形成方法。 (3)一対の寸法補正検出用パターンをレジスト膜に複
数組描画せしめることを特徴とする特許請求の範囲第1
項又は第2項記載のレジストパターンの形成方法。[Claims] After drawing a pattern on the resist film on the substrate using a Rusk-type electron beam scanning device by turning the electron beam on and off with address units at equal intervals, a development process is performed to form the address units. When forming a resist pattern whose dimensions have been corrected by an integral multiple of A process of point-symmetrically drawing a pair of dimensional correction detection/mother turns spaced apart by a distance equal to or less than an integral multiple of the address unit, and a step of drawing the resist film with a developer to form corners of the pair of dimensional correction detection patterns. A method for forming a resist/mother turn, comprising the step of developing so that the point of contact is the end point. (2) A pair of dimension correction detection resistors according to claim 1, characterized in that the turns thereof have a rectangular shape.
How to form a 1+ turn. (3) Claim 1, characterized in that a plurality of pairs of dimension correction detection patterns are drawn on the resist film.
The method for forming a resist pattern according to item 1 or 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58113755A JPS607128A (en) | 1983-06-24 | 1983-06-24 | Formation of resist pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58113755A JPS607128A (en) | 1983-06-24 | 1983-06-24 | Formation of resist pattern |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS607128A true JPS607128A (en) | 1985-01-14 |
JPH0542809B2 JPH0542809B2 (en) | 1993-06-29 |
Family
ID=14620307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58113755A Granted JPS607128A (en) | 1983-06-24 | 1983-06-24 | Formation of resist pattern |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS607128A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6641482B2 (en) | 1999-10-04 | 2003-11-04 | Nintendo Co., Ltd. | Portable game apparatus with acceleration sensor and information storage medium storing a game program |
US7223173B2 (en) | 1999-10-04 | 2007-05-29 | Nintendo Co., Ltd. | Game system and game information storage medium used for same |
US11211227B2 (en) | 2019-09-10 | 2021-12-28 | Nuflare Technology, Inc. | Multi charged particle beam evaluation method and multi charged particle beam writing device |
-
1983
- 1983-06-24 JP JP58113755A patent/JPS607128A/en active Granted
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6641482B2 (en) | 1999-10-04 | 2003-11-04 | Nintendo Co., Ltd. | Portable game apparatus with acceleration sensor and information storage medium storing a game program |
US7223173B2 (en) | 1999-10-04 | 2007-05-29 | Nintendo Co., Ltd. | Game system and game information storage medium used for same |
US7601066B1 (en) | 1999-10-04 | 2009-10-13 | Nintendo Co., Ltd. | Game system and game information storage medium used for same |
US8562402B2 (en) | 1999-10-04 | 2013-10-22 | Nintendo Co., Ltd. | Game system and game information storage medium used for same |
US9138645B2 (en) | 1999-10-04 | 2015-09-22 | Nintendo Co., Ltd. | Game system and game information storage medium used for same |
US9205332B2 (en) | 1999-10-04 | 2015-12-08 | Nintendo Co., Ltd. | Game system and game information storage medium used for same |
US9579565B2 (en) | 1999-10-04 | 2017-02-28 | Nintendo Co., Ltd. | Game system and game information storage medium used for same |
US10046231B2 (en) | 1999-10-04 | 2018-08-14 | Nintendo Co., Ltd. | Game system and game information storage medium used for same |
US11211227B2 (en) | 2019-09-10 | 2021-12-28 | Nuflare Technology, Inc. | Multi charged particle beam evaluation method and multi charged particle beam writing device |
Also Published As
Publication number | Publication date |
---|---|
JPH0542809B2 (en) | 1993-06-29 |
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