JPS606873A - Digital speed detection system of resolver - Google Patents

Abstract

PURPOSE:To eliminate the need for the processing time of a computer by feeding the deviation between a resolver detection frequency and a resolver excitation frequency back, and computing a resolver rotation frequency through hardware configuration. CONSTITUTION:A resolver 1 has exciting windings 1a and 1b and a detection winding 1c. The exciting windings 1a and 1b are supplied with an exciting current from a resolver exciting circuit 2. The output of the exciting circuit 2 and the output of the detection winding 1c are inputted to an up/down counter 5 through waveform shaping circuits 4 and 3. A binary digital number D proportional to the difference between the resolver excitation frequency and resolver detection frequency is supplied to an absolute value circuit 6. A frequency proportional to the digital number D is fed back to the input terminal of the up/ down counter 5 to detect the rotating speed of the resolver 1 as the counted value of the up/down counter 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for digitally detecting the rotational speed of a rotating electric machine or the like using resolute noises arranged on the rotating shaft.

2. Description of the Related Art Conventionally, in a digital control device using a microprocessor or the like, resolute sensors are used to detect the speed of a rotating electric machine.

One method of detecting the rotational speed of a resolver as a digital quantity is to count the period of the resolver detection frequency as the number of pulses of a high-frequency clock, and to detect the reverse rotational speed by calculating the counted value. It is being

The resolver detection frequency changes depending on the rotation speed.

Therefore, in the method of counting the period of the resolver detection frequency, the one resolution period of the detection chamber changes depending on the rotational speed. For example, when considering an excitation frequency of 18 kHz and a resolute pole count of 72, the sampling period changes by a width of 1:20 for a speed change of ±11000 Orp. When a speed loop is configured using this detection method, the loop conditions change depending on the rotation speed, so a high speed loop gain cannot be achieved, and control responsiveness deteriorates.

Another method is to make the sampling period constant (Japanese Patent Laid-Open No. 57-3335'5). This method is
The resolver rotation frequency is multiplied by using a phase lock droop, and the multiplied resolver detection frequency during a fixed sampling period is counted.

In this method, the rotation speed is calculated from the multiplied resolver detection frequency through arithmetic processing.
The value at zero rotation speed must be subtracted. When performing highly accurate detection, the count value or the value of the rotational speed to be subtracted becomes large, and the computer performs double word length (32 bit) processing. This is considered to have the drawbacks of increasing the processing time of the computer and increasing the number of input ports to the computer.

Here, the present invention overcomes the difficulties of the conventional method and calculates the resolver rotation frequency using a hardware configuration by feeding back the deviation between the resolver detection frequency and the resolver excitation frequency, thereby saving computer processing time.・To provide various di-notal speed detection methods,
That purpose.

Now, the resolver detection frequency f. is the excitation frequency f during forward rotation. The excitation frequency f becomes higher during negative rotation. Suppose it becomes lower. The detection frequency f of the resolute 9 is expressed by the following equation (1) when the rotational speed is N (rpm).

However, P is the number of poles of the resolver and its sign indicates the rotation direction.

A block diagram showing the configuration of an embodiment of the present invention is shown in FIG.

1 is a resolver with excitation windings la and lb and detection windings 1c installed on the rotating shaft of a rotary sleeper, etc.; 2 is a resolver with 5in2πf or c082πfo on the two excitation windings 1a and lb of the resolver 1; 3 or 4 is a resolver detection frequency f. Or resolver excitation frequency f. A waveform shaping circuit that shapes the waveform of , fM are the output frequencies of the rate multiplier 7.

By the way, the operation when the resolver is rotating upward (f, > fo) will be explained.

When the up/down counter 5 is positive, the adder circuit 8.9 functions as an adder circuit f. +fM is derived, and when the up/down counter 5 is negative, the circuit 9 acts as an adder circuit and generates f and +fM.

However, since the resolver 1 is rotating in the forward direction, the up (UP) input of the up/down counter 5 is
f to v down (DOWN) input. If you enter fo
>fo, and the up/down counter 5 detects the detection frequency f and the excitation frequency f of the resolver 1. outputs the difference as a binary positive digital number (D = f, = f
. ).

The digital number is supplied to the absolute value circuit 6, but since the value of D is positive, there is no numerical conversion and the digital number is supplied to the rate multiplier 7 as it is.

The rate multi-series controller 7 uses a 5-inary digital number to determine the clock frequency f. This is a variable frequency oscillator that divides and outputs the frequency. When the rate multiplier 71M pits are used, the output frequency fM is expressed by (Equation 2).

The output fM of the rate multilayer 7 is the direction switching circuit lO.
Because resolver 1 rotates in the normal direction, <fo>
It is added to the t Ok addition circuit 8.

Therefore, the up/down counter 5 stops counting when the frequency of the up input and the frequency of the down input match.

On the other hand, consider a case where the resolvers 1 are rotating in the negative direction.

f, <f. Therefore, the output of the up/down counter 5 is a binary negative digital number Di. The absolute value circuit 6 converts the negative digital number into a positive digital number and supplies it to the rate multizolar layer 7. Also, the rate multi-scillator output fM is added to the adder circuit 9 by the direction switching circuit lO. Therefore, as in the case of forward rotation of the resolver 1, the up/down/counter 5 stops counting when the frequencies of the up input and the down input match.

In this way, the resolver excitation frequency f. And Resol,?
Detection frequency f. and resolver detection frequency f.

Detects an infinitely digital number proportional to the difference between
By feeding back the frequency fM proportional to this digital number to the input terminal of the up/down counter 50, the rotational speed of each resolver 1 can be detected.

That is, when the up/down/counter 5 stops counting, (Equation 3) holds true.

fθ=fo±fM Therefore, the rotation frequency fR of the resolver 1 is expressed as (Equation 4).

fR=fc-f.

=±7X fc ・・・・・・・・・・・・・・・(4
(Formula) However, the sign represents the direction of rotation.

As shown in equation (4), the resolver rotation speed can be digitally detected as a digital number of ζ inary.

As can be seen from (Equation 4), the detected rotational speed Hy.

is the excitation frequency f of the resolvers 1. Contains no ingredients.

Therefore, since it is not necessary to calculate the entire rotational speed from the detected data, the processing time of a separate computer can be saved, and the input port of the computer can also be used effectively.

FIG. 2 is a block diagram of main parts of another embodiment of the present invention.

This embodiment has a circuit configuration that increases the output of the rate multiplier 7 by N4 times.

From (3 formulas) Therefore, the detected digital number becomes (Equation 5).

When inputting the digital rotational speed detection value to the computer, the counter output is performed through a latch circuit. Since the counter 5 constantly counts the rotational speed, the computer can take in the detected rotational speed values at constant spring/spring intervals.

Here, specific numerical values will be given and explained.

The number of poles P of resolvers 1 is 72 poles, the resolver rotation speed N is 1000 Orpm, the number of bits M of rate multiplier 7 is 16 bits, and the clock frequency fC is 96 kHz.
z, then the rotational speed detection scale in one embodiment of the present invention shown in FIG. When N,=4, it becomes.

FIG. 3 is a block diagram of main parts of another embodiment of the present invention.

This embodiment has a circuit configuration in which an addition/subtraction circuit 13 is inserted between the up/down/counter 5 and the absolute value circuit 6 in place of the addition circuit 8.9 and the direction switching circuit 1O of FIG.

Addition/subtraction circuit 13 has a certain set value. is supplied in advance. This setting value. is the value at which the counter 5 output is zero when the resolver rotation speed is zero, that is, when the counter 5 output is zero, the rate multiplier 7 output fM is the resolver excitation frequency f. Let the value be equal to .

The rotational speed fR (resolver modulation frequency) of each resolver 1 is expressed by (Equation 6).

fθ= fM fR=foif.

Thus, according to the present invention, the following effects are recognized.

◎ Since the counter output always counts the resolver rotation speed, it is possible to perform constant sampling on the computer.

■ Even when the clock frequency is set to -bo, the detection resolution can be increased to any value.

@ Since the resolver rotation speed can be detected as the resolver modulation frequency fR, the detected value is a value proportional to the resolver rotation speed. Therefore, the processing time required for arithmetic processing by a computer is uncertain.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the circuit configuration of one embodiment of the present invention, FIG. 2 is a block diagram showing the main parts of the embodiment of the invention, and FIG. 3 is the main part of another embodiment of the invention. FIG. 1... Resolver with excitation windings 1a and 1b and detection winding 1c, 2... Resolver excitation circuit, 3.4... Waveform shaping circuit, 5... Up/down counter, 6...・
Absolute value circuit, 7... Rate multi-series, 8, 9...
... Addition/subtraction circuit, lO... Direction switching circuit, 11...
Clock oscillator, 12... Frequency dividing circuit, 13... Addition/subtraction circuit.

Claims (1)

[Claims] 1. A resolver that detects the speed of a rotating body, a counter that counts the difference between the detection frequency of this resolver and an excitation frequency, and an oscillator that generates a frequency proportional to the output of this counter. Digital speed detection, characterized in that the output of the oscillator is added to the excitation frequency or detection frequency of the resolver to form a feed barrier cruise, thereby generating a resolved digital speed signal. method. 2. The resolute digital speed detection method according to claim 1, wherein the detection resolution is improved by additionally connecting a frequency dividing circuit to the output stage of the oscillator.