JPS6066577A - Picture signal binary-coding circuit of facsimile equipment - Google Patents

Picture signal binary-coding circuit of facsimile equipment

Info

Publication number
JPS6066577A
JPS6066577A JP58174783A JP17478383A JPS6066577A JP S6066577 A JPS6066577 A JP S6066577A JP 58174783 A JP58174783 A JP 58174783A JP 17478383 A JP17478383 A JP 17478383A JP S6066577 A JPS6066577 A JP S6066577A
Authority
JP
Japan
Prior art keywords
average density
circuit
signal
image signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58174783A
Other languages
Japanese (ja)
Inventor
Toshiro Koshimizu
越水 敏郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58174783A priority Critical patent/JPS6066577A/en
Publication of JPS6066577A publication Critical patent/JPS6066577A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a fixed output for variation of depth of an original by determining a threshold level and binary-coding according to the relation to the average density around a read picture element. CONSTITUTION:In an average density circuit 3, a picture signal 6 and a 2-line delayed picture signal 8 are added and inputted to an ROM13 as an address signal together with a 1-line delayed picture signal 7. Data of the ROM13 is written beforehand to become a 3-line average density 16. An adder 14 adds above-mentioned average density for 32 picture elements and outputs to an ROM15 as an address signal, and the average density of an area shown in the figure is outputted from the ROM15 as an average density signal 9. A delay circuit 4 delays the signal 7 in the horizontal direction to become the center 17 of the average density area and outputs a delayed picture signal 10 thus obtained. A threshold circuit 5 is made up of an ROM that converts the signals 9 and 10 to addresses, sets the output to become white or black in a fixed leve, and outputs a binary coding signal 11.

Description

【発明の詳細な説明】 本発明は、画信号λ値化回路に関し、特に、ファクシミ
リ装置の原稿読み取シ画信号のλ値化処理に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal λ value conversion circuit, and more particularly to λ value conversion processing of an image signal read from a facsimile machine.

従来のファクシミリ装置においては、送信原稿を読み取
った画信号を白、黒ス値化する場合に、読へ取っている
画信号を、即時にあらかじめ決められ固定されたスライ
スレベルによりλ値化するか、もしくは画信号の変化に
従って変化する70−ティングスライスレベルによりλ
値化が行われていた。この場合、読み取った両信号をそ
の場でλ値化してしまうために、yX稿の0淡に対して
固定スライスの場合には追従は不可能であり、また、画
信号によりスライスレベルを変化させる場合でも直前の
走査中のデータとの関係からしかIB従させることが出
来なかった。
In conventional facsimile machines, when converting the image signal obtained by reading a transmitted document into white and black slice values, it is necessary to immediately convert the image signal being read into lambda values using a predetermined and fixed slice level. , or by using a 70-ting slice level that changes according to changes in the image signal.
Valuation was being carried out. In this case, since both read signals are converted into λ values on the spot, it is impossible to follow the 0-darkness of the yX draft in the case of a fixed slice, and the slice level is changed depending on the image signal. Even in this case, it was possible to make the IB follow only from the relationship with the data being scanned immediately before.

本発8Aは従来の技術に内在す、乙上記諸欠点を解消す
る為になされたものであり、従って本発す)の目的は原
稿を読み取ったアナログの画(、′;号をλ値化しよう
としているi81!liI素に対して、その画素の周辺
)平均濃度との関係によシスレツショルドレベルを決め
てλ値化することによシ原稿の礎淡の変化に対して常に
一定の出力を71JられるようにLlc画信号の新規な
λ値化回路を提供することにある。
This invention 8A was made to eliminate the above-mentioned shortcomings inherent in the conventional technology, and the purpose of this invention is to convert the analog image (,'; For the i81!liI pixel, the threshold level is determined based on the relationship with the average density of the surrounding area of that pixel, and by converting it into a λ value, the output is always constant regardless of changes in the background light of the original. The object of the present invention is to provide a novel λ value converting circuit for Llc image signals so that 71J can be obtained.

上記目的を連成する為に、本発明によるファクシミリ装
置の画信号λ値化回路は、送信原稿を読み取ったアナロ
グ画信号をNピットのディジタル画素に変換する原稿読
み取シ回路と、該原稿読み取り回路から送られてきたデ
ィジタル画素を数ライン分記憶するラインメモリ回路と
、前記原稿読み取り回路からのディジタル画素と前記ラ
インメモリ回路の出力からディジタル画素に対する任意
の領域の平均濃度を出力する平均濃度回路と、λ値化し
ようとしているディジタル画素が平均濃度の領域の中央
にくるように各ディジタル画素全遅延させる遅延回路と
、平均濃度出力とその領域の中央になるよう遅延された
ディジタル画素を用いてスレッショルドレベルを決定し
ディジタル画素をユ(m化するスレッショルド回路を含
んで構成される。
In order to achieve the above object, the image signal λ value converting circuit of the facsimile apparatus according to the present invention includes a document reading circuit that converts an analog image signal read from a transmitted document into N-pit digital pixels, and a document reading circuit a line memory circuit that stores several lines of digital pixels sent from the document reading circuit; and an average density circuit that outputs the average density of an arbitrary area for digital pixels from the digital pixels from the document reading circuit and the output of the line memory circuit. , a delay circuit that delays each digital pixel so that the digital pixel to be converted into a λ value is at the center of the area of average density, and a threshold using the average density output and the digital pixel delayed so that it is at the center of the area. It is configured to include a threshold circuit that determines the level and converts the digital pixels into m.

以下本発明をその好ましい一実施例について図面を参照
して具体的に説明する。
Hereinafter, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

@1図は本発明の一実施例を示すブロック構成図である
。図において、参照番号/は原稿読み取9回路を示し、
該原稿読み取り回路/は送信原稿f:読み取り画信号6
として例えば/7ビツトのデ・rジタル信号を出力する
。ラインメモリ回IP’s 、2 tJ: /ラインず
つ一ライン記憶できる。しうになっており/ライン遅延
画信号り1.2ライン遅延画イ8号、(を出力する。平
均濃度回路3は画信号A、/ライン遅延画信号7.22
イン遅延画信号1?を入力し平均a度伯号9を出力\す
る。
Figure @1 is a block configuration diagram showing an embodiment of the present invention. In the figure, the reference number / indicates nine original reading circuits,
The original reading circuit/transmission original f: reading image signal 6
For example, a /7 bit digital signal is output. Line memory times IP's, 2 tJ: /line can be stored one line at a time. The average density circuit 3 outputs the image signal A and the /line delayed image signal 7.22.
In-delay image signal 1? is input and the average a degree number 9 is output\.

第一図は平均濃度回路、?のブロック図である。The first figure is the average concentration circuit, ? FIG.

画信号乙及びコライン連延画信号には、加算器/コによ
り加算され、lライン遅延画信−弓7と共にRC・zA
/3にアドレス信号として入力される。ここで、 i(
OM/3のデータを3ライン平均濃度16となるようや
1/!込んでおき、これを加n器/y、に出力する。加
↓1蓉1÷//1.では3ラインの平均濃度回路コ画免
分加194シ、これをROM 15にアドレス信号とし
て出力し、ROI4 /、5よシ第3図に示す領域の平
均濃度を平均tユ度信号ワとして出力する。
The image signal B and the co-line continuous image signal are added by an adder/co, and are added together with the l-line delayed image signal - RC zA.
/3 is input as an address signal. Here, i(
The OM/3 data is 3 lines with an average density of 16 or 1/! This is then output to the adder/y. Add↓1蓉1÷//1. Now add the 3-line average density circuit fraction 194 and output this as an address signal to the ROM 15, and output the average density of the area shown in FIG. do.

遅延回路りでは、lライン遅延画信号7を入力し、これ
を第、7図の平均濃度領域の中心/lになるように水平
方向に76ビツト遅延させた遅延画信号10を出力する
The delay circuit inputs the 1-line delayed image signal 7 and outputs a delayed image signal 10 which is delayed by 76 bits in the horizontal direction so as to be at the center /l of the average density area in FIG.

スレッショルド回路Sは平均濃度信号9と遅延画信号I
OをアドレスとするROMからなシ、この■の出力が一
定のスレッショルドレベルにより白又は然となるように
設定し、これをa値化信号/lとして出力する。
The threshold circuit S has an average density signal 9 and a delayed image signal I.
From the ROM whose address is O, the output of this (2) is set to be white or natural depending on a certain threshold level, and is output as an a-valued signal /l.

第り図はスレッショルドレベルの実際の設定例を示す。Figure 2 shows an example of actual setting of the threshold level.

つまシ、平均濃度に対して画信号レベルが図中のスレッ
ショルドレベル/lよシ高い場合には黒、低い場合には
白と判定される。
In other words, if the image signal level is higher than the threshold level /l in the figure with respect to the average density, it is determined to be black, and if it is lower, it is determined to be white.

本発明は、以上説明したように、画信号に対する任意の
領域の平均濃度と画信号レベルの関係によシ、原稿読み
取シ画信号をλ値化することができる。
As described above, the present invention can convert an original read image signal into a λ value based on the relationship between the image signal level and the average density of an arbitrary area with respect to the image signal.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック構成図、第一
図は第1図に示した平均の度回路の詳細なブロック構成
図、第3図は本発明における平均0度の領j戊を示す概
略説明図、第9図はスレッショルドレベルの実際の設定
例を示す図である。 l・・・原稿読み取シ回路、コ・・・2インメモリ回路
。 3・・・平均濃度回路、q・・・遅延回路、S・・・ス
レッショルド回路、6・・・画信号、7・・・/ライン
遅延画信号、t・・・λライン遅延画信号、り・・・平
均濃度信号、io・・・遅延画信号、/ハ・・λ値化信
号、/ユ・・・加算器、/3・・・ROM、/4’・・
・加算器、/S・・・ROM、/A・・・3ライン平均
濃度、 /7・・・中心、1g・・・スレッショルドレ
ベル特許出願人 日本電気株式会社 代 理 人 弁理士 熊谷雄太部 13 14 15 第2 図 第41叉1
FIG. 1 is a block configuration diagram showing an embodiment of the present invention, FIG. 1 is a detailed block configuration diagram of the average degree circuit shown in FIG. 1, and FIG. FIG. 9 is a diagram showing an example of actual setting of the threshold level. l... Original reading circuit, Co... 2-in memory circuit. 3... Average density circuit, q... Delay circuit, S... Threshold circuit, 6... Image signal, 7.../line delayed image signal, t... λ line delayed image signal, ...average density signal, io...delayed image signal, /c...λ-valued signal, /u...adder, /3...ROM, /4'...
・Adder, /S...ROM, /A...3 line average density, /7...center, 1g...threshold level Patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai 13 14 15 2nd figure 41 prong 1

Claims (1)

【特許請求の範囲】[Claims] アナログ画信号をNビットのディジタル画素に変換する
原稿読み取シ回路と、該原稿読み取シ回路から出力され
るディジタル画素を数ライン分記憶するラインメモリ回
路と、ディジタル画素に対して任意の領域の平均濃度を
出力する平均濃度回路と、λ値化しようとしているディ
ジタル画素が平均濃度の領域の中央にくる様に各ディジ
タル画素を遅延させる遅延回路ど、前記平均濃度回路の
出力と前記遅延回路の出力を用いてディジタル画素をλ
値化するスレッショルド回路とを具備することを特徴と
1−だファクシミリ装置の画信号λ値化回路。
A document reading circuit that converts an analog image signal into N-bit digital pixels, a line memory circuit that stores several lines of digital pixels output from the document reading circuit, and an average of an arbitrary area for digital pixels. An average density circuit that outputs the density, and a delay circuit that delays each digital pixel so that the digital pixel to be converted into a λ value comes to the center of the average density area, the output of the average density circuit and the output of the delay circuit. digital pixel using λ
1. An image signal lambda value converting circuit for a facsimile machine, comprising: a threshold circuit for converting the image signal into a value.
JP58174783A 1983-09-21 1983-09-21 Picture signal binary-coding circuit of facsimile equipment Pending JPS6066577A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58174783A JPS6066577A (en) 1983-09-21 1983-09-21 Picture signal binary-coding circuit of facsimile equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58174783A JPS6066577A (en) 1983-09-21 1983-09-21 Picture signal binary-coding circuit of facsimile equipment

Publications (1)

Publication Number Publication Date
JPS6066577A true JPS6066577A (en) 1985-04-16

Family

ID=15984587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58174783A Pending JPS6066577A (en) 1983-09-21 1983-09-21 Picture signal binary-coding circuit of facsimile equipment

Country Status (1)

Country Link
JP (1) JPS6066577A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62107571A (en) * 1985-11-05 1987-05-18 Canon Inc Picture tone identifying device
JPS62107570A (en) * 1985-11-05 1987-05-18 Canon Inc Picture tone identifying device
JPS63164759A (en) * 1986-12-26 1988-07-08 Matsushita Graphic Commun Syst Inc Binarization processing method
JPH02196565A (en) * 1989-01-25 1990-08-03 Eastman Kodatsuku Japan Kk Picture binarizing system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723183A (en) * 1980-07-18 1982-02-06 Ricoh Co Ltd Picture processing method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723183A (en) * 1980-07-18 1982-02-06 Ricoh Co Ltd Picture processing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62107571A (en) * 1985-11-05 1987-05-18 Canon Inc Picture tone identifying device
JPS62107570A (en) * 1985-11-05 1987-05-18 Canon Inc Picture tone identifying device
JPS63164759A (en) * 1986-12-26 1988-07-08 Matsushita Graphic Commun Syst Inc Binarization processing method
JPH02196565A (en) * 1989-01-25 1990-08-03 Eastman Kodatsuku Japan Kk Picture binarizing system
JPH0576223B2 (en) * 1989-01-25 1993-10-22 Eastman Kodak Japan

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