JPS6066366A - Method for detecting pulse train - Google Patents

Abstract

PURPOSE:To prevent a pulse train from incorrect recognition and to improve the recognition percentage of data by correcting the pulse train reproduced from a tape or the like and having dispersion to the pulse train included in a recongnition allowable range at the detection of pulse train in a sampling period. CONSTITUTION:A pulse train reproduced from a tape is supplied to an input deciding means 1. The means 1 decides wherther the level of the input is logical ''1'' or logical ''0''. At the logical ''1'' level, a control signal DEH is supplied to the 1st timer means 2, an output means 3, the 2nd timer means 4, and the 3rd timer means 5. The operation of the means 1 is controlled by the 3rd timer means 5 and the means 1 operates during the operation of the 3rd timer, i.e. for a period T3 from timer start to timer end. Thus, the input pulse train is converted into a pulse train included in the recognition allowable range at a sampling period t0, so that the pulse train can be prevented from incorrect recognition.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a pulse train detection method for detecting a pulse train representing data such as time or index recorded on a tape in a tape recorder or the like.

(B) Prior art In recent years, answering machines, dictating machines, etc. record the date and time of recording, as well as an index of the contents, and read out and display the data during playback. Function has been realized.

The data recorded on the tape is as shown in Figure 1.
Start bit pulses S, ~S, and synchronous pit pulses Pl, P2 . P3... and synchronized Bisothohals P...
P2. A 4-bit data bit pulse D exists between P, . -D,,D,~D7. ..., and during playback, by detecting eight start bit pulses S, ~S6, it is recognized that the next pulse is a pulse containing data,
Read data between synchronization bit pulses Ps, Pg, Pg...

Conventionally, when detecting a pulse train, the period T of the pulse train is
A period t of about l/degree. Sampling is performed at 0 to detect the rising or falling edge of the pulse train signal. For example, if the pulse train shown in FIG. 2(a) arrives, the period t. When the rising edge of the synchronization bit P is detected by sampling, one cycle t occurs.

"9" is set in the timer means to be subtracted by the timer means, and 1'' is set in the flag.Here, FIG. 2(b) shows the timing of the operation of the timer means, and FIG.
C) is a diagram showing the contents of the flag. The timer means set to "9" indicates the sampling period t.

When "1" is subtracted for each time and the result is rOJ,
That is, after the period of 9t0 has elapsed, the contents of the flag ゛1
" is recognized as a pulse of the synchronization bit P1, the flag is reset, and the timer means is set to "9" again. Then, when the period 9to has elapsed, the content of the flag is set to "0" as data bit D. It is recognized as a pulse, and "9" is set in the timer means. Therefore, the timer means has a period t. However, if the rising edge of the pulse of data bit D is detected before rOJ is reached, the flag is set to 1'' and the timer is reset to 9. be done. Furthermore, 9
When t'o has elapsed, the contents of the flag +1, +1 are recognized as a pulse of data bit D1. Thereafter, the pulses of the pulse train are detected by the same operation.

However, when reading a pulse train from a tape, the cycle of the pulse train varies by approximately ±6% in the short term and ±3% in the long term due to variations in tape speed, etc., so it is difficult to obtain an accurate sampling period t. If the pulse train was sampled with , the pulse train could not be completely detected, resulting in a low recognition rate. For example, the center period T of the pulse train is 62.5ms
, the range of short-term variation is 58.75m5
≦T≦66.25 m5, and the range of long-term variation is 60.6 ms ='r=64.37 ms. On the other hand, as shown in FIG. 3, when pulses of '1' are continuous, the range that can be recognized is within the period where the rising edge of the next pulse is indicated by A, that is, 10to≦T<ist,
, for example, when the sampling period t0 is 6.1 ms, it is 6177154 T (109,8 total).

In addition, as shown in FIG. 4, when data of '0' is continuous, the range that can be recognized is the range where the rising edge of the subsequent synchronization bit pulse is indicated by B, and 5X9io≦5T
49x6t. Therefore, when to is 6.17715, the recognition tolerance range is 54.9ms≦T (65.88ms. Therefore, if "1" continues, the variation range exceeds the recognition tolerance range. .

(C) Purpose of the Invention The present invention has been made in view of the above points, and when a pulse n 1 u shorter than the center period arrives, this pulse is corrected to the length of the center period, and in the case of 11011 The present invention provides a pulse train detection method that corrects an input pulse train to be within the recognition permissible range by correcting it to near the lower limit of the recognition permissible range, thereby preventing erroneous recognition.

B) Structure of the Invention The present invention has a central period T. In a method for detecting a pulse train having a variation in a range of ±Δ, determining whether the pulse train is at a first level or a second level by an input determining means in an operating state, When at the first level, a first timer means is operated, and a time T is generated by the first timer means. outputs a pulse of a first level having a period, and when the pulse is at the second level, operates a second timer means, and generates a period T by the second timer means. The periodic force T is output by outputting a second level whose period is a shorter time t. −
The first level pulse of ΔT has a period T. The configuration is such that a pulse train is created in which the delay due to the correction is corrected to a period t of a second level, and the pulse train is sampled and detected using a sampling pulse of a predetermined period.

(E) Embodiment FIG. 5 is a block diagram showing an embodiment of the present invention. The pulse train reproduced from the tape is applied to the input determining means (1), and the input determining means (1), in the operating state, determines that the level of the input pulse train is the first level, logic II I
II or second level, logic "0"
When a level of 1'' is applied, the control signal DEH is sent to the first timer means (2), the output means (3), the second timer means (4), and , 3rd
On the other hand, when the level of °0'' is applied, the control signal DEL is applied to the second timer means (4).The operation of this input determination means (1) is controlled by the third timer means (5), and while the third timer means (5) is operating, that is, the time T from the timer start to the timer end,
Opening operation.

The first timer means (2) has a center period T. T1 is a timer that creates a time of approximately A of the central period.
It consists of a timer (6) and a T2 timer (7). That is, the central period T. is the sum of T1, the time T of the timer (6), and T2, the time T2 of the timer (7). T
, the timer (6) receives the control signal D from the input determining means (1).
The operation starts when EH is output, and the operation of the T2 timer (7) is started by the output signal output after T7 time. In addition, the output of T and the timer (6) is output by the output means (
3) and when the control signal DEH is applied, 1
It controls the output means (3) that outputs the level of ``1'' and changes the output ``1'' to 0.

That is, the T1 timer (6) determines the period during which a 1" pulse is output. The output of the T2 timer (7) is applied to the third timer means (5), and the input determination means ( T after the control signal DEH is output from 1).

After a period of time, in order to operate the input determination means (1) again,
The third timer means (5) is operated. The third timer means (5), during the timer operation, input determination means (5).
1) is activated, but when the control signal DEH is output, it is reset and the timer operation is stopped.

On the other hand, the second timer means (4) input determination means (1
) is in operation, it is controlled by the control signal DEL that is output when detecting the N OII of the pulse train, and when the control signal DEL is applied, the timer operation is started. IIO outputted by
This is to create the minimum period t of II. The output of the second timer means (4) is applied to the third timer means (5) to start the timer operation of the third timer means (5) in order to judge the pulse train after a period of time. . Also, during the operation of the second timer means (4), the input determination means (1
) detects the pulse train II II II and outputs the control signal DE.
When H is output, the second timer means (4) is set and stops the timer operation.

In the embodiment shown in FIG. 5, the center period T.

The operation when a pulse train with a longer period T is applied will be explained with reference to FIG. FIG. 6 (at is a waveform diagram of a pulse train, FIG. 6 is a timing diagram showing the operation period of the third timer means (5), that is, the operation period of the input determination means (1), FIG. 6 (C > indicates the timing of the operation of the T1 timer (6), FIG. 6(d) indicates the timing of the operation of the T2 timer (7), and FIG. 6 (el indicates the operation of the second timer means (4) Timing: FIG. 6(f) is a waveform diagram showing the output of the output means (3).

First, at the timing shown in Figure 6, the input determination means (1
), when the pulse train input becomes 1", the input determination means (1) outputs the control signal DEH. By outputting this control signal DEH, the output means (3) outputs "1". The T1 timer (6) starts the timer operation, and the second timer means (4) and the third timer means (5) are set and stop the timer operation. The operation of the determining means (1) also stops -0, and
When time T has elapsed, the output means (3) changes the output of 1" to "0" by the output of the timer (6), and
2 timer (7) starts timer operation. Figure 6 (
At the timing of Bl, when the T2 timer (7) counts up, the third timer (5)
starts the timer operation and puts the input determination means (1) into the operating state. At this time, since the period is T>To, the pulse train signal is lOl'', and the input determination means (1) outputs the control signal DEL.Thereby, the second timer means (4) The timer operation starts. As shown in Fig. 6 (
At cl, when the pulse train signal becomes 1'', the output means (3) outputs 1'' by the same operation as described above, and the second timer one means (4) and the third timer one means ( 5)
Meanwhile, the T1 timer (6) starts operating.

Then, in FIG. 6(D), when time T has elapsed, the third timer means (5) and the second timer means (4) start the timer operation in the same way. If the pulse train does not become 1" within the period in which the third timer means (5) measures time T3, that is, when the data indicated by the pulse train is "0", the input determination means (1) After T5 time has elapsed, it becomes inactive. On the other hand, the second timer means (4) continues the timer operation, and as shown in FIG. Depending on the output, the third
The timer operation of the timer means (5) is started, and the input determination means (1) is brought into operation. At this time, since the pulse train signal is "O'", the input determining means (1) outputs the control signal DEL, and the second timer means (4) is brought into operation again. During the operation of the input determining means (1), the pulse train signal is 1'' at the timing shown in FIG. 6 (F'1).
In this case, the same operations as in (3) and (0) in FIG. 6 described above are performed.

As shown in FIG. 6, the period T of the pulse train is the center period T
. If it is longer, the signal output from the output means (3) will be a signal whose rising edge is synchronized with the pulse train and whose period is equal. In other words, this is equivalent to outputting the applied pulse train as is.

On the other hand, FIG. 7 shows a case where the period T of the pulse train is shorter than the center period To, and FIGS. As shown in Figure 7 (a),
When pulses of 1" arrive successively 1. For example, in the case of start bit pulses Sl, S2, Ss..., first,
The input determination means (1j is kept in an operating state at all times.

Therefore, when the pulse S1 becomes '1', the input determination means (
A control signal DEH is output from 1), and in response to the control signal DBH, the output means (3) outputs 1'', and T.

The timer (6) starts operating. When T7 time elapses, the output means (3) becomes 1" due to the output of the timer (6).
The output of the T2 timer (7) is changed to 0'', and the T2 timer (7) starts its timer operation.Then, when 12 hours have passed since the operation of the timer (6), the output of the T2 timer (7) is changed to 0''. As a result, the third timer means (5) operates and the input determination means (1) becomes operational.Here, since the pulse train signal has already become 1'' due to the pulse S2, the input determination means (1) is the control signal D at the same time as the operation.
Output EH. Therefore, the third
The timer means (5) is immediately reset and stops operating. At the same time, the timer (6) starts its timer operation. Thereafter, by performing similar operations, the period T is output from the output means (3). A pulse train of is output. However, in this case, the period of the input pulse train and the output pulse train is T. Since there is a difference of -T, the output pulse train has a delay of 7 (T, -T) until eight start bit pulses are output.

FIG. 8 shows a start bit pulse S6, a synchronization bit pulse P, and a data bit pulse D. This is a timing diagram when outputting a start bit pulse, and the timings shown by (a) to (fl) are the same as those shown by (aS to (f)) in FIGS. 6 and 7. As mentioned above, the start bit pulse At the time when S is output, there is a delay of ? (To - T) between the input pulse train and the output pulse train.However, the delay between the start bit pulse S6 and the synchronization bit pulse P is There is always a blank for one cycle in between, and if the data represented by the four data bits D.-D is a BCD code, there is always one period of "0" data in it. Therefore, the delay must be corrected in the period of the blank and "0" data bit pulses.In other words, in FIG. From the time when the input determination means (1) determines 1'' and outputs 1'', T. When the period elapses, the third timer means (5) starts the timer operation by the output of the T2 timer (7). The control signal DEL is output from the input determination means (1) which is in the operating state, and the timer operation of the second timer means (7) is started.Then, the timer operation of the second timer means (7) is started.
) until the timer operation ends, the pulse train signal is 0'', so the second timer means (4
) continues the timer operation, and after a period of time, the third timer means (5) is operated again by the output of the second timer means (4), and the input determination means (1) is set to the operating state. do. At this time, since the synchronization bit pulse P1 has arrived in the pulse train, the input determining means (1) outputs the control signal DEH at the same time as the start of operation. The subsequent operations are as described above. Therefore, since the time t created by the second timer means (4) is set shorter than the period T of the pulse train, the delay between the rise of the synchronization bit pulse P and the output pulse is 8 (To- T)-('r-t), and the delay is reduced. Similarly, data bit pulse D
. Even when is "0", the delay is reduced because the time Tt is shortened.

Therefore, when detecting a pulse train with a center period of 62.5 ms at a sampling frequency of 6.1+rLs, the time T created by the first timer means (2). is set to 62.5 yns, and the time t created by the second timer means (4) is set to 55@s, which is the minimum value of 54.9 ms of the allowable range for detecting the NOI+ pulse. As shown in the figure, the period T of the pulse train is the center period T. More +3
%, an output with the same period as the pulse train is obtained, and as shown in FIGS. 7 and 8, the period T of the pulse train is the center period T. If it is -3% shorter than
The output is a 1" pulse with a period of 62.5 ms K"O" corrected to 55 m5. At this time, the maximum delay after the start bit pulse S8 is 8
(To T ) = 15.2 ms, but in the synchronization bit pulse P, 8 (To-T) (T
)=9.6ms. Additionally, a data bit pulse D. If is 0'', the delay is 9(T, -T)
-2(T-t)=5.9 ms, which is further shortened.

Therefore, the variation range of the pulse train output from the output means (3) is 62.5m54T in the case of a '1'' pulse.
If ≦64.37m5.0”, 55 @s≦T≦6
The result is 4.37@s, which is within the allowable range when the sampling period is 6.1 ms.

Further, the operation of the embodiment shown in FIG. 5 can also be realized by a microcomputer.

In this case, detecting that the pulse train signal has become 1'' is done by applying the pulse train to the interrupt input terminal of the microcomputer and checking whether or not there is an interrupt request.
Processing corresponding to 1'' of the pulse train is performed by interrupt processing.

FIG. 9(at(bl) is a flow diagram showing the operation of the program of the microcomputer. FIG. 9(a) is a flow diagram showing the operation of the main program. (In T1, when the microcomputer starts operating, it first initializes the RAM (random access memory), etc., and also resets INTMSK, which disables interrupts, to enable interrupts. Next, T1 timer, T2 timer,
Detects the end of one hour of the T3 timer and t timer. The TI timer and the T2 timer are the first timer means (2) shown in FIG. 5, the T timer is the third timer means (5), and the t timer is the second timer means (4). ). When the end of the timer operation of the T and timer is detected, the output port of the microcomputer that outputs the pulse train is set to "O", and the timer operation of the T2 timer is started. When the end of the timer operation is detected, the timer operation of the T3 timer and the t timer is started, and then the INTMSK
Reset to enable interrupts. On the other hand, T3
INTMS when the end of the timer operation is detected.
Set K to disable interrupts. In this manner, the main program constantly monitors the end of each timer's operation, detects the end, and performs the corresponding operation. Also, the 9th
During the operation shown in Figure (a), interrupts are permitted only after the initial setting and after the end of the T,-timer, or during the T3 period from the end of the t timer until the end of the T, timer is detected. It is. ’1 to the interrupt input pin within this period.
” signal is applied, an interrupt occurs and the state shown in Figure 9 (
Interrupt processing indicated by bl is executed.

Figure 9 (In the interrupt processing in bl, T, timer and t timer are reset and the timer operation is stopped, while the timer operation of T and timer is started and the output port for outputting the pulse train is set to 1''. , Furthermore, INTMSK is set to 12 to disable interrupts.

In this way, in a microcomputer, a pulse train is applied to the interrupt input terminal. By executing the program that performs the operation shown in FIG. 9(a) (bl), it is possible to perform exactly the same operation as in the embodiment shown in FIG. The pulse train is converted into a pulse train within an acceptable range.

(f) Effects of the Invention As described above, according to the present invention, a pulse train having variations reproduced from a tape or the like is sampled at a sampling period t. By correcting the pulse train so that it falls within the permissible recognition range when detected by the system, erroneous recognition of the pulse train can be prevented, and the recognition rate of data recorded on answering machines, dictation tape recorders, etc. can be improved. , it has the advantage of improving commercial value and reliability.

[Brief explanation of drawings]

Figure 1 is a waveform diagram showing a pulse train, Figure 2 (a), (b) (
Figures 3 and 4 are timing diagrams showing a method for detecting a cl haha pulse train. FIG. 5 is a block diagram showing an embodiment of the present invention,
Fig. 6(a)(bl(cl(dl(el(f)), Fig. 7(a)(b)(cl(d)(el) and Fig. 8(a)
l(bl(cMd)(el(fl) is a timing diagram showing the operation of the embodiment shown in FIG. 5, FIG. 9(at (b)
1 is a flow diagram showing the operation when implementing the present invention in a microcomputer. (1)...Input determination means, (2)...First timer means, (3)...Output means, (4)...Second
a timer means, (5)...a third timer means,
(6)...T, timer, (7)...T, timer. Figure 1 Figure 3 Figure 11 fil Figure 5 Figure G

Claims (1)

[Claims] 1. Central period T. In a method for detecting a pulse train having a variation in a range of ± to T, determining whether the pulse train is at a first level or a second level by an input determining means in an operating state, When the level is at the first level, a first timer means is operated to output a first level pulse having a period of time l1lo created by the first timer means, and when the timer is at the second level. , by operating the second timer means and outputting a second level whose period is a time t shorter than the period T0 created by the second timer means, To-△T is determined. The first level pulse has a period T. A pulse train detection method includes creating a pulse train in which the delay due to the correction is corrected to a period t of a second level, and sampling and detecting the pulse train with a sampling pulse having a predetermined period.