JPS6063659A - Automatic fault recovery system - Google Patents

Abstract

PURPOSE:To prevent a master processor from disabling due to a fault occurring to a slave processor by releasing the master processor from a wait state without fail when the master processor is kept in the wait state continuously for longer than a specified time. CONSTITUTION:The master processor 1 is provided with a monitor timer mechanism 11, and salve processors 2 and 3 are provided with NORDY control circuits 22 and 23. The monitor timer mechanism 11 turns on automatically a monitor signal line 12 a preset time later. Once the monitor signal line 12 is turned on, the NORDY control circuits 22 and 32 turns off an NORDY signal line forcibly to release the master processor from a wait state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides a memory sharing type multiprocessor system in which a parent processor becomes inoperable due to a failure of one child processor while occupying the memory exclusively.
Automatic failure recovery system that prevents failure of the entire system as a result [Background of the Invention] In a multiprocessor system, it is necessary to communicate various information between each processor, but this communication information is stored in a shared memory. The shared memory type, which stores information in
Used in terminal control devices, etc.

FIG. 1 shows an outline of the configuration of a terminal control device using a memory-sharing type multi-processor support system 11.

A floppy disk 4 is used to control the entire terminal control device (for example, control the panel 6 such as keys and lamps of the device) and to communicate between the child processors 2 and 3.
The control program is loaded into the own memory 5 and the shared memory in the child processors 2 and 3 from there. Child processor 2゜3 is the line (first place 7 for pair, terminal 8, etc.)
Sends/receives corresponding data and controls procedures.

FIG. 2 is a detailed configuration diagram for explaining the operation of FIG. 1.

1, 2, and 3 are the parent processor and child processor shown in FIG. 1, respectively. 23.33 is each child processor 2
, 3 is a shared memory placed in correspondence with . Also, 14.1
5 and 16 are address lines used when the parent processor l accesses the child processors 2 and 3, respectively;
Data line and control line are shown, 24.25
．． 26 (34, 35, 36) indicate an address line, a data line, and a control line, respectively, when the child processor 2 (3) accesses the shared memory 23 (33).

21.3+ is an access identification structure, in which the address information sent via the address line 14 from the parent processor 1 or the address lines 24.34 from the child processors 2 and 3 is accessed by the parent processor 1. If the access is from the parent processor 1, it is further determined whether the access is to its own shared memory or not. At this time, the shared memory 23.33 of the child processor 2.3 is shared by the parent processor 1.
Each of them occupies an area with a different address within the memory space of , and accesses to the plurality of shared memories 23 and 33 do not occur in response to an access to a specific address from the parent processor l.

Reference numeral 13 indicates a N0RDY signal to the parent processor 1 indicating that the access identifier groove 21.31 has accepted an access from the parent processor 1. Also, 27 (37), 2
8 (38) are the access identification mechanism 21 (31
) This is an address line and a control line when the shared memory 23 (33) is accessed from the parent processor 1 or the child processors 2 and 3 based on the identification result by the parent processor 1 or the child processors 2 and 3.

In this method, the shared memory 23 corresponding to the child processor 2.3
．． 33 stores a program for operating the child processors 2 and 3.
is performing line-compatible processing. Therefore, in accessing the shared memory 23, 33, accesses from the child processors 2 and 3 are given priority over accesses from the parent processor 1. Therefore, for access from the parent processor 1, the access identification mechanism 21.31 corresponding to the target shared memory 23.33 turns on the N0RDY signal.
The parent processor 1 is placed in a waiting state temporarily, and is controlled to be released after access is completed. For this reason, N
If a failure occurs in the child processors 2 and 3 that turned on the 0RDY signal, and the N0RDY signal is fixed in the ON state,
The parent processor 1 remains in a waiting state and becomes inoperable, making it impossible to control the entire device, resulting in a serious problem.

[Purpose of the invention]

An object of the present invention is to solve the drawbacks of the prior art as described in 1. In a memory-sharing multiprocessor system consisting of a parent processor and a plurality of child processors, the parent processor It is an object of the present invention to provide an automatic failure recovery method that can automatically avoid becoming inoperable and causing a failure of the entire system.

[Summary of the invention]

- In order to achieve the object set forth in item 1, the present invention provides at least one child processor such as a parent processor, a memory provided between the two processors, and a memory provided between the child processor and the parent processor, and a first circuit that outputs a control signal to put the parent processor in a waiting state when an access request is received, and a time-over signal is output when the waiting state of the parent processor continues for a certain period of time or more. -1 by providing a timer for controlling the timer, and a second circuit for switching the state of the control signal in response to the time-over signal to release the I part processor from the waiting state and put it into an operational state.
- If a failure occurs in the child processor, the parent processor and other child processors are automatically prevented from being inoperable at the same time.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on the drawings. FIG. 3 is a diagram showing an embodiment of the present invention. The difference from the conventional example shown in FIG. 2 is that a monitoring timer mechanism 1] is provided in the parent processor 1, and N*RDY control circuits 22 and 32 are provided in the child processors 2 and 3. Accordingly, the supervisory signal line 12 is connected to the supervisory timer mechanism 11 and each N0RDY.
It is provided between the control circuits 22 and 32. The monitoring timer mechanism 11 is configured to automatically turn on the monitoring signal line 12 after a preset time. When the monitoring signal line 12 is turned on, the N○RDY control circuit 22
．． 32 forcibly turns off the N0RDY signal line 13 and releases the parent processor 1 from the waiting state.

During normal operation, the program of the parent processor 1 periodically accesses the monitoring timer mechanism 11 at a cycle shorter than the monitoring time (every GP state of the state counter, which will be described later), repeatedly resets the monitoring time, and monitors the timer mechanism 11. Signal line 12 is O
It is controlled so that the N state does not occur.

On the other hand, if a failure occurs in the child processors 2 and 3 and the parent processor 1 remains in the waiting state, the above-mentioned stage 1
~ Since the GP state no longer appears in the counter, the program of the parent processor 1 cannot reset the monitoring time for the monitoring timer mechanism (1), and the monitoring signal line 12 turns ON after a preset time. When the monitoring signal line 12 is turned on, the N0RDY control circuit 22.
32 forces the NORD'Y signal line 13 into the FF state and releases the parent processor 1 from the waiting state.

Next, memory access control will be explained in detail with reference to FIGS. 4 and 5.

FIG. 4 shows the memory access control mechanism in the child processor 2, which is surrounded by a dashed line in FIG. Each child processor has its own memory access control mechanism.

Since the shared memory 22 is accessed by both the parent processor 1 and the child processor 2, the child processor 2 performs refresh (RF) → child processor (r
-p ) → Parent processor (GP) → Refresh (RF
)... State counter 2 that repeats each state in order
It has a. An access address to the shared memory 22 is selected using state signals GPS, LPS, and RFS obtained from the state counter 2a. Here, the state signals GPS, LPS, and RFS correspond to the states GP, LP, and RF of the state counter 2a, respectively. In addition, in order to distinguish between writing and reading, the data line 15
．． 25 also each have a bidirectional gate 29, and the stay 1
~ Signals (GPS, LPS) and control signals (GWR
, GRD, LWR2LRD) to select the direction. Here, GWRlGRD, LWR, and LRD indicate a write signal from the parent processor, a read signal to the parent processor, a write signal from the child processor, and a read signal to the child processor, respectively.

Note that the comparator 2]a-GP access 21b, the memory access 2]c, the address selector 21d, the refresh counter 21a, and the address/refresh selector 21f are provided in the address identification mechanism 21.

The refresh counter 21e has a shared memory 22 composed of a dynamic RAM."1. Therefore, it is provided to cause the shared memory 22 to perform a refresh operation when the state counter 2a is in the RF state 1.

Next, memory access control operation will be explained.

First, a program for the child processor 2 is set using the program switch 2b. Address line 14, connection 1~
When there is an access request from the parent processor 1 to the shared memory 22 via the port line 16, the address is
The access identifier also uses comparator 2]a in l521 to determine whether the address matches the address in the shared memory 22 set in advance, and if they match, the GP access 21b accepts the access and sends a controller to that effect. The N ORD 'Y control circuit 22 is notified through the 1 Herol line 28. The NOR,DY control circuit 22 that received the notification,
Immediately sends the N0RDY signal line 1 to the parent processor 1 regardless of the state 1~ of the state counter 2a.
3 outputs the NORD Y signal and waits until the GP state is reached. On the other hand, the address has been learned by the shared memory 22 during the above period via the address selector 2]d, the address, and the response/refresh selector 21f,
When the counter 2a to the stage 1 reaches the GP state, a memory access signal is outputted from the memory access 21c to the shared memory 22 via the roll line 28 to the controller 1, and the access is executed. Then, when the access is completed, the output of the N0RDY borrowed sign is stopped.

Access requests from child processor 2 are controlled as follows. If an access request is received from the child processor 2 when the count state 1-28 is a state 1 other than the LP state, the state is rewritten to the LP state 1- and the access is immediately executed. This access is executed when an address signal is input to the address selector 21d via the address line 24, and the memory area corresponding to the child processor 2 in the shared memory 22 is specified by the address selector 21d and the address/refresh selector 21f. This is accomplished by a memory access signal from memory access 21c.

Note that the operation cycle of the child processor always includes three stages hGP, LP, and RF, so
Only child processors do not access it continuously for a long time.

FIG. 5 shows changes in the normal state and the state of the signals regarding the stay 1 to the counter and the N0RDY control circuit 22.32.

In the normal state, as shown in FIG. 5(a), when the access from the parent processor 1 is accepted (a), the
r) The Y signal is turned ON, and this N0RDY borrowing is automatically turned OFF when the parent processor (GP) stay I- ends and the access ends (b). Therefore, N0
Tarock signal to forcefully turn off the RDY borrowed code (
CLK signal) and the interrupt TNT signal remain in the OFF state.

However, as shown in FIG. 5(b), some kind of failure occurs in child processors 2 and 3 at point (c), and the state counter 2a becomes undefined, and at point (b), the parent processor 1 requests access. If there is, the N0RDY borrowed symbol will remain in the ON state.

Parent processor 1 becomes inoperable. . Therefore, in order to automatically recover from this state, when the parent processor 1 is inoperable, the C[, K signals are issued via the supervisory signal line I2 after the time set in the timer mechanism 11 has elapsed. The NOR and DY signals are forcibly turned off by the TNT signal and the TNT signal. Here, by using the CLK signal as it is as an INT signal for interrupt, it is possible to notify the parent processor 1 that a failure has occurred.

〔Effect of the invention〕

As explained below, according to the shared memory multiprocessor system using the automatic failure recovery method of the present invention,
Since the parent processor is always released from the access waiting state after a certain period of time, it is possible to automatically prevent the parent processor from becoming inoperable and the entire system becoming inoperable due to the influence of a failure occurring in the child processor.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of the configuration of a terminal control device using a shared memory multiprocessor system to which the present invention is applied;
Fig. 2 is a block diagram of the memory shared multiprocessor system shown in Fig. 1, and Fig. 3 is a failure automatic @ according to an embodiment of the present invention.
Figure 4 is a diagram for explaining memory access control when the automatic failure recovery device according to the present invention is applied. Figure 5 shows the state counter and N0RDY control in Figure 4. FIG. 3 is a diagram showing the relationship between each signal of the circuit. 1: Parent processor, 2, 3: Child processor, 1]: ■1
Visual timer mechanism, 12: Monitoring signal line, 13: N ORD
Y signal line, 1/I, 24, 27, 34, 37: address line, 15, 25, 35: data line, +6.26.28,
36.38: Control line, 2], 3]: Access identification mechanism, 22, 32: N0Rr) Y control circuit, 23.3
3: Shared memory. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] A parent processor, at least one child processor, and nine memories provided between the two processors; when the parent processor also requests access while the child processor is accessing the memory, a timer that outputs a time-over signal when the wait state of the parent processor continues for more than a certain period of time; and a second circuit which responsively switches the state of the control signal to release the parent processor from the waiting state and into an operational state.