JPS6063636A - Data retrieval processor - Google Patents

Abstract

PURPOSE:To shorten a processing time by performing logical arithmetic directly through hardware without any time delay behind the field-to-field comparison result of comparison data corresponding to respective fields and interfield comparison result for a blocked record. CONSTITUTION:Field data F1-F3 are inputted from a storage device 1 to an arithmetic circuit 40 and compared with comparison data 41 on a condition 39 to set ''1'' in L1-L3 of a latch 16 when they coincide with each other or ''0'' when not. Then, arithmetic circuits 33-36 perform arithmetic together with the values of logical arithmetic latches 17, 19, and 21 which are installed previously to retrieve a record. Further, field data F1-F3 are set in registers 46 and 47. Then, arithmetic circuits 44 and 45 compares respective fields as to whether they meet conditions 42 and 43 or not. Then, arithmetic circuits 33-36 perform arithmetic together with the values of logical arithmetic latches 27, 29, and 31 to retrieve a record.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a data search processing device. The present invention relates to a data search processing device for searching for records.

[From U] 1! Figure 1 shows a conventional method of comparing records transferred field by field from an external storage device such as a magnetic tape or magnetic disk to a data processing device and searching for a record by performing a logical operation on the results. As shown in FIG.
3, the data is stored in the buffer area of the main memory in the data processing equipment building, fetched code by code into the main memory area referenced by the program, compared by field by program, and the results are processed by logical operations in the program. A method is used. However, in the method shown in FIG. 1, the search speed is affected by the instruction execution time of the processing device that processes the program.

In order to increase the search speed, a high-speed processing device is required. This high-speed processing device is generally expensive and has poor cost performance.

Therefore, in order to speed up the search as much as possible, a method has been proposed in which the storage control device 2 is provided with a data search function.

This method will be explained with reference to FIG.

First field data F□ to F4 from storage device 1
When the data is transferred to the control device 2, the control device 2 compares each field with data 8 set in advance according to an arbitrary condition 9, and sets the results of this comparison in the latches 10-13. That is, if Fl>vl, the latch 10 K
1F2-If F2, the latch IIK is set to "1" in sequence. Before the next record is transferred to this rack data, a micro program performs logical operations to check whether or not those records satisfy the search conditions. Perform the desired processing on records that satisfy the conditions.

However, with this method, since the microphone p program is processed within the gap G between records, K
, the transfer of the next record to the storage device] and the controller 2 is stopped, or it is necessary to make the HCAP G passage time longer than the processing time of the MICRO PROGRAM 5. Therefore, when processing multiple records in succession,
Performance decreases in proportion to the processing time of the microprogram.

Furthermore, there are also drawbacks such as the inability to block code.

Therefore, even for blocked records, field-based comparison operations and arbitrary logical operations using the results of these comparisons are executed without time delay, so K does not use microprograms. Another possible method is to perform it directly by hardware.

However, in this method, unnecessary field data is also stored in the buffer memory during the search and acquisition of print records, which reduces the efficiency of buffer memory usage and also causes the data to be transferred from the control device 2 to the channel device 3. There is also a waste of transfer time. That is, even if only F2 and F3 are necessary data when storing records matching the search conditions in the buffer memory, other fields F, , F4 in the same record are also stored.

Therefore, the inventor of the present invention first performed an arbitrary logical operation between the comparison results using direct hardware on the comparison results of the record from the storage device 1 with the comparison data corresponding to each field, and at the same time We proposed a processing device that acquires only the fields that need to be acquired from among the fields in the buffer memory, thereby making effective use of the buffer memory and reducing data transfer time.

However, this processing device is insufficient because it only performs comparison operations between each field and certain data, and cannot perform comparison operations between fields. For example, if expense fields such as budget, travel expenses, and outsourcing expenses are stored in records for consecutive years, recently δ
When determining the year with the lowest outsourcing costs, K requires comparison between fields.

[Purpose of the invention]

In order to satisfy such a request, it is an object of the present invention to provide a system that involves a time delay in comparing the results of a blocked record with comparison data corresponding to each field and the results of comparisons between fields. To provide a data retrieval processing device which can perform arbitrary logical operations on comparison results directly by hardware and acquire only necessary fields into a buffer memory during record retrieval.

In order to achieve the above object, the data search processing device of the present invention sets arbitrary comparison conditions and comparison data corresponding to multiple fields of record data sequentially transferred from a storage device, and performs the comparison. a circuit that latches a matching output that satisfies a condition in a field-compatible manner; a latch circuit M□ that is arbitrarily set and reset in correspondence with the latch circuit; and a circuit that performs a logical operation between both latch circuits. In the data search processing bag @, which has information such as attributes related to each field and a counter synchronized with the byte comparison of each field, a comparison condition can be set between any fields, and a match output that satisfies the comparison condition. A circuit Ue that latches, a latch circuit M't:r that is arbitrarily set and reset corresponding to the latch circuit, the launch circuit M/, and the latch circuit M are arbitrarily set. From K, perform the following logical operation on the field-corresponding comparison condition results and the field-to-field comparison condition results, perform record search processing from the above operation result XK, and store only the necessary fields of the search matching record in the buffer memory. It is characterized by having a control means for storing the information.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a logic sequence diagram of a search condition matching circuit installed in a data search process, showing an embodiment of the present invention.

In FIG. 3, field data F is stored from storage device 1.
1 to F3 are input to the arithmetic circuit 40 and compared with the comparison data 41 under condition 39. If the condition is met, '1' is set in Ll, ~L, of the comparison result latch 16, and if not matched, "Set O1'. Then, the records are searched by performing calculations in the logical calculation circuits 33 to 36 together with the values of the logical calculation latches 17, 19 and 21 set in advance.

The above functions are the same as the conventional search method.

In FIG. 3, field data F, ~F3 from the storage device f1 are set in registers 46.47, and the fields are compared in an arithmetic circuit 44.45 to see if they match conditions 42.43. If they match, the comparison is made. Result latch 2
1f1 to L'4 of No. 6 are set to 1", and if they do not match, set to 0". Then, the records are searched by performing calculations in the logical calculation circuits 33 to 36 together with the preset values of the logical calculation latches 27.about.29.31.

The above functions are newly provided by the present invention.

In Figure 3, the general trap and latch are Lj ”1jI4
．． Each of the circuits, represented by u, is composed of a circuit that performs the following calculations.

X1j-LjV Mg' ” Mountain (1) x/j-Bird M
Kj...V
, lL'2...L'm, any plurality of L□+L
'3- is selected and logical product is performed. This represents selecting an arbitrary number from the comparison result latches 16.26. In other words, (1), (1
Substituting the expression j yields K as follows.

Xl-(L□M1.)△(L2VM□2)△・・・・・・
・・△(LnVMl)△(L'I VM'l 1)△
(L/2M7□)△・・・・△(Side V floor.)・・・・
(3) Assuming that Xl represents the output of the AND circuit 33, when an arbitrary number L1 + L2 + T-r'1 is selected, Xl is expressed by the following equation.

Xl-(I,, △L2△L11) ・・・・・・(4)X
To set l, Mll of logic operation latch 17.27,
Set M1□9M'1□ to "1", M13.M
;2. M'13.Mt4 is set to "O", and each value of the comparison result latch 16.26 and the corresponding logic operation lunch 17.270 invert output are output to the OR circuit 18.
28.

+ 謬9 ＋
, 7 blocks) △ (L 2 blocks) △ (L, 7 blocks) △ (L'V blocks) △
to (L'275) (L', VO) △ (L'O) - (L
,VO)△(L2V's△(LVI)△(L110)△(
L'21)△(L'1)△(L'41)-L1△L2△
L'1 (6) Further, any logical operation formula can be created by performing a logical sum operation using each term X□ of the logical product according to the following equation.

X - X1 . For example, consider a case where the logical product term X3 (representing the output of the logical product circuit 35) is deleted and the following calculation is performed.

x −x, X2...■! In this case, each term M3□ of the logic operation latches 21 and 31
, MB□, X3. , M'3□2M'3□+ M
'33. It is sufficient to set all of M- to "1".

That is, X3-L, △L2△L3△L11△LI2△
L/, △L'4...(8), which is X,,
This is a sufficient condition for X2 to hold, and no matter what conditions are chosen for X□ and X2, X3 will never hold without Xl*X2. Also, X3
When the following holds true, k is sure to hold Xl and X2 hold true.

In this way, any logical sum term Xd can be deleted.

Next, consider the case of executing the formula below.

X-(L1△L3)■(L1△L2△L-△Lt)・・
...(9) In this case, the logic operation latch 17.27
To all M, 1+ M, 2* M,, 1M'11+ M
', 2+ M'13+ M'14 is "1", "0".

If "l11.l"o", "o", "Qll, IIQ", Xl of the AND circuit 33 indicates L1△L3,
Logic operation latch 19゜20 M21 r X22
+ X23 + M'2I+ M'221M'23 r
M'24 is "l", "1" U Qll, 1"1",
"Oo", "1", "When turned ON, X2 of the AND circuit 34 indicates L1ΔL2ΔL11ΔL/3, and furthermore, each of the logical operation latches 21.31 M3□2M,

X33r M'3. t M'3□, M'13. M
’u as 1”, “1”, “1”, “1”.

If “1”, “1”, “1” is set, the X of the AND circuit 35
3 is the logic operation latch 21°3 of the OR circuit 22.32
All inputs from 1 become “0”, and the comparison result latch 1
6. All values in 26 must be “1”G; lr “1”
do not become. As a result, the operation result latch 37 which latches the output of the OR circuit 36 & the AND circuits 33, 34
．． It turns out that the force which is the logical sum of 35) is ultimately equal to the above equation (9).

Here, the phrase indicates the latch value of one comparison condition for each field, but a circuit for setting a second comparison condition for the same field is added, and this latch value is set to Lm.
+11 Lm+2..., L2! Il, and logical operation latch Mij is 1""L 2+ "・-211t, j
By setting = 1.2°...U and combining it with LS, more complex search conditions can be set.

Next, in order to delete unnecessary fields from the record, that is, to store only the necessary fields in the buffer memory, and to compare fields, the field data register 46.4-7 of the record is set. I will explain how to do this.

FIG. 6 is a block diagram of the main part of FIG. 4.

As shown in the diagram, the control device 2 includes a comparison data unit 85, a logic operation circuit 83, and comparison operation circuits 4Q, 4.
4, 45, inter-field comparison register unit 8
0, a latch circuit 82, a control unit 84 (the above blocks are shown in X311), a buffer memory 88, a buffer unit 72, etc. FIG. 5 shows the field information holding register 87 in the buffer unit 72, a part of the control a-/l/ unit 84, and the inter-field comparison register unit 80 in FIG. I'll do it.

First, a method for storing necessary fields in buffer memory 88 will be described.

Information regarding one field is transmitted from the buffer unit 72 holding information regarding the fields of the record as a trigger signal Fl, C-0 indicating that the processing of the field immediately before this field has been completed, as shown in FIG. It is set in the field information holding register 87 shown in FIG.

The field information holding register 87 has a function as a field length counter, and stores information SLF indicating that this field is a necessary field.
D by counting the address of the buffer memory 88 based on the counter value FL indicating the length of this field.
Upload and store data. The real KK counts down the field count value FLC in synchronization with the four clocks, and keeps the buffer until this value FLC reaches "011."
Field data is stored in memory 88.

Thus one each required field is stored in the buffer memory 88.
The search conditions for one record are completed, and the buffer memory address is changed based on the result. In other words, when k:'-)' satisfies the search condition, the current buffer memory address is sent to another register (not shown) as a record match signal trigger.
In the case of a record mismatch signal, the value of the address backup register is transferred to the buffer memory address register (
(not shown) as the buffer memory address.

After the necessary fields of the record are stored in the buffer memory 88 in this way, only the matching fields are retained.

Next, operations associated with comparison between fields will be explained.

Field information holding register (field length counter)
Based on the restrift field 98 from 87,
In the control unit 84, the field decoder 1105K identifies the field used for comparison between the fields, and the first field 108 and the second field are identified.
Fill field 118. Based on the presence of the first field signal 108, the registers (rest lift registers) 46 to 46', 4-7 to 477 that store the current field
The field data is stored through the gate 109 and the AND gate 112. Further, based on the second field signal 118, the field selector 1 selects the second field number to be compared with the first field.
It will be done in 06. Then, the field selector 106 is
When the corresponding second field is transferred from the memory device fi 21, a trigger signal T is provided for inputting data from each register 46', 47 to each corresponding comparator 44-45. This results in registers 46.46', 4
A comparison is made between the data in 7.47' and the transferred data.

Hereinafter, a specific example of the actual market will be explained.

Now, each record is Fl (unit number), F2 (research number), F3 (current term child 3J), F4 (current term travel expenses), F,
(Current term outsourcing expenses), F, (previous term budget), F7 (previous term travel expenses)
, F, (previous term outsourcing expenses), consisting of eight fields F□ to F8, execute the following inquiry.

"The unit ja is 305, the research number is 570 or more, the budget for this term is greater than the budget for the previous term, and the outsourcing cost for this term is 50)
Please show me the research number and current budget for which the travel expenses for this term are less than yen or the travel expenses for this term are greater than the travel expenses for the previous term.''

This alignment can be expressed by the following logical formula.

(F, -305)△(F2〉570)△(F,>F6)
△(F, <500 minutes)■(F□-305)△(F2≧
570) Δ(F4≧F7) ...00) Before starting the search, primary initialization is performed by a microprogram or other means.

That is, the comparison condition is stored in the comparison condition register 39 in the control device 2, the JtM data is stored in the comparison data buffer 41,
Comparison conditions are stored in the restriction comparison condition registers 42 and 43 that perform comparison operations between fields, and the field length buffer 786 stores the field length, ratio vi limit yield flag, selected field flag, and end field flag.
Field attributes such as flags, restriction register designations, and the like are set in the logic operation circuit 83, as well as logic operation latches and the like corresponding to the above-mentioned logical expression GO). As shown in FIG. 4, seven lags 91 to 95 are stored in the field length buffer 86. In addition,
'7 in the A restriction register designation tag 94 and the second restriction register designation tag 95
The lag "l" indicates the first part in the restriction, and the 7 lag "1/n" indicates the seventh canto part. Generally, this tag field contains the flag ``l''
is one, and there can be a plurality of flags "1". Further, in the logic operation circuit 83, the logic operation latch shown in FIG. 3 is set as follows.

After the above initial settings, data transfer from the storage device 1 is started. At this time, in the field length buffer 7 unit 721C, information regarding the field F1 is set from the field length buffer 86 to the field length counter 87.

Information regarding field F1, field length 96, comparison field 7 lag 91, selection field flag 9
2, the final field flag 93, the second restriximin designation tag/7 lag 94, and the second restriximin designation tag/flag 95 are connected to lines 96, 101, 100, .
l, 1.97 to the Huntroll unit 8%. When data transfer is started from the storage device 1, the field length counter 87 detects the clock CL of that transfer.
It is counted down in synchronization with KK.

On the other hand, the data read from the storage device I is transferred via the line 71 to the comparator circuits 40, 44, 45 and the restriction registers 46, 47, as well as to the buffer.
It is also sent to memory 88 via line 70.

[Field) 1 Processing] From the content of the inquiry, the selection fields are F2 (research number) and F, (current budget), and field F□ is a comparison field. Therefore, control unit 84 sets compare field flag 91 on talol.
In response to "1", the data buffer unit 8δ is activated via f177. The buffer unit 85 inputs the first comparison data v1 and the comparison condition C□ to the comparison circuit 40.

In addition, all other information regarding this field F□ is "0" as is clear from the field length no. column of the buffer unit 65, so O [Processing of field F2] After the processing of field F□ is completed, field length information regarding field F2 is set in the register 87.

Since the 74-field F2 is a comparison field and a selection field, both the comparison field flag 91 and the selection field flag 92 are "1".
The subsequent processing operations are the same as those of the conventional method, and will therefore be omitted.

[Processing of Field F3] After completing the processing of Field F2, the field length information of Field F3 is set in the register 67. Since this field F is both a selection field and a restriction register specification field, it is treated as a 0 selection field where the selection field flag 92 and the second restriction register tag 7 lag 94 are 1''. Since the processing is the same as the conventional method, the explanation will be omitted.Here, the processing for restriction specification will be explained.

A part of the data set in the field length counter 87 (part related to restriction) is sent to the restriction field decoder 105 in the control unit 84 via a line 98 shown in FIG. Sent. Since field F is involved in restriction and is the first part thereof, it is input to AND gate 103 via M2O3, and its output 109 is input to counter 104 and AND gate 112.

The counter 104 is 0 in the initial state, and is counted and updated by the input from the AND gate 103.

The output from this counter 104 is transmitted via line 110.
This field F is input to the register decoder 23.
3 is to be stored in the restriction first field register 46 r 46', 47 +
4τ is determined. Now, if the decoding result of the decoder 23 is register number 1, then the decoder 23
The output 111 is input to the restriction first field register group 46 as a trigger. Therefore, the field (aFD) of this field F is
Stored in restriction first field register 46 via line 71.

Storing to this register 46 is performed by counting down the field length data of field F in synchronization with clock CLK.

After the above settings, when this field F and the second part field for performing restriction appear, the data from this register 46 and the data in the restriction comparison condition register 42 are input to the comparison circuit 44. Ru. The comparison result is comparison result lunch 26:L'I
K is set.

[Processing of Field F4] After completing the processing of Field F3, the field length information flashed in Field F4 is set in the register 87. This field F4i;l: is a restriction register specification field, so the second restriction register
Register tag 7 lag 95 is "1". The subsequent processing is the same as the processing for field F3, so a description thereof will be omitted. However, field F4 field
The data is stored in the restriction register 47, and when the second part field of this field appears, the data in the restriction comparison condition register 43 is input to the comparator circuit 45. The comparison result is set to L' and K of the comparison result latch 26.

[Processing of Field F6] After completing the processing of Field F4, field length information regarding field Fs is set in the register 87. Since this field F is a comparison field, the comparison field flag 91 is "1". This process is the same as that for field F8, so the explanation will be omitted.

[Processing of Field F6] After completing the processing of Field F5, the field length information flashed in Field F6 is set in the register 87.

Since this field F64; t, restriction register tag 7 lag 94 is "1./n," it is the second part for the data of restriction register number 1. Same as field F3.F4. Part of the data in the field length counter 87 is stored in the fifth field length counter 87.
Control unit 84 via line 98 indicating 1 mK
The signal is sent to the restriction field decoder 105 in the Field F6 is involved in restriction (F3>F6) and is its second part, so in order to determine the first part of this field via line 107, the field selector 106 is
The output of the field decoder 105 is given below. The output of this selector 106 specifies a part of the restriction register group 46', and the output of this selector 106 is used as a trigger to compare the data in the register 46 and the comparison condition of the restriction comparison condition register 42 with a line. The field data FD is input to the comparison circuit 44 together with the field data FD sent via 71. In this case, the data in the restriction register 46 and the restriction comparison condition register 42 are input to the comparison circuit 44 in synchronization with the transfer of field F6. Then, this comparison result is set to L/ of the comparison result latch 26.

[Processing of Field F7] After completing the processing of Field F6, field length information regarding Field F7 is set in the register 87. This field F7 is the restriction register.
Since the tag flag 95 is "II", this is the second part for the data of restriction register number 2.The subsequent processing is the same as that for field F6, so the explanation will be omitted.

[Processing of field F8] After completing the processing of field F7, field F.

The field information regarding is set in the register 87.
It will be done. Since the jlk feed flag 93 of this field F8 is "1", the subsequent processing is the same as in the conventional method. Since the value of the buffer memory address counter in control unit 84 does not change, data in the next record is stored at the address next to the value of the address counter.

〔Effect of the invention〕

As explained above, according to the present invention, for records read from a storage device, not only comparison results with comparison data corresponding to each field but also comparison results between fields are compared by hardware. Since arbitrary logical operations are performed on each result, even when records are narrowly blocked, records can be searched for logical operations with search conditions that are more complex than before without any time delay. Furthermore, since only the necessary fields in a record are stored in buffer memory,
Buffer memory can be used effectively, and the amount of data transferred to the data processing device can be reduced, making it possible to reduce processing time.

[Brief explanation of drawings]

￥A! Figure I1; Figures 5 and 2 are block diagrams of conventional data search processing devices, Figure 3 is a logic sequence diagram of search condition-several circuits of a data search processing device showing an embodiment of the present invention, and Figure 4 is a logic sequence diagram of a number circuit. FIG. 5 is a block diagram of a data search processing device showing an embodiment of the present invention. FIG. 5 is a block diagram of the main part of FIG. 4. 1: Device 12: Storage control device, 3: Channel device, 4: Data processing device ft % 7140 + 44
+ 45: Comparison calculation circuit, 8, 41: Comparison data, 9,
39゜42.43: Comparison conditions, 10.16.26: Comparison results lunch, 17.19.21.27.29.31
:Logic operation lunch, 18.20.22.28.30.3
2.36: OR circuit, 33.34.35: AND circuit, 37 = Operation result latch, 40.47: Restriction register, 72: Buffer unit, 80:
Inter-field comparison register unit, 82: Latch circuit, 83 Two-wheel operation circuit, 84: Hunt roll unit, 86 "Yield length buffer, 87: Field length counter, 88: No. 7A memory, 104: Counter, 105 = decoder, 106: selector.

Claims (1)

[Claims] A circuit that sets arbitrary comparison conditions and comparison data for multiple fields of record data sequentially transferred from a storage device, and latches matching outputs that satisfy the comparison conditions for each field. , a latch circuit Mij that is arbitrarily set and reset in correspondence with the latch circuit, and a circuit that performs a logical operation between both latch circuits;
In a data search processing device that sets information such as attributes regarding each field and has a counter synchronized with the byte comparison of each field, a comparison condition is set between arbitrary fields, and a match output that satisfies the comparison condition is output. A launch circuit M? is set and reset arbitrarily in response to the latch circuit. 1 and the latch circuit M
1. and the latch circuit M, the following logical operation is performed on the comparison condition result L4 corresponding to the field and the comparison condition result between the fields, and the record search process is performed using the above operation result X,
A data search processing device characterized by comprising a control means for storing necessary fields of a search match record in a memory button.