JPS6059592A - Dynamic random access memory - Google Patents

Abstract

PURPOSE:To speed up data cycle time by writing plural input data in plural memories simultaneously with continuous reading from plural memory cells without overlap. CONSTITUTION:A data input buffer 17 is controlled by a write control clock WE' activated in one cycle time of a reference clock CAS' through a write timing circuit 16 or the like and plural input data are written in plural memory cells 12. These stored contents are stored in a corresponding data output buffer 20 through a data transfer gate 19 controlled by a transfer clock DT' activated in one cycle time delayed from the clock CAS'. The buffer 20 is controlled by reading clock SO', S1 successively activated in one cycle time of the clock DT' synchronously with the DT' and the stored contents are successively read out without overlap, so that the data cycle time is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a dynamic random access memory.

[Prior art]

In the following, all circuit descriptions are made using MOS) transistors (hereinafter referred to as MO8T)'Ir, used, and N-channel M
Dynamic random access memory consisting of O8T (
Hereinafter, it will be referred to as DRAM. ), high level is logic 1
11, and the low level is logic 10I.

As the speed of central processing units (CPUs) increases, even faster performance is required in both memory cycle time and access time.Currently, the operating efficiency of C1) U is sufficiently increased to compensate for the lack of memory speed. There are many cases where this is not possible. To address this lack of speed, for example, users are using parallel-to-serial conversion to improve data cycle time on the board, while MOS-T) RAM
The device achieves faster cycle time and access time than normal operation within the range of all memory cells or consecutive 4-bit memory cells on a selected word line.

This will be explained below using the drawings. FIG. 1 (Standard MO8-I with two rows of basic clocks in at to (C) and multi-address system) 11. An operation timing diagram of an AM high-speed operation mode is shown. It is activated in the normal cycle order shown in the same figure (al), and based on the activation transition time from high level to low level, set-up time and hold time are taken, row address and column address are given, and selection is made. After the read or write operation for the cell is completed, both clock RAS and clock CAS are set to high level to prepare for the next cycle. Each has an access time and a minimum time required for charging and balancing the internal nodes of the dynamic circuit operation, which determines the speed performance.

In order to realize a data cycle faster than the normal cycle, a page mode shown in FIG. 2(b) and a nibble mode not shown in FIG. 4(c) are provided. The page mode is
Clock 1tAs, following activation of CAS, clock C
Pulse application is repeated by AS, and a column address is given each time, and a read or write operation is performed for the memory cell on the word line selected by the clock RAS and the row address. Since the circuit operation is limited to column-related circuits, the speed is increased to 50 to 60% of the normal cycle. Nibble mode uses the same clock ILAS as page mode,
CAS timing, but the internal circuit uses clock RAS
.

Each time CAS is activated, the 5-bit information of the 4-bit memory cell is applied to each of the four sets of data buses, and read data is sequentially obtained at the data output in response to the activation of the clock CAS. Write operations can be performed in synchronization with CAB. Since the shift selection within 4 bits requires only communication with the p1 data bus, the cycle time is further increased to about 60% of the page mode. In nibble mode, the row and column addressing of the first cycle determines the 4 bits to be accessed, so no address input is given from the second cycle of clock CAS onwards.

In this way, the speed is increased by focusing on the clock CAS system or the column system in the clock RAS system 11.
This is basically a one-transistor cell refresh operation, and it is necessary to take as much time as possible.

The block diagram and operation timing of the conventional I)RAFJO column-related circuit are shown in FIGS. 2 and 3, respectively. In response to the activation of the clock CAS, the column-related timing generation circuit 5 operates and drives the first column 6, the first buffer 9, and the data output buffer 1o in this order, and reads out the read data of the memory cell 2 specified by the address input.
Bring to data output. If the write control clock WE is at a low level during the active period of the clock CAS, the write timing generation circuit 6 operates and writes to the data cover 7 and the write memory cell 2.

Regarding reading, as in the nibble mode, it is possible to prepare the data in the memory cell 2 up to the entrance of the data output buffer 10 in advance, so the access time can be increased to just move the data output buffer 10. However, the data output requires a reset period of the clock CAS as shown in Figure 3, and furthermore, in response to the transition from low level to high L//<
Since it is necessary to return 1% MK, there are constraints on shortening the data cycle time, such as the effective width of output data becoming strict. It is even more difficult to increase the speed of writing, and it is basically necessary to input data through the data capacitor 7a 8, the write gate 7, the data input/output bus 4, and the column decoder 3, and then the memory cell 2. No significant shortening can be expected.

On the other hand, considering fields that require high-speed data cycle times such as image processing, even faster data cycles for reading and writing are required. ing. Furthermore, most of the data is handled in units of 4 or 8 bits, and there is a problem in that there is a limit to high-speed data cycle time.

[Purpose of the invention]

An object of the present invention is to provide a dynamic random access memory having a faster data cycle by solving the above-mentioned problems. Or, in DR and AM, which have multiple basic timing clocks, address inputs for selecting multiple memory cells arranged in rows and columns, and one write control clock as external input terminals, multiple N data inputs, multiple By activating the write control clock within one cycle time of the N read control clocks and one data transfer lock external input, one data output, and the basic timing clock,
a write means for simultaneously writing data iN of the memory cells based on a data input; and a write means for activating the data transfer lock in a manner delayed from the basic timing clock on one side of the write operation, and synchronizing with this, and read means for sequentially activating N read control clocks and reading read data from the N memory cells consecutively so as not to overlap each other as the data output.

The dynamic random access memory of the second invention is configured such that the dynamic random access memory of the first invention is provided with an external input of N write-inhibit control clocks and a write-in control to control writing to the memory cell. It is constructed by adding selective write means for selectively writing by activating the clock and I.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram showing essential parts of an embodiment of the first invention.

This embodiment uses a basic timing clock CAS.

Address input for selecting a plurality of memory cells 12 arranged in rows and columns and one write control clock W
In a DRAM having E as an external input, a plurality of N data inputs DINO-DINN-1, a plurality of N readout control clocks SO~'A-1 and one data transfer lock DT external input, and one Data output D
OUT and activate the write control clock WE within one cycle time of the basic timing clock CAS to write data based on N data inputs T)INO to T)INN-1. An IJ write means for simultaneously writing into N memory cells 12, N data manual buffers 17 each connected to the data input/output bus 14, and one basic timing clock CAS for the 1 write operation. The data transfer lock DT is activated in a delayed manner, and in synchronization with this, the N read control clocks SO~5N-1'i are sequentially activated to output the read data of the N memory cells 12 as the data output DOTJ'l'. It is constructed by including N data amplifiers 18, data transfer gates 19, and N data output buffers 20 as escape means for reading data continuously without overlapping.

Next, the operation of this embodiment will be explained with reference to the operation timing diagram for N=4 shown in FIG.

The column basic clock CAS controls the entire data input/output system shown in FIG. When the clock CA8 is activated and the signal of the memory cell 12 on the selected word line is amplified on the digit line by the row basic clock RAS, the selected column decoder output is activated, and the signal of the memory cell 12 of N of them is activated. are respectively transferred onto N sets of data input/output buses 14. Each set of data amplifiers 18 is then activated simultaneously and the signals on data input/output bus 14 are rapidly amplified to logic levels.

The column-related timing generation circuit 15 based on the clock CAS directly controls the reading up to this point, and when the data transfer lock DT is activated after the data amplifier 18 has sufficiently amplified the data, the data transfer lock DT is activated as shown in FIG. The data transfer gate 19 is opened, and the signals of the N memory cells 12 are transferred to the input stage of each of the N data output buffers 2o.

These N data output buffers 20 are 80. St.
....

Each of them is individually activated by N read control clocks 5N-1. N memory cells 1
The interval during which clock DT is activated, which coincides with the cycle time of clock CAS, is such that all the data of 5N-1 from clock SO can be output as data output DOUT.
It needs to be activated one time at a time. As shown in FIG. 5, when clocks S3 are inputted from clock SO to clock S3 in such a manner that their respective active periods are continuous with the same width, the signals of memory cells 12 on four sets of data buses are input to data output DOUT. It will appear continuously with equal width within the interval of DT, and this will be repeated. Basically, the clock DT needs to be activated after a certain delay time after the clock S3 is activated and before the clock SO is activated.

When clock DT is activated, data output buffer 2
Since the data in the 0 input stage is newly replaced, the data output buffer 70 is required to perform a latch type operation so that no change occurs in the data output DOUT at this time.

As with conventional MOS-DRAM, writing is controlled by the clock CA8, and by activating the clock WEi during its active period, the data input D at that time is controlled by the clock CA8.
INO-DINN-1 will be written. However, in this case, there are 13-N data inputs INO to DINN-1, which are the same as the read control clock, and input data D is simultaneously input to N sets of data input/output buses 14 through each data manual buffer 17
INo to DINN-1 are sent and written into N memory cells 2 through the column decoder 13.

If it is desired to perform both writing and reading in one clock CAS cycle, conditions are set on the activation timing of the clock WE and the clock DT depending on which data is to be applied to the data output DOUT. When outputting data to be written, use the clock CAS in Figure 5.
As shown in the second cycle, the clock WE is first activated, and the input data DINO-
After DI-NN-1 is sufficiently amplified, clock DT is activated and output data DOUT is obtained through data output buffer 20. Conversely, it is activated when outputting read data.

As explained above, the reading method used in this embodiment can theoretically achieve a faster data cycle than the nibble 14 mode shown in FIG. 1 (C1).

In the nibble mode, a read or write operation is performed during the active period of the clock CAS, and during the reset period, data output is set to high impedance or the next address selection operation is performed.

In this embodiment, a plurality of read control clocks 5o-
8N-1' is provided in correspondence with the data input/output bus 14, so by creating an input configuration in which each active period is sequentially continued, only the active period of the nibble mode can be included in the data cycle time. . That is, the clock RAS.

FIG. 4 is an operation timing chart in which the cycle time of CAS- is kept within the active period N@ of read control clocks SO to 5N-1. This partial detailed circuit diagram shows a read system circuit 21 from the data transfer gate 19 in FIG. 4 to the data output DOUT via the data output buffer 20, and the figure shows one set of read data. I
It is assumed that the signals of the four memory cells 12 are sufficiently amplified by the data amplifier 18 and are present on the data input/output bus for /QO and T/QO. When the clock DT is activated, the internal timing clock DT
increases, MO8T Ql and Q2 become conductive, and l100
The true complementary logic levels on and l100 are transferred to node N1 and node N2, respectively. At this time, the data amplifier 18 is in a holding state after activation, and amplifies the data to a sufficient logic level even after transfer. Similar transfer operations are performed on the other three data input/output buses 14 as well. When new data enters node N1 and node N2 and a sufficient level difference occurs, read control clock SO can be activated to obtain data output, and when the complete logic level is reached, clock DT=i is reset. and node Nl and node N
Latch the data to 2. l100. l100 and node N
1. After node N2 is disconnected, clock RA-8 to clock CAS are reset, and the memory cell 12 side can enter a precharge period.

At the time of activation of clock SQ, node N7. Node N8 is at low level and high level respectively, data output DO
While UT is at a high level, node N as new data
1. Assume that node N2 is reserved at low level and high level, respectively. At this time, among the timings based on the clock SO, the precharge timing clock SoP is at a high level, and the activation timing clock SOO and the clock SO are at a low level, so that the node N3. N12 and N1
4 is at a precharged high potential, while node N4,
N5. N6. N9. NIO, Nll, N13 and N15
is at ground potential. When SO is activated, first SOO rises and then SoP moves to a low level. 500e receiving MO8T' Through Qto and Ql4, nodes N6 and N9 rise, respectively, MO8TQll and Ql
5 is conductive. The high level of node N8 is kept in a high impedance state, and MO8TQ15 to MO8TQ
l7. 17- is pulled to ground potential by covering Ql8. Also, MO8T Ql5 to MO8'l' Q
It is also connected to the clock SO through l6, and is also set to the ground potential. On the other hand, for node N7, MO8TQl
The entire MOi9T Q7 is connected to the clock s□ with low impedance, and is kept at the ground potential.

In this way, after the previous data is cleared and reset,
Allow the next clock SO to rise.

When the clock SO rises, MO8TQ9 is non-conductive and MO8TQl8 is conductive due to the level of the new data latched at nodes Nl and N2, so node N
4. N5 and N7 begin to rise. On the other hand, node N8. N
IO and N11 are suppressed at a low level. Node N7
When the level of MO8T exceeds the threshold voltage, MO8T Ql
3 and Q20 become conductive, and node N8 settles at ground potential. Furthermore, when the threshold voltage exceeds twice the threshold voltage, MO8T
At the level of the source-follower of Q26, node N15 exceeds the threshold voltage, and the conduction of MO8T Q25 moves node N14 to ground potential. MO8T Q8 and Ql
7 becomes non-conductive, nodes N1 and N2 are disconnected from the data output DOUT, and at this time, the data output buffer 20 driven by the clock SO is ready for the next activation of the clock DT. Become.

Finally, MO8T Ql2 and Ql3 of flip-flop configuration amplify the levels of nodes N7 and N8, and low level data is obtained at the data output DOUT. When reading by the clock SO is completed and it is reset, ie returned to high level, the clock SOO first goes low and MO8T Ql and Ql5 become non-conductive. As a result, a high level in a high impedance state is left at node N7, and node N8 is held at ground potential by MO8T Ql3. At this point the next clock 81
can be activated, and the read operation is repeated in the same way. In this way, reading for 4 bits is performed by connecting the active period from clock SO to clock S3t, and the precharge period of each read control clock SO to 5N-1 is made invisible, resulting in a high-speed data cycle. can be realized.

As described above, according to this embodiment, while writing data to N memory cells from N data input terminals at once, N read control clocks are sequentially activated to write data to N memory cells. M configured to read data continuously.
An OS-DRAM has been obtained, which can realize a read data cycle at an unprecedentedly high speed, and can perform data insertion with a margin, making it very effective as a device oriented toward high-speed data cycles.

FIG. 8 is a block diagram showing a main part of an embodiment of the second invention, and FIG. 9 is an operation timing chart thereof.

This embodiment is constructed by inputting N write inhibit control clocks f of the first invention shown in FIG. 4 to N data manual buffers 17', respectively.

Next, the operation of this embodiment will be explained. When the clock INHi is activated to a low level in a write cycle prior to whichever of the clocks CAS and WE is activated later,
The data manual buffer 17/ of the corresponding bit is kept isolated from the data input/output bus and no write operation is performed.

Therefore, according to this embodiment, it is not necessary to write data to N bits at the same time, and it is not necessary to write data that does not need to be written among N bits, so more rational operation is possible. Become.

Although the above explanation deals with an N-channel MO8) transistor as a transistor, the present invention can also be applied to P-channel MO8) transistors, insulated gate transistors in general, or other memory elements. Needless to say.

〔Effect of the invention〕

As described above in detail, the dynamic random access memory of the present invention includes a write means for simultaneously writing a plurality of N pieces of input data into N memory cells, and a read means for reading N memory cells 21- during one of the write operations. Since it is equipped with a readout means that reads out data continuously without overlapping, the reset period of the start column basic clock CA8, which was required in the conventional nibble mode read method with the highest speed data cycle, is no longer required, and This has the effect of reducing the data cycle time by up to 20%. Furthermore, by adding a means for selectively writing input data, it is possible to suspend input data that does not need to be written at the same time, resulting in a more rational write operation and a faster data cycle. can get.

[Brief explanation of the drawing]

FIG. 1 (al~(C1 is an operation timing diagram of three typical examples of conventional dynamic random access memory,
FIG. 2 is a block diagram showing a main part of an example of a conventional dynamic random access memory, FIG. 3 is an operation timing diagram thereof, and FIG. 4 is a block diagram showing a main part of an embodiment of the first invention. 5 is an operation timing diagram thereof, FIG. 6 is a partial detailed circuit diagram of the 22nd embodiment of FIG. 4, FIG. 7 is an operation timing diagram thereof, and FIG. 8 is an example of the second invention. A block diagram showing the main parts of the embodiment, and FIG. 9 is an operation timing chart thereof. ■・・・Column address inverter buffer, 2...
...Memory cell, 3...Column decoder, 4.
...Data input/output bus, 5...Column timing generation circuit, 6...Write timing generation circuit, 7...Short gate, 8... ...Data input/output buffer, 9...Data amplifier, ]0
...Data output buffer, Jl...Column address inverter buffer, 12...Memory cell, 13...Column decoder, 14...
Data input/output bus, 15...Column timing generation circuit, 16...Write timing generation circuit,
17.17'... Data person Kaha7a, 18.
... Data amplifier, I9゜19' ... Data transfer gate, 20 ... Data output buffer 7, 21 ... Lighting system circuit, N1-N13・・・
...Node, Ql~Q27 ...MOS)
Ransistor, R, As, CAS, WE, l)
'r, S Q~SN-/, T N1rO~INf4
N・/. 60081. Clock, DINO~DINN-/...
...Data input, DOUT...Data output.

Claims (2)

[Claims] (1) One or more basic timing clocks, multiple N data inputs that select multiple memory cells arranged in rows and columns, multiple N read control clocks, and one external data transfer lock. write input, one data output, and activating the write control clock within one cycle time of the basic timing clock to simultaneously write data based on the N data inputs to the N memory cells; means for activating the data transfer lock in a manner delayed from the basic timing clock on one side of the write operation, and in synchronization with this, sequentially activating the N read control clocks to output the N read control clocks as the data output. 1. A dynamic random access memory comprising: reading means for reading data from memory cells consecutively so as not to overlap. (2) 1 - 1 - multiple basic timing clocks, multiple N to select multiple memory cells arranged in rows and columns
External input of data input, N read control clocks, one data transfer lock, and N write inhibit control clocks, one data output, and five of the basic clocks are also performed within the cycle time. a write means for simultaneously writing data based on the N data inputs into the N memory cells by activating the write control clock; and writing to the memory cells by activating the write inhibit control clock. selective writing means for selectively writing, and one of the write operations activating the data transfer lock with a delay from the basic timing clock and sequentially activating the N read control clocks in synchronization with this; [7] A dynamic random access memory characterized by comprising: reading means for reading read data of the N memory cells consecutively so as not to overlap as the data output.