JPS6058502B2 - information processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system, and particularly to an information processing system that has a plurality of central processing units for calculations and processes array data at high speed for high-speed processing of vector calculations.

Generally, in scientific and technical calculations, especially in simulator environments, simulator models are constructed using simultaneous linear equations, differential equations, and the like.

This type of problem ultimately requires repeated matrix calculations, which requires a large amount of calculation time on a general-purpose computer.

When data can be handled as a matrix in this way, this data, that is, a vector, is suitable for handling in a system that can perform parallel operations. A vector is a set of mutually independent items (scalars), such as a set of row elements, a set of column elements, a set of diagonal elements, etc. of a matrix. In most matrix operations, this vector is the unit of processing.
In vector operations, it is easy to utilize parallelism due to the independence of each item. In order to perform a series of vector computations using a plurality of arithmetic processing units, a control central processing unit that controls the arithmetic processing unit group determines all initial conditions and termination conditions related to the vector computation, Although a method of sequentially notifying each arithmetic processing unit and then starting arithmetic processing is conceivable, the present invention provides an improved vector arithmetic system that minimizes the load on the control central processing unit.

An object of the present invention is to combine a plurality of general-purpose central processing units to form a complex information processing system consisting of a control central processing unit that controls the entire system and a calculation central processing unit group that shares vector calculations. The purpose of this invention is to provide a highly versatile high-speed vector arithmetic system.

In particular, it is an object of the present invention to provide a high-speed hector calculation system in which the processing time required by a control central processing unit to notify the start and end conditions of vector calculation is minimized, and the overall vector calculation processing time is shortened. Furthermore, each central processing unit for calculations has the ability to calculate and know the number of repeated calculations of the vector group related to its own calculation processing by parallel processing, thereby realizing a faster vector calculation calculation system. The information processing system of the present invention includes a control central processing unit and N arithmetic central processing units having the same configuration and controlled by commands from the control central processing unit, The central processing unit, prior to supplying a command instructing vector calculation to P units (1<P<.N) of the calculation central processing units,
A different logical number P for each central processing unit for calculation
. The arithmetic central processing unit includes a circuit, and the arithmetic central processing unit divides the supplied total number of repeated operations C by the number of used units P to obtain a quotient Q and a remainder 1, and this remainder 1 is the value obtained by adding 1 to the logical number Pi. If it is, the quotient Q is output as the number of vector operations Q, and if the remainder 1 is less than the value obtained by adding 1 to the logical number P, then 1 is added to the quotient Q as the number of vector operations Qi.
and a calculation circuit for calculating the number of calculations that outputs the sum of the values. That is, the information processing system of the present invention:
An information processing system consisting of a control central processing unit and a plurality of arithmetic central processing units that have the same function and are controlled by commands from the control central processing unit, and the control central processing unit is It has a central processing unit control circuit, and the control circuit transmits the logical number Pi of each calculation central processing unit and the number of units used P value to the P calculation central processing units to be used for the purpose of vector calculation. and a means for transferring the total number of repeated operations C value of the vector operation prior to the vector operation, and each operation central processing unit uses the P, value, P value, and C value supplied from the control central processing unit. It is constituted by having means for calculating and determining the number of vector calculations Q or Q+1 to be divided and repeatedly calculated within the own calculation central processing unit.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and is a block diagram for explaining an overview of the operation of the present invention.

The information processing system shown in FIG.
, arithmetic central processing unit control circuit 10, arithmetic central processing unit 20, 21,...2n, calculation number calculation circuit 200
, 210, . . , 2n0, a main memory device 3, a main memory interface line 4, and a common bus line 5.

When starting a vector calculation, the control central processing unit 1 selects P units used for one calculation among the calculation central processing units 20, 21, . . . , 2n that share and execute vector calculations. Initial setting, startup, calculation status measurement, etc. are performed for the central processing unit for calculations through the common bus line 5.

After initial setting, the activated arithmetic central processing units each perform their assigned vector arithmetic operations according to independent software programs. The present invention aims to standardize control at the time of initial setting and improve the performance of the system.

FIG. 2 shows an example of vector distribution 3R on the main storage device 3 when vector operations are performed in the embodiment shown in FIG.
It shows the correspondence of PEl, . . . PE, . . . PEp-1. The vectors on the main storage device 3 are distributed at regular intervals with a constant word length, and FIG. 2 is a diagram in which the constant intervals are modeled as zero.

The total number of vector words is C, and C vectors are
The data is distributed in an orderly manner to the central processing units PEO, PEl, and PEP-1 for use in calculations.

That is, when C is divided using the dividend P as the divisor, C=P・
A relationship of Q+I is established. This means that Q+1 vectors are allocated to I calculation central processing units, and the remaining (
This shows that Q vector operations are assigned to the P-1) operation central processing units. Furthermore, Figures 1 and 2
The present invention will be explained in detail using the drawings.

Normally, vector operations are performed between two groups of vectors in the main memory, and there are two sets (for example, 30, 31) of vector distribution example 3R, and operations are performed between them. are executed, and the results are added or stored in a manner that is distributed on main memory at regular intervals.

Now, a case will be described in which an operation is performed between two sets of C vectors and stored in C areas.

Prior to calculation, the control central processing unit 1 calculates the value of the total number of vector words C, the number of calculation central processing units to be used,
In other words, the number of units used is P
O, PEl, ... Notify PEP-1.

This is notified all at once via the common bus line 5. Furthermore, a logical number Pl (P, P-1) having a value from 0 to P-1 is assigned to each of the P central processing units for calculation.

Control lines 60, 61, .
. . 6n, it is possible to send the corresponding logical number Pi only to an arbitrary arithmetic central processing unit PEl.

In this example, the logical number Pf is sent through the common bus line 5 to all the arithmetic central processing units PEi specified by the control line 61.

These P calculation central processing units are also notified of the vector calculation start address, the distance between each vector, etc.

This operation can be performed at the same timing. Total number of repeated operations C
, the number of calculation central processing units P and the logical number Pi assigned to the own calculation central processing unit are given, and furthermore, when the start of vector calculation is activated through the common bus line 5 or the control line 61, the calculation The central processing unit PEl calculates the total number of repeated vector operations C using the operation number calculation circuit 210.
is divided by the number of units used P, and the quotient Q and remainder 1 are calculated. Further, the operation number calculation circuit 210 compares Pi+1 with the remainder 1, and if P1+1×I, it adds 1 to the quotient Q to obtain Q+1, and if P,+1>I, the quotient Q is calculated by the central processing unit for own calculation. It has means for storing the number of vector operations to be executed by the device PEl as Q. Furthermore, the calculation central processing unit PE
, uses the vector operation start address and the distance between each vector to read Q or Q+1 vector groups, perform the operation, and store them in the Q or Q+1 area. Complete.

Operation count calculation circuit 200, 210,..., 210,...
. , 2n0 is shown in FIG. 3. The total number of repeated operations register 70 holds the total number of repeated operations C, the number of used units register 71 holds the number of used units P, the logical number register 72 holds the logical number P, the division circuit 73 performs division, and the Input the quotient register 75 which holds the quotient Q, the remainder register 75 which holds the remainder 1, the remainder 1 held in the remainder register 75, and the logical number P held in the logical number register 72, and compare the values remainder 1<5P1+1. ,P,+1kuI
A comparator circuit 76 outputs a ゜“1゛ value when P,+1〉1, and a ゜0゛ value when
It consists of an adder 77 that adds the outputs of the comparison circuit 76, and a vector operation number register 79 that holds the number of vector operations Qi to be executed by the own calculation central processing unit PEi of the addition result. In the present invention, the control central processing unit 1
This allows a plurality of arithmetic central processing units to share and execute vector calculations, and concurrently allows a plurality of other sets of arithmetic central processing units to execute other vector calculations.

In these calculations, the control central processing unit 1 needs to consider the distribution of the calculation central processing units used for the calculations, but once this has been decided, it is as if the calculation is activated by one calculation processing unit. Similarly, a group of arithmetic central processing units can be activated, and the logical operation within the control central processing unit becomes very simple. When the calculation central processing unit that has executed one vector calculation in each group completes the calculation on its own calculation central processing unit, the control line 60, 61,
..., 6n, the control central processing unit 1 is notified of the completion of the calculation, and the control central processing unit/device that has detected the completion of Q+1 calculations can move on to the next operation.

In the information processing system of the present invention, by adding an operation count calculation circuit to each of the arithmetic central processing units, each arithmetic central processing unit can calculate the number of operations. This has the effect of reducing the load.

As explained above, the present invention includes a central processing unit for calculation,
By having the ability to determine the number of calculations, it is possible to control a high-speed vector calculation system using a central processing unit for simple control.

) Brief Description of the Drawings FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a data distribution diagram on the main memory of vector operation data executed by the embodiment shown in FIG. 1. FIG. 3 is a block diagram showing an example of the operation count calculation circuit shown in FIG. 1.

1... Central processing unit for control, 10... Central processing unit control circuit for calculation, 20, 21, 22, 23, ~
, 2n, PE0, PE1, ~, PEP-1... Central processing unit for calculation, 200, 210, 220, 230, ~
, 2n0...Calculation circuit, 3...
Main memory device, 4...Main memory interface line, 5...Common bus line, 60, 61, 62, 63, ~,
6n...Control line, 70...Total repetition operation number register, 71...Number of units used register, 72...
...Logic number register, 73...Division circuit, 74.
... Quotient register, 75 ... Remainder register, 76 ... Comparison circuit, 77 ... Adder, 7
9... Vector operation count holding register, P...
・・Number of units used, Ppi・・Logical number, C・・・・・
・Total number of repeated operations, Q...Number of vector operations.

Claims (1)

[Claims] 1 includes a control central processing unit and N arithmetic central processing units having the same configuration and controlled by commands from the control central processing unit; P units of central processing units (1≦P≦N
), a different logical number Pi (0≦Pi≦P−1) is transferred to each of the P calculation central processing units, and at least the P calculation central processing units are a calculation central processing unit control circuit for commonly supplying the number of used units P and the total number of repeated operations C to the central processing units for calculations; said central processing unit for calculations uses the supplied total number of repeated operations C; The quotient Q and remainder I are obtained by dividing by the number of units P, and if this remainder I is greater than or equal to the value obtained by adding 1 to the logical number Pi, the value obtained by adding 1 to the quotient Q is output as the number of vector operations Qi, and the value obtained by adding 1 to the quotient Q is output as the number of vector operations Qi. An information processing system comprising: an operation count calculation circuit that outputs the quotient Q as the vector operation count Qi if the remainder I is less than the value obtained by adding 1 to the logical number Pi.