JPS6057437A - Compiler device - Google Patents

Abstract

PURPOSE:To delete a redundant store instruction covering plural blocks and to produce a machine word program having a small quantity of memory occupation, by putting substitution equations to the same variable with superposition into 2 immediately subsequent blocks. CONSTITUTION:A common substitution equation deciding part 24 detects a block A containing plural immediately subsequent blocks in a flow graph memory 23 and checks the equations in these subsequent blocks. When the variable at the left side of a substitution equation detects the same equation, the position information in the flow graphs of two equations is transferred to a register substitution equation producing part 25. The part 25 changes the variable at the left side of the substitution equation into a register which is common to two equations. Then a deciding part 26 for immediately preceding block to be controlled decides an immediately preceding block which is controlled by the block A on the basis of the flow graph. A variable substitution equation producing part 27 adds an equation which substitutes the contents of the register decided by the part 25 to the variable common to two equations at the head of a block in the flow graph. Then all blocks in the memory 23 are processed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a compiler device that performs flow analysis using a flow graph when converting a high-level language source program into a machine language program.

Conventional configurations and their problems In recent years, high-level languages that are easier for humans to understand have been used in the development of microcomputer software in place of the conventional assembler language. For this reason, a compiler that translates into memory-efficient machine language is essential. Conventional compilers translated a set of data into machine language.

This method generates many load/store instructions, resulting in inefficient translation results. Conventionally, in order to improve this drawback, translation into machine language has been performed on a block-by-block basis. Even in this case, it is difficult to eliminate redundant load/store instructions that extend between blocks. In addition, optimization processing performed by flow analysis that analyzes the flow of data includes (1) removal of common expressions, (2) movement of loop-invariant expressions, and (3) optimization of loop control variables. Since it requires division processing, it is not easy to implement considering execution speed and program size.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional drawbacks by providing a compiler device that eliminates redundant store instructions extending between blocks through relatively simple processing and generates a machine language program that occupies less memory. The purpose is to provide.

Structure of the Invention The present invention provides a 70-graph memory for storing a flow graph created from intermediate code, and a first 70-graph memory in the flow graph memory.
a common assignment expression determination unit that detects assignment expressions for the same variable included in each of the immediately following blocks of the block; and a common assignment expression determination unit that generates an assignment expression for the same register instead of the variable for the assignment expression detected by the common assignment expression determination unit. a register assignment expression generation unit; a to-be-fitted predecessor control block determination unit that detects a second block that is immediately dominated by the first block; This is a compiler device that is equipped with a variable assignment expression generator that generates expressions to be assigned. This device can eliminate duplicate assignment expressions that exist between blocks, and is a machine language that occupies less memory. You can get the program.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows an example of a high-level language program that includes an assignment expression for the same variation in the immediately succeeding block. Equations 1 and 2 are assignment expressions for the same variable y. Figure 2 shows a flow graph representation of the program in Figure 104
and 6 are the immediately succeeding blocks of block 3 υ, and 6 is the block immediately preceded and dominated by block 3. Figure 3 represents each formula in block 4 and block 5 in a format that takes into account the internal registers of the computer. 07 indicates the register name, and 8 and 9 represent block 4 and block 6.
This is an assignment expression for the same variable that is duplicated between. Fourth
The figure is a diagram in which Equations 8 and 9 are moved to the common immediately succeeding block 6 of blocks 4 and 6 (this is a block that is immediately preceded and dominated by PU o and RI 3). 28 is deleted from block 4 and formula 9 is deleted from block 6.

A common assignment expression 1o is added to block 6. As a result, the assignment formulas for the same variables that were duplicated in blocks 6 and 6 are reduced to one formula, making it possible to obtain a machine language program that occupies less memory. The above is a general description of the present invention. Next, the hardware that performs these processes will be explained. FIG. 6 shows a hardware configuration for realizing the present invention. 20 is a converted intermediate code, 21 is an intermediate code reader that reads the intermediate code 2o, and 22 is a flow graph that configures the intermediate code 20 read by the intermediate code reader 21 into a flow graph as shown in FIG. A creation unit 23 is a flow graph memory that stores a flow graph spanning the entire program, and 24 is an assignment formula for the same variable in a block immediately following a certain block under the control of a common assignment formula determination unit 24. 26 is a register assignment expression generation unit that changes the expression into an assignment expression for a register; 26 is a pre-control lock determination unit that determines a block to which an expression for assigning the value of the register determined by the register assignment expression generation unit 26 to a variable is added; 27 is a variable substitution formula generation unit that adds a formula for substituting the above-mentioned register value to liquid yield at the beginning of the block determined by the inserted preceding dominant block determination unit 26; 29 is the machine language generated by the code generator 2B.

The common assignment formula determination unit 24 selects a block (A
) is detected, the expressions in each of the immediately succeeding blocks are examined, and when an expression is detected in which the variable on the left side of (1) is the same as the assignment operator, information on the positions of these two expressions in the flow graph is stored in the register. It is passed to the assignment expression generation unit 26. Change the variable on the left side of the register assignment expression generation operator to a register common to the two expressions. Then, the fitted preceding dominant block determination unit determines the block to be immediately preceded and controlled by the aforementioned block (A) based on the flow graph. Then, in the variable assignment expression generation unit 2γ,
The register assignment formula generation unit 2 is placed at the beginning of the block in the flow graph determined by the inserted preceding dominant block determination unit 26.
Add an expression that assigns the contents of the register determined in step 5 to a variable common to the above two expressions. The above processing is then performed for all blocks in the flow graph memory 23. As described above, according to the present invention, duplicate assignment expressions for variables in each block can be deleted.

Although the example of this embodiment has been explained with reference to the case where there are two diameter wire blocks as shown in FIG. 2, the same applies to the case where there are two or more diameter wire blocks. Also, as shown in Figure 6,
Even if part of the diameter line block contains assignment expressions for the same variable.

All you have to do is create a new block at the location shown in 11 and generate an expression in it to assign the contents of the register to a variable.

Effects of the Invention According to the optimization method of the present invention, when assignment formulas for the same variable exist redundantly in two or more diameter line blocks, redundant assignment formulas for variables in each block can be deleted. , it is possible to obtain a machine language program with good memory efficiency.

[Brief explanation of drawings]

Figure 1 is a program diagram showing an example of a high-level language program that includes assignment expressions for the same variable in the diameter line block.
Figure 3 is a program diagram that expresses the program in Figure 1 using a flow graph, Figure 3 is a program diagram that expresses the flow graph in Figure 2 in a format that takes registers into consideration, and Figure 4 shows that the present invention eliminates redundant assignment expressions. FIG. 6 is a block diagram of a compiler device in an embodiment of the present invention. FIG. 6 is a program diagram showing an example of a flow graph of a program having three or more diameter line blocks. FIG. 7 is a program diagram showing a flow graph resulting from applying the present invention to the flow graph of FIG. 23...Flow graph memory, 24...
- Common assignment formula determination unit, 26...Register assignment formula generation unit, 26...Inserted preceding dominant block determination unit, 27...Variable assignment formula generation unit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] A flow graph memory that stores a flow graph. a common assignment expression determination unit that detects assignment expressions for the same variable included in each of the blocks immediately following the first block in this flow graph memory; and a variable substitution for the assignment expression detected by the common assignment expression determination unit. a register assignment expression generation unit that generates an assignment expression for the same register, an immediately preceding dominant block determining unit that detects a second block that is immediately preceding dominated by the first block, and an immediately preceding controlling block determining unit that detects a second block immediately preceding controlled by the first block; a variable assignment expression generation section that generates an expression for assigning the contents of the register to the variable at the beginning of the second block detected by the first block; A compiler device characterized by eliminating duplicate assignment expressions for variables.