JPS6057032B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece equipped with a variable frequency dividing circuit and capable of easily measuring rate.

Conventionally, the rate adjustment of electronic watches equipped with a crystal oscillation circuit has been carried out by adjusting the trimmer capacitor built into the crystal oscillation circuit to match the oscillation frequency.

However, the above method has drawbacks such as large rate changes due to changes in the trimmer capacitor over time and the high price of the trimmer capacitor, so the frequency division ratio of the frequency dividing circuit is changed without using the trimmer capacitor. A so-called digital rate adjustment method has been proposed in which the rate is changed at regular intervals. However, although this digital rate adjustment method has many advantages, the main reason why it has not been adopted to date is as follows.
This is thought to be because the rate measurement is difficult because the variable period of the frequency division ratio is not constant for each clock. The present invention has been made in consideration of the above-mentioned problems, and an object of the present invention is to provide an electronic timepiece that employs a digital rate adjustment method and allows easy rate measurement.

The gist of the present invention to achieve the above object is to provide a reference oscillator, a frequency divider circuit, a frequency division ratio variable circuit for varying the frequency division ratio of the frequency divider circuit, and a frequency division ratio variable circuit that sets the q division ratio. In an electronic timepiece having a frequency division ratio setting means and a digital display means, a rate measurement mode setting means, a variable frequency division inhibiting means controlled by the rate measurement mode setting means, and the frequency division ratio setting means A rate signal generation circuit is provided which outputs rate adjustment value information based on the frequency division ratio set by the rate measurement mode, and when the rate measurement mode setting means is set, the variable frequency division operation is stopped and the rate is displayed on the digital display means. It is characterized by displaying adjustment values. An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing the display state of the electronic timepiece according to the present invention, where the figure A shows the time display state in the normal watch operation mode, and the front view shows the rate display state in the rate measurement mode. . In the figure, 1 is an electronic clock, 2 is a digital display device consisting of a liquid crystal display cell, and 3 is a watch for setting the operating mode. Because of this, the digital display device 2 is in the time display state and is displaying 1m3 2@. From this state, when the user 3 is pulled out one step as shown in the diagram and the rate measurement mode is set, the digital display device is switched to the rate display state, and the rate adjustment value set by the frequency division ratio setting means, which will be described later, is displayed. 0.30S1d is displayed. FIG. 2 is a block diagram of the electronic timepiece shown in FIG. 1, where 5 is a reference oscillator equipped with a crystal oscillator and generates a reference signal of about 32,768 Hz, and 6 divides the frequency of the reference signal to generate a timing signal φ. A frequency dividing circuit, 7 is a clock circuit that counts the clock signal φ and generates time information, 8 is a decoder that converts the time information of the clock circuit 7 into a display signal, 9 is a display drive circuit, and 2 is shown in FIG. This is a digital display device shown. 10 is a frequency division ratio variable circuit for varying the frequency division ratio of the frequency division circuit 6; 11 is a switch block as a frequency division ratio setting means for setting the frequency division ratio of the frequency division ratio variable circuit 10; In this case, it is composed of six switches 11a to 11f.

12 is a decoder that converts the frequency division ratio set in the variable frequency divider circuit 10 by the switch block 11 into a display signal as rate adjustment value information; 13 is a rate measurement mode setting means for setting the rate measurement mode; this embodiment In this case, a mode switch is used which is controlled by the operation of the user 3 as shown in FIG.

14 is an AND gate as variable frequency division inhibiting means controlled by the mode switch 13; 15 is an exclusive OR gate (hereinafter referred to as EXOR gate) for adding the interrupt signal passing through the AND gate 14 to the frequency division circuit 6; 16 is an inverter.

Next, the operation of the electronic timepiece having the above configuration will be explained.

In the clock operation mode in which the user 3 is held in the clock operation position as shown in FIG. 1A, the mode switch 13 in FIG. Yes, and the control terminal D of the decoder 8
Since the control terminal D of the decoder 12 is set to logic "0" via the inverter 16, the display drive circuit 9 is in a state where the signal from the decoder 8 is supplied. In this embodiment, the switch 11c of the switch block 11 is set as the digital rate adjustment, so the frequency division ratio variable circuit 10 interrupts according to the periodic signal supplied from the frequency division circuit 6 to the periodic terminals T, -T6. An interrupt signal is generated at the output terminal 0. As a result, the interrupt signal from the frequency division ratio variable circuit 10 is transmitted to the AND gate 14 and the EXO
By performing the variable frequency division operation that is added via the R gate 15, the error in the oscillation frequency of the reference oscillator 5 with respect to the reference value is corrected, and a correct clock signal φ is generated. Time information generated by driving the clock circuit 7 with the clock signal φ is displayed on the digital display device 2 by the decoder 8 and the display drive circuit 9.
At this time, the display drive circuit 9 AC drives the liquid crystal display unit constituting the digital display device 2 using an AC signal of about 32 Hz supplied from the frequency dividing circuit 6. A case will be described in which an attempt is made to measure the rate of an electronic watch in the above state using a commercially available rate measuring device for quartz watches. That is, when an electric field detection microphone included in a commercially available rate measuring device detects an electric field signal leaking from the digital display device 2 of the electronic timepiece, a differential waveform of the AC signal driving the liquid crystal display cell with AC is obtained. It is well known that in the case of an ordinary electronic timepiece that does not perform variable frequency division, the rate is measured by measuring the period T between n pulses of this differential waveform. However, it is also well known that in the case of the electronic timepiece of the present invention, which has a variable frequency division, the period T varies depending on the state of the interrupt signal, so rate measurement cannot be performed as it is. Next, the rate measurement mode of the electronic timepiece according to the present invention will be explained.

By pulling out the user 3L as shown in Figure 1, the
The mode switch 13 in the figure is set to logic 0 and the electronic timepiece enters the rate measurement mode.In other words, the AND gate 14 is turned OFF and the variable frequency division operation is no longer performed to block the interrupt signal. At the same time, the gate control terminal D of the decoder 8 is inverted to the logic "゜0" and the control terminal D of the decoder 12 is inverted to the logic "゜1", so that the display drive circuit 9 is supplied with the signal from the decoder 12. becomes,
As a result, the digital rate adjustment value information obtained by converting the frequency dividing ratio set in the variable frequency dividing circuit 10 into daily difference S/D is displayed on the digital display device 2 as shown in the opening of FIG. The AC signal supplied to the circuit 9 is an AC signal based on the oscillation frequency accuracy of the reference oscillator 5. Therefore, by measuring the electronic clock in this state with the rate measuring device equipped with the above-mentioned electric field signal detection microphone, the reference oscillator 5 can be detected.
By adding the digital rate adjustment value displayed on the digital display device 2 to this measured value, the digital rate-adjusted timing signal φ can be obtained. You can know the rate of When the rate measurement is completed, the mode switch 13 is switched to logic "1" by pushing the user 3 back to its original state, and the mode returns to the clock operation mode.The rate adjustment value information shown in FIG. The difference is not limited to the daily difference shown in this implementation, but may be a monthly difference or a yearly difference,
Furthermore, the ratio may be displayed using PPM, or the set switches may be displayed using numbers or symbols. Furthermore, the concept of the present invention can be applied to a hand movement display type electronic watch equipped with a pulse motor, and in this case, the mode switch can be used to stop the variable frequency dividing operation, and at the same time, the operation can also be performed using the clock signal φ. The digital rate adjustment value 2 can be determined based on the state of hand movement by stopping the hand movement and performing a hand movement operation that changes again based on the variable frequency division set value. Furthermore, in this case, the rate adjustment value information can be displayed by separately providing a display element such as a light emitting diode, or by displaying the rate adjustment value printed on a rotating member for setting the switch so that it can be seen from the outside on the dial. It is also possible to display the location, for example in the calendar window 2. Also, the timing signal φ for driving the pulse motor generated while the rate measurement mode is set.
It is also possible to store the value and then, after returning to the timepiece operation mode, speed up the pulse motor by the amount of the stored value to compensate for the delay in the hand movement display device that occurs when measuring the rate. As described above, in the present invention, a rate measurement mode setting means is provided in a variable frequency division electronic timepiece, and by setting the rate measurement mode as necessary, the frequency data of the reference oscillator is output as a rate measurement signal. At the same time, since it is configured to clearly display digital rate adjustment value information, it is now possible to measure the rate of variable frequency division type electronic watches using a conventional rate measuring device, which was previously considered difficult. By adopting this method, the cost reduction and reliability improvement of electronic watches can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an electronic timepiece according to the present invention, and FIG. 2 is a block diagram of the electronic timepiece shown in FIG. 1...Electronic clock, 2...Digital display device, 3...Reuse, 5...Reference oscillator,
6... Frequency divider circuit, 10... Frequency division ratio variable circuit, 11... Switch block, 12...
··decoder.

Claims (1)

[Claims] 1. An electronic device having a reference oscillator, a frequency dividing circuit, a variable dividing ratio circuit for varying the dividing ratio of the frequency dividing circuit, a dividing ratio setting means for setting a dividing ratio in the variable dividing ratio circuit, and a digital display means. The timepiece includes a rate measurement mode setting means, a variable frequency division inhibiting means controlled by the rate measurement mode setting means, and a frequency division ratio set in the frequency division ratio variable circuit as rate adjustment value information. A decoder is provided to convert the variable frequency division operation into a display signal by the variable frequency division inhibiting means when the rate measurement mode setting means is set, and the rate adjustment is output from the decoder to the digital display means. An electronic clock that displays a value.