JPS6055623A - Aligning device - Google Patents

Abstract

PURPOSE:To enable positive detectin of the position of an alignment mark by comparing the summed data obtained by a plurality of times of scanning with specific data having a predetermined value and by determining the pattern position according to timing of the signal output of a comparing meas which outputs the compared result. CONSTITUTION:When instrumentation is started, data of memory 152 and data of the optical signals digitized by an A-D convertor 104 are inputted to an adder 150, and their sum is written in the memory 152. Thus, each digital datum of an optical signal obtained by each scanning is successively stored in the memory 152. When a predetermined times of instrumentation are completed, a microprocessor searches the peak data to calculate a slice level from these paek data. The slice level set in the memory 109 is successively compared with the summed date stord in the memory 152 by a digital comparator 106, and the passing timing of the slice level is determined at the counting circuit 119.

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to an apparatus for aligning two objects, and particularly for aligning a semiconductor integrated circuit pattern on a mask or reticle to a predetermined position on a wafer (hereinafter referred to as alignment). The present invention relates to a position detection circuit that detects the position of an alignment mark on a mask or reticle and the position of an alignment mark on a wafer prior to processing.

(Prior Art) A semiconductor manufacturing process includes a step of sequentially transferring several patterns onto a wafer to form a semiconductor integrated circuit. In this case, in order to accurately position another pattern on the wafer onto which the previous pattern has already been transferred, it is necessary to align the mask with the pattern and the wafer with high precision. This alignment is achieved by first determining the relative positional relationship between the alignment marks written on the mask and wafer by photoelectrically detecting them, and then moving them by a predetermined amount based on this positional relationship. .

By the way, alignment mark detection is performed by identifying that the peak level of the detection signal is higher than a predetermined reference level. However, conventionally, this reference level has been fixed, and depending on the type of wafer or mask that is the substrate for the alignment mark, it may be too high or too low, resulting in detection failure. In some cases, the reference level was manually adjusted when a failure occurred.

(Objective) The present invention has been proposed in view of the above-mentioned drawbacks, and is an alignment device having a position detection circuit that automatically adjusts a reference level and reliably detects the positions of alignment marks on two objects. The purpose is to provide.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 shows the external appearance of a positioning device having a position detection circuit according to an example of the present invention. Reference numeral 1 denotes a mask provided with an integrated circuit pattern, which includes mask alignment marks and mask wafer alignment marks. 2
is a mask stage that holds the mask 1 and moves the mask 1 in the plane and in the rotational direction (2). 3 is a reduction projection lens, 4 is a wafer with a photosensitive layer, and a mask wafer alignment mark and a wafer alignment 5 is a wafer stage. The king bar stage 5 holds the wafer 4 and moves it in the plane and in the rotational direction, and also controls the wafer baking position (projection bone). 6 is the objective lens of the detection device for TV wafer alignment, 7 is an image pickup tube or solid-state image sensor, and 8 is a TV receiver for video observation. 9
is a binocular unit that projects the wafer 4 through the projection lens 3.
useful for observing the surface of Reference numeral 10 denotes an upper unit housing an illumination optical system array (a detection device for mask wafer alignment) for converging the mask illumination light emitted from the light source 10a.

The wafer stage 5 holds the wafer transported by a wafer transport means (not shown) at a predetermined position, and first moves to a position where the alignment mark on the wafer is within the field of view of the objective lens 6 for television wafer alignment. The positional accuracy at this time is due to mechanical alignment accuracy, and the field of view of the objective lens 6 is approximately 1 to 2 ffl+++ in diameter. The alignment mark within this field of view is detected by the image pickup tube 7, and the alignment mark is detected by the image pickup tube 7.
- Using an alignment reference mark (described later) as a reference, the coordinate position of the alignment mark on the wafer is detected from there. On the other hand, since the detection position for automatic alignment of the projection optical system and the position of the reference mark for TV/wafer alignment described above are set in advance, these two
The amount of feed of the wafer stage 5 to the auto-alignment position is determined from the position of the point and the coordinate position of the television wafer alignment mark.

The position detection accuracy of TV wafer alignment is less than ±5μ, and even when taking into account the error caused by moving the wafer stage from the TV/phenol 1 alignment position to the mask/phenol 1 alignment position, it is ±10μ.
That's about it. Therefore, fine alignment is approximately +10μ
It is sufficient to perform alignment within a range of 17100 or less, which is the field of view range of conventional alignment, which is less than 17100, which means that alignment can be performed faster than conventional alignment.

FIG. 2 is a diagram showing the optical system of the alignment apparatus according to the embodiment of the present invention, and shows a state in which alignment mark detection signals for the mask and wafer are sent to the position detection circuit. In the figure, a mask 1, a reduction projection lens 3, a wafer 4, and a sea urchin stage 5 are as shown in FIG. The projection lens 3 is depicted schematically for convenience. 11 and 11'
is a mask alignment mark, which is engraved in an immovable location such as a lens barrel or a part of the device.

On the other hand, at the positions indicated by mask 1''2 (1, 20') there are scan lines 60, as indicated by numbers 75 and 76 in FIG. 3(A).
A line or slit-shaped alignment mark is provided at an angle of 45 degrees with respect to the other direction. In addition, at the position indicated by 21.21' on the Ever 4, there is a line inclined at 45 degrees with respect to the scanning line 60 as indicated by the month numbers 71.72 and 73.74 in Fig. 3cA). Alternatively, a slit-shaped alignment mark is provided. Normally, positioning is performed using signals from both the left and right observation systems.

Note that the alignment marks on the mask 1 and the alignment marks on the wafer are arranged so that when a system other than the same-magnification projection system is used, the dimensions of both alignment marks do not change even if the projection or back projection is performed. The dimensions are set to be different, and in this case, the reduction magnification is set so that the dimension of the alignment mark on the wafer is divided by the dimension of the alignment mark on the mask.

Returning to FIG. 2, 22 is a laser light source, and 23 is an optical deflector such as an acousto-optic system element. The optical deflector 23 switches the light emission direction upward, horizontally, and downward in response to a switching signal from the outside. 24 and 25 are convergent cylindrical lenses, which are arranged so that their generating lines are perpendicular to each other, and have the function of converting the cross-sectional shape of the laser beam into a linear one. 26 and 27 are trapezoidal prisms, which have the function of refracting the light that has been deflected downward on one side by the optical deflector 23 in the opposite direction. 28 is a rotating polygon mirror (polygon) that rotates around a rotation axis 29.

The laser beam H30 emitted from the laser light source 22 passes through the cylindrical lens 24 and the prism 26, depending on the state of the optical deflector 23, into a slit-shaped beam 30a.

The optical path is either the slit-shaped light IN 30b passing through the cylindrical lens 25 and the prism 27, or the spot-shaped nine-ray beam 30c traveling straight, but in either case, it converges to a point 31 on the surface of the rotating polygon @28J: do.

32, 33, and 34 are intermediate lenses, 35 is an optical path splitting mirror, 36 is a half mirror forming a visual observation system 37, 38, 37 is a lens, and 38 is an eyepiece that forms an image of the wafer surface. 39 is a lighting system that does not require visual observation 40.41
40 is a condenser lens, and 41 is a lamp. 42 is a half mirror forming the photoelectric detection system 43, 44° 45.46; 43 is a mirror;
44 is a lens, 45 is a spatial filter, 46 is a condenser lens, 47 is a photodetector for detecting an alignment pattern signal, 57 is a lens, and 58 is a photodetector for detecting a synchronization signal.

Further, 48, 49, 50, and 51 are total reflection mirrors, 52 is a prism, and 53 is an f-θ objective lens. 54 is the position of an alignment pattern provided on the mask 1 for mask alignment.

As can be seen from Figure 2, the signal detection system consists of completely symmetrical left and right systems, the system shown with a dash with the operator side in front of the page is the signal detection system on the right, and the system without a dash is the signal detection system on the left. I'll call you.

Intermediate lenses 32 , 33 , 34 align the origin of vibration from the rotating polygon mirror 28 with the pupil 5 in the aperture position 55 of the objective lens 53 .
Form into 6. Therefore, the laser beam is
The mask and wafer are scanned by the rotation of the wafer.

In addition, in the objective lens system, an objective lens 53, an aperture 55
, the mirror 51 and the prism 52 are movable in the XY directions by a moving means (not shown), and the observation and measurement positions of the mask 1 and wafer 4 can be changed arbitrarily. For example, when moving in the X direction, when the mirror 51 moves in the direction indicated by arrow A in the figure, the objective lens 53 and diaphragm 55 simultaneously move in the A direction, and in order to keep the optical path length constant, the prism 52 also moves in the A direction. 51 movement amounts.

On the other hand, when moving in the Y direction, the entire optical system for observation and position detection moves in the Y direction (direction perpendicular to the plane of the paper).

The scanning beam 61 of the optical path 30a passing through the cylindrical lens 24 forms an angle θ-45° with respect to the scanning axis 60,
In FIG. 3(A), it is almost parallel to marks 71 and 72.75. When scanning in this state, the photodetector 47 shows S7+ and S? as shown in FIG. 3(B). 5, 57
2 signals are obtained. SKI, 875, and 572 are signals corresponding to the alignment marks 71°, 75.72, respectively. Further, even if there is minute dust on the scanning surface, unlike the case of a spot beam, it is averaged and is not practically detected as an output.

On the other hand, the optical path 30b passing through the cylindrical lens 25
The scanning beam 62 is inclined at θ=-45° with respect to the scanning axis 60 to mark the mark 3, 74, and 76, the detection signals are S78, S76, and S? in FIG. 3(b). It becomes 4. Therefore, the detection signal s1. , sflo 1572
+ 5ell + S76, S? By measuring the interval 4, the amount of deviation between the mask and the wafer can be detected, and when they match, the intervals between the detection signals become equal. In addition, the present applicant has published Japanese Patent Application Laid-Open No. 53-90872 or Japanese Patent Application Laid-open No. 53-90872
No. 91754, etc., proposes auto-alignment.

As described above, using FIGS. 2 and 3, the alignment mark 20 on the mask 1 and the alignment mark 2 on the wafer surface are
1, that is, the outline of the mask-to-urchin alignment was explained.

Next, the configuration of the alignment mark position detection circuit of the alignment device according to the embodiment of the present invention will be described.

FIG. 4 is a block diagram of a position detection circuit according to an embodiment of the present invention. 47. 47' is a photodetector that converts the optical signal of the alignment mark already explained into an electrical signal, and 5
8.58' is a photodetector that converts the laser beam scanning the mask and wafer into an electrical signal and detects the scanning timing. 101 is a synchronization detection circuit that binarizes and waveforms the output signals of the photodetectors 58, 58' and outputs a synchronization signal 161 and control signal 103 as shown in FIG. 3 (C1). 102 is an analog is a switch,
A switching operation is performed by the control signal 103, and the output signals from the photodetectors 41 and 47' are combined (FIG. 3(B) shows the output signals from the photodetector 47).

104 is an AD converter, which converts the analog signal level of the analog switch 102 into an 8-bit digital signal at a fixed timing. 105 is an AD converter 10
This is a latch that temporarily stores the digital signal of 4. A timing signal (not shown) for controlling AD converter 104 and latch 105 is output from control/timing generation circuit 114, which will be described later.

150 is an adder with an input A port 8 bits long, an input B port 16 bits long, and an output Y port 16 bits long, which adds the output data (Al) of the latch 105 and the output data (B) of the latch 153, Output to.

152 is a 16-bit x 4 word random access memory, and address and read/write control is provided by the output of the data selector 154 (yo.

y+). The output of the memory 152 is input to the latch 153, and the output of the latch 153 is input to the B port of the adder 150 as described above.

On the other hand, the input and output of the memory 152 are transmitted to the microprocessor (not shown) via buffers 157 and 158, respectively.
data bus 121.

154 is a data selector, and its output signal (R/W
signal, ADR signal) is the output signal (R/W signal, ADR signal) of the control/timing generation circuit 114,
or microprocessor output signals (R/W signals, ADR
The selection is made by the select signal 156 output from the control/timing generation circuit 114.
controlled by Note that the select signal 156 is controlled by a microprocessor.

107 is a data selector, which receives the select signal 10 output from the control/timing generation circuit 114.
8 selects and outputs either the output of the buffer 112 or the output of the latch 153.

Here, buffer 112 is connected to a data path 122 of a microprocessor (not shown). 109 is an 8-bit 24-byte random access memory,
The read/write signal (hereinafter referred to as R/W signal) and address signal (hereinafter referred to as A
DH signal), and the data selector 10
The output data of No. 7 is written to a predetermined address, or the written data within a predetermined address is read. Here, the output signal of the data selector 110 (R/W signal,
ADH code) is control/timing generation circuit 1
14 output signals (R//W signal, ADR signal) or microprocessor output signals (RAW signal, ADR signal) output via address and control path 123, the selection of which is controlled / is controlled by the select signal 111 output from the timing generation circuit 114.

106 is a digital comparator that compares the output data of the launch 105 with the read data of the memory 109 and outputs the result to the control/timing generation circuit 114. The control/timing generation circuit 114 selects the previously described data selector 1 based on the output signal 116 of the digital comparator 108, the synchronization signal 101 of the synchronization detection circuit 100, and the output data signal of the microcomputer provided via the data bus 122.
07, 110, a data selector 117, and a counting circuit 119, which will be described later. The counting circuit 119 is 1
It is a 6-bit counter, and its counting operation is controlled by a clear signal and a count enable signal applied from control/timing generation circuit 114 via signal line 120. 121 is a 16-bit x 24-word random access memory, and data selector 1
17 (R/W signal, ADR signal), the count value of the counting circuit 119 is written to a predetermined address, or the written data within a predetermined address is read. Here, the output signals (R/W signal, ADR signal) of the data selector 117 are the output signals (RAW signal, ADR signal) of the control/timing generation circuit 114, or the microcontroller output signal via the address and control path 123. Processor output signal (R/W signal,
ADR signal), and the selection thereof is controlled by the select signal 118 output from the control/timing generation circuit 114. Further, the outputs of the memories 109 and 121 are output to the data bus 122 via buffers 113 and 115, respectively, so that the microprocessor can read the data from the memories.

Next, the operation of the position detection circuit according to the embodiment of the present invention will be explained with reference to the drawings. FIG. 5(A) is a flowchart showing the control sequence of the microprocessor that controls the position detection circuit of FIG. 4. Also, Figure 5 (
B) is a flowchart for explaining in more detail the state of execution of the first measurement shown in FIG. Similarly, FIG. 5(c) is a flowchart for explaining in detail the execution state of the second measurement shown in FIG. Here,
The first measurement refers to a superimposed addition process of digitized signals, and the second measurement refers to measurement of the pulse interval of the alignment mark detection signal using a reference slice level calculated from the peak value obtained by the first measurement. This will be explained in detail below.

First, the memory 109 is cleared (step 501).

That is, in the microprocessor, the control/timing generation circuit 114 sends the select signal 111 to the data selector 110 and the select signal 108 to the data selector 110.
The signal is controlled to be output to the selector 111. This allows data selector 110 to access the microprocessor's address and control path 123, and data selector 10
7 selects the microprocessor data bus 122 via a buffer. Memory 109 is directly accessed by the microprocessor and all storage areas of memory 109 are written with zeros and cleared.

Similarly, the memory 152 is cleared (step 501).
.

That is, the microprocessor controls the control/timing generation circuit 114 to output the select signal 156 to the data selector 154. This causes data selector 154 to select the microprocessor's address and control path 122. Memory 152 is directly accessed by the microprocessor and all storage areas of memory 152 are cleared by writing zeros.

Next, a first measurement mode is set (step 502).

This setting is the memory 15 connected to the microprocessor.
2 is separated from the control of the microprocessor and operates under the control of the control/timing generation circuit 114. That is, the microprocessor causes the memory 152 to select the output of the latch 151, and the data selector 154 to select the R/W signal and ADR output from the control/timing generation circuit 114.
At this point, the digital comparator 106 and the data selector 107 are connected to the latch 15.
Do not input the output data of step 3.

Once the configuration is complete, the microprocessor will take control/
A first measurement command is issued to the timing generation circuit 114, and measurement is started (step 551). All measurements are performed by hardware under the control/timing generation circuit 114 without the intervention of the microprocessor, and when the measurement is completed, the control/timing generation circuit 114 automatically notifies the microprocessor of the completion.

The addition process operation of the first measurement performed under the control of the control/timing generation circuit 114 will be explained using FIG. 5(B). After the start of measurement 551, an address counter (not shown) for the memory 152 provided in the control/timing generation circuit 114 is cleared in step 560.

Next, when the synchronization signal 101 is detected at 561, 562
At the same time, the data at address 0 of the memory (which is initially cleared, so it is zero) is read, and the AD converter 1
At step 04, the optical signal is digitized using the first sampling signal. These two data are each stored in a latch 105.
, 153 to the adder 150 at the same timing and are added together (step 563). The addition result is written to the memory 152 via the latch 151 (step 564), and the address counter for the memory 152 is incremented by 1 (step 565). The optical signal digitized by the next timing signal is stored at address 1 of the memory 152 according to the instruction of the address counter.

Thereafter, each digital data of the optical signal for one scan is sequentially stored in a predetermined address of the memory 152 by the same operation. This operation continues until the end of the synchronization signal (loop 562→567). The number of words in address 4 of the memory is determined by the period of the synchronization signal and the sampling interval of the AD converter 104 (2), and it is fI that the address advances to address 4095 (4K) before the synchronization signal ends.
stomach.

The scan is repeated up to a predetermined number of times (loop 560→567). The number of scans is determined according to the required accuracy. The relationship between the required accuracy and the number of scans (the two are clarified in Japanese Patent Application No. 57-208765 by the present applicant). When the predetermined number of measurements is completed, in step 568, the control/timing generation circuit 114
generates a termination signal to the microprocessor and ends the measurement. At the end of the measurement, the waveform shown in FIG. 3B is superimposed and added for the number of days of scanning, and is stored as digital data in the memory 152.

Returning again to FIG. 5(A). After the measurement is completed, the microprocessor accesses the memory 152 in step 505 to search for peak data in the memory 152, and then in step 50
6, the slice level is calculated from the peak data, and the slice level data is stored in the memory 1 in step 507.
Write to 52.

Next, the second measurement mode is set (step 508
). This is similar to the setting of the first measurement mode described above, in which the memories 109 and 152 are separated from the control of the microprocessor and are made to operate under the control of the control/timing generation circuit 114. That is, when the settings are completed, the microprocessor instructs the control/timing generation circuit 114 to issue a second measurement command, thereby starting measurement (step 509).

The operation of g 2 i1 measurement will be explained using FIG. 5(c).

When a measurement start command is issued in step 509, the control/timing generation circuit 114 goes to step 531 to detect the rise of the synchronization signal 101, and when detected, starts actual measurement. Furthermore, this command clears the address counter (not shown) for the memory 121 in the control/timing generation circuit 114 (step 53).
0). The second measurement is to successively compare the slice level set in the memory 109 and the added data stored at each address (2) in the memory 152, and measure the timing at which the slice level is passed.

Here, passing through the slice level means that the addition data of the memory 152 (hereinafter referred to as C) outputted via the latch 153 and the slice level data (hereinafter referred to as C) read out from the memory 109 are digitalized for each address. This refers to when the result of comparison by the comparator 108 changes from C≦D→C>D, and when COD→C≦D. In terms of hardware, this means detecting the rising and falling edges of the comparison result signal.

Furthermore, the timing at which the slice level passes can be measured by counting the timing clocks generated within the control/timing generation circuit 114. this is,
The timing clock is counted by the counting circuit 119 using the start point of reading from the memory 152 as the starting point. Therefore, in step 532, if a change in C>D is detected, the control/timing generation circuit 114
generates a write signal to the memory 121 in step 533.

The value written to the memory 121 at this time is the value written to the counting circuit 119.
This corresponds to the time from the time when the memory 152 is read. To explain this with reference to FIG. 3(c), this is the time interval data indicated by T71 in the figure.

(Effects) As described above, according to the embodiment of the present invention, the slice level is automatically determined in accordance with the peak value of the actual alignment mark signal, thereby preventing the alignment mark signal from being overlooked. This has the effect of saving the trouble of manually resetting the slice level.

Furthermore, since the measurement is performed based on the added data, the influence of noise etc. can be removed, the alignment accuracy is improved, and the number of scans for addition can be selected according to the required accuracy, so the work efficiency is improved.

Furthermore, since the optical signal digital data obtained by the addition process and the slice level data are compared in size by hardware, the measurement time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of a positioning apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing an optical system of the positioning apparatus according to an embodiment of the present invention, and FIG. 3 (Bl is a diagram showing the detection signal corresponding to the alignment mark in FIG. 3 (N), and FIG. 4 is a block diagram of the position detection circuit, and FIG. 5 is a flowchart showing the control sequence of the microprocessor that controls the position detection circuit of FIG.
FIG. 5(B) is a flowchart diagram for explaining in detail the execution state of the first measurement shown in FIG. 5(5), and FIG.
) is a flowchart diagram for explaining in detail the execution state of the second measurement. 47.47', 58.58'...Photodetector 10
0...Synchronization detection circuit 102...Analog switch 103...Analog switch control signal 104.
...AD converter 105.151.153...Latch 106...
...Digital comparator 107.110,117
, 154... Data selector 109.121
,152...Memory 112.113,115,
157, 158...Buffer 114...
・Control/timing generation circuit 119...
・Counting circuit 122...Microprocessor data bus 1
23... Microprocessor address bus,
Control path 101...Synchronization signal 103...Analog switch control signal 108.
111, 118, 120, 156...Control signal 116 output from the control/timing generation circuit...Digital comparator output signal 15
0...Adder 1st measurement needle side start 551 Memory 2 Noah 501 Metsu Y Torres 560 111 measurement Clear mo, -to flood 1 14 Kaisho GO-55623 (11) 3912 Measurement

Claims (1)

[Scope of Claims] A device for aligning an object to a predetermined position by optically scanning an alignment pattern provided on the object multiple times, comprising: a photoelectric conversion means for detecting the pattern; and an output of the photoelectric conversion means. digital conversion means for sequentially digitizing signal levels; addition means for adding digitized data obtained by multiple scans in a superimposed manner; storage means for storing added data obtained by said addition means; and said storage. Comprising means for comparing the magnitude relationship between the addition data in the means and the specific data having a predetermined value,
A positioning device characterized by comprising a position detection circuit that measures a button position based on the timing of a signal output from the comparison means.