JPS6053989B2 - Crystal defect compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a crystal defect compensation circuit suitable for use in an image pickup device using a charge transfer device such as a CCD or BBD as an image pickup device, and particularly relates to a crystal defect compensation circuit suitable for use in an image pickup device using a charge transfer device such as a CCD or BBD as an image pickup device. The present invention proposes a crystal defect compensation circuit that prevents deterioration of image quality by removing the defects and is suitable for IC implementation.

If there is a crystal defect in a semiconductor element used as a charge transfer device, the signal in that part will have a large level of noise, so the signal in this part of the crystal defect is generally compensated with a signal 1 bit (one pixel) earlier. I have to.

This is known as a compensation circuit of a prior value hold type, and as shown in Fig. 1, it has an image sensor 1 and a sampling and hold circuit 2, and furthermore, it determines which part of the image sensor 1 has a crystal defect. A control circuit 3 having a memory element in which a defect position signal is stored is provided, and when a defect position signal is obtained, a sampling pulse P is generated in a gate circuit 4.
It is configured such that H is blocked and the sampling hold output of one bit before is held as is. Therefore, this compensation operation may result in an incomplete image after compensation as described below.

For example, in the case of a black and white object as shown in FIG. 2A, if the crystal defect X corresponds exactly to the boundary line, the image after compensation will become as shown in FIG. 2B. This is based on the discrepancy between the delay time of the transmission system before compensation and the delay time of the transmission system after compensation, and now the input of the transmission system before compensation is s. If the output is Sx, then Sx■50... (1) However, during compensation operation, a delay element with a delay time of 1 bit is inserted in the signal transmission system. Since they are equivalent, the output SY at this time is due to the presence of this quadratic component Exp (-jωτ) contained in the output SY,
A delay time difference of 112 bits occurs between the outputs Sx and SY.

This time difference results in an incomplete compensation screen as described above. Therefore, in the present invention, the above-described time difference is prevented from occurring to prevent deterioration of image quality due to image distortion. That is, in the present invention, the bit signal obtained from the crystal defect position is determined by the average value signal of the bit signals obtained from each bit before and after the crystal defect position, or by two signals adjacent to the horizontal line where the crystal defect exists. Interpolation is performed using the average value signal of the bit signals obtained from the bits corresponding to the crystal defect position of the horizontal line. In order to do this, it is necessary to use a normally used bit signal that is delayed by a predetermined amount of time; in this case, the delay time is equal to the delay time of the average value signal used when there is a crystal defect. , the above objectives can be achieved.

If such a delay time is taken into consideration, a configuration as shown in FIG. 3 can be adopted.

5 is a first delay circuit, which in this example outputs the original output, that is, the original bit signal S;

is output after being delayed by one bit. This output is defined as the first bit signal S1. A second delay circuit 6 outputs a second bit signal S2 obtained by delaying the original bit signal SO by two bits.

The second bit signal S2 and the original bit signal S.

are synthesized by the synthesizer 7, and the synthesized output . (
SO+S2) is supplied to a weighting variable resistor 8 and averaged. Reference numeral 9 denotes a switching circuit whose switching is controlled by a control pulse Pc from the control circuit 3.

Therefore, the original bit signal S.

As shown in Figure 4A. Considering the bit output A2 and A4
If it is assumed that the bit output (marked with X) that spans is the bit output due to a crystal defect, the first bit signal S1 is
Since the second bit signal S2 is as shown in C in the figure, the average value signal S3 is as shown in D in the figure. Here, if there is no crystal defect, the first bit signal S1 is used as the final composite bit signal ST.

Therefore, as shown in FIG. Due to the switching, the composite bit signal S, becomes as shown in FIG. That is, in the section where a crystal defect exists, instead of this crystal defect output, an average value signal S3 obtained by averaging the bit outputs A2 and a4 before and after this crystal defect bit is output, so that the crystal defect position is compensated for. be able to. Now, since the delay time of the first delay circuit 5 is k, which is γ, the first and second bit signals Sl
A, S2 is . Become VJW-Wano.

Therefore, in the average value signal S3, COsωT is the amplitude component, and the phase component is exactly the same as in equation (3).

That is, the delay time of the average value signal S3 in equation (5) is the first
The bit signal is delayed by exactly the same amount of time whether it passes through the transmission system including the first delay circuit 5 or the transmission system including the average value circuit 10. I will do it. Therefore, even if the imaging state is exactly the same as that shown in FIG. 2A, the compensation screen as shown in FIG. 2B will not be obtained. In this way, when compensating for crystal defects,
By interpolating using the signals of successive bits as described above, even in the case of Fig. 2 A, the interpolation is performed at the average level of white and black, and the limbus as shown in Fig. B does not occur. .

In other words, it becomes a smooth limbus. By the way, in the conventional example shown in FIG. 3, its configuration is not suitable for IC implementation. When a conventional circuit as shown in Fig. 3 is integrated into a single chip, a third circuit is placed on the same substrate as that for the image sensor.
This is because it is necessary to configure a circuit as shown in the figure, and in this case, the switching circuit 9 is not suitable for IC implementation due to reasons such as the inability to obtain a sufficiently high-speed switching circuit 9.

Therefore, in addition to the above-mentioned object, the present invention proposes a crystal defect compensation circuit suitable for IC implementation.

FIG. 5 is a system diagram showing the principle configuration of an example,
Three switching circuits SWa-SW for the output signal path
c are connected in parallel, and weighting variable resistors 12 and 13 are connected to the output sides of the second and third switching circuits SWb and SWc.

Then, it passes through the second switching circuit SWb and 1/
The second bit signal Sb weighted by 2 is delayed by one bit in the first delay circuit 15, and its delayed output is combined with the first bit signal Sa passed through the first switching circuit SWa. is supplied to the vessel 16.

This combined output is further delayed by 1 bit in the second delay circuit 17, passes through the third switching circuit μSWc, and is supplied to the combiner 18 together with the third combined bit signal Sc weighted with 112. From this, the desired final composite bit signal ST is obtained. In addition,
In FIG. 5, Sa'' and Sb'' are delayed outputs of the first and second bit signals Sa and Sb. Now, image sensor 1
The bit signal S from . is as shown in FIG. 6A, and the bit output (
When the signal (X mark) is crystal defect noise, the control circuit 3 outputs switching pulses PA, PB,
It is assumed that the PC is output. Therefore, the first bit signal Sa becomes O only when the bit output corresponds to the crystal defect position, and the second and third bit signals Sb and Sc become O only when the bit outputs are A4 and a6. Since the switching circuits SWb and SWc are turned on, the outputs are as shown in F and G in the figure.

And, due to the presence of the first and second delay circuits 15 and 17,
First bit signal Sa″ delayed by 1 bit (H in the same figure)
and the second bit signal Sb″ delayed by 2 bits (Fig. 1
) are obtained, these bit signals Sa″, Sb″
By simply synthesizing and the third bit signal Sc, a composite bit signal as shown in J in the figure is obtained, in which the signal of the crystal defect part is interpolated by the average value signal (ν(A4+A6)) of the bit output A4 and ~. ST will be obtained. The configuration shown in FIG. 5 is converted into an IC as shown in FIG.

That is, FIG. 7 is a block diagram showing an example of the crystal defect compensation circuit according to the present invention, where SR is a charge transfer type shift register, and when the image sensor 1 is a CCD, the structure of the charge transfer is the same as that of the CCD. Made of the same structure.

Then, with this one shift register SR, the delay circuit 15
, 17 and the functions of combiners 16 and 18 are provided. Also,
This shift register SR is configured as a 3-bit shift register.

A circuit corresponding to the final stage shift register SR3 corresponding to the third bit is located on the output side of the synthesizer 18 in FIG. 5, but is not shown in FIG.

As shown in the figure, this shift register SR is driven by two-phase clocks φ1 and φ2, and regions C1 to C3 are charge regions and T1 to T3 are transfer regions.
An input circuit 20 is provided in each charge region C1 to C3 of each register SRl, SR2, and SR3 for 3 bits.

That is, as shown in the figure, an input circuit 20 is formed by input source sections h1 to H3 and input gate sections G1 to G3, and input source sections h1 to h1. has a bit signal S
. is commonly supplied. And input gate section G
1 to G3 are control input gates G and a as shown in the figure.
-G3a and ■input gates Gl, ~G3b, and the control input gate Gla-G3a has a fifth
The control pulses PA-PO shown in the figure are supplied,
Bit signal S. control is performed. Therefore, these control input gates Gla-G38 correspond to switching circuits SWa-SWc in FIG. 5. and,
Bit signal S.

In this example, the channel regions of the input gate sections G1 to G3 are used to weight the input gates G1 to G3.
That is, the channel width C2 of the input gate section G2
On the other hand, the channel widths Cl and C3 of the other input gate sections G1 and G3 are selected to be 1/2 of that width. Therefore, the area of the channel stopper of the input gate portions Gl and G3 may be expanded by the amount of weighting. In this way, the first bit signal Sa is sent from the input gate section G2, the second bit signal Sb is sent from the input gate section G1, and the third bit signal Sa is sent from the input O gate section G3.
A bit signal Sc of 1 is obtained. When the first bit signal Sa is transferred to the register SR3, the register S
This is delayed by one bit due to the presence of R2, and when the second bit signal Sb is transferred to register SR3, register S
Since this is delayed by 2 bits due to the presence of Rl and SR2, by supplying the third bit signal Sc to this final stage register SR3, a composite bit signal ST similar to that described above can be obtained.

In addition, 30 is the output circuit, 0G is the output gate,
0D is the output diffusion region.

In addition, Tp is a precharge MOS-FET operated by a precharge pulse Pp, and TO is an output MOSFET.
It is an S-FET. As explained above, according to the present invention, the delay time of the transmission system before compensating for crystal defect noise can be made equal to the delay time of the transmission system when compensating for crystal defect noise. Since interpolation is performed using an averaged signal, it is possible to obtain a natural compensation screen.

Therefore, deterioration in image quality due to image distortion can be prevented. The principle configuration shown in FIG. 5 uses a charge transfer element as the shift register SR.
As shown in FIG. 7, it can be extremely easily integrated into an IC.

Furthermore, when using a charge transfer type shift register SR, input addition, weighting, etc. can be realized extremely easily, so there is no need to provide an external addition circuit or a 1/2 gain control circuit. Mean value interpolation can be realized with a simple configuration, and a crystal defect compensation circuit that is extremely suitable for IC implementation can be realized. In other words, when converting a conventional circuit as shown in FIG. 3 into an IC on one chip, a substrate for an image sensor! It is necessary to construct a circuit as shown in FIG. 3 on the same board as the switching circuit 9, and in this case, it is not suitable for IC implementation because the switching circuit 9 cannot be fast enough. This is also because the above objective must be achieved by an external circuit.

In addition, since the clock used for a solid-state image sensor (CCD imager) can be used as the drive clock for the shift register SR, there is no need to provide a drive clock generation source for the shift register SR, which simplifies the circuit configuration. It has the characteristics of being able to

Note that in the embodiment described above, crystal defect noise is interpolated using the average value signal of successive bit outputs;
The same effect as described above can be obtained even if interpolation is performed using the average value signal of bit signals obtained from bits at the same position in two horizontal lines adjacent to the horizontal line in which the crystal defect exists.

In this case, since the delay circuits 15 and 17 are selected to have a delay time of 1H, what about the shift register SR? is the amount of delay.

[Brief explanation of the drawing]

Figure 1 is a system diagram showing a conventional example of a crystal defect compensation circuit;
FIG. 3 is a system diagram showing another example of the conventional circuit; FIG. 4 is a diagram explaining the operation;
FIG. 5 is a system diagram showing the principle configuration of the present invention, FIG. 6 is a diagram for explaining its operation, and FIG. 7 is a diagram showing an example of the crystal defect compensation circuit according to the present invention, showing the specific configuration of FIG. It is an explanatory diagram. 1 is an image sensor, 3 is a control circuit, 5, 6, 15, 17 are delay circuits, 10 is an average value circuit, SR is a shift register, G
1 to G3 are input gate sections.

Claims (1)

[Claims] 1 A bit signal obtained from a crystal defect position of a solid-state imaging device in which semiconductor elements are arranged horizontally and vertically in a matrix pattern is calculated as the average value of the bit signals obtained from each bit horizontally before and after this crystal defect position. In a crystal defect compensation circuit for a solid-state imaging device, the crystal defect compensation circuit of a solid-state imaging device performs interpolation using a signal or an average value signal of bit signals corresponding to the crystal defect position of two horizontal lines adjacent to the horizontal line with the crystal defect, The output signal from the solid-state imaging device is
, are supplied in parallel to three different first, second and third delay positions of the charge transfer type shift resist through second and third input gates, and each of the delay positions is connected to the first, second and third delay positions of the charge transfer type shift resist. 2,
The delay amount is made smaller in the third order, and the channel width of the first and third input gates is set to be approximately 1/2 of the channel width of the second input gate, so that the solid-state imaging device The first, second and third input gates are controlled according to the crystal defect position information, and normally the output signal of the second input gate is output, and where there is a crystal defect, the first and third input gates are controlled. A crystal defect compensation circuit for a solid-state imaging device is configured to output an average value of outputs from three input gates.