JPS6053972B2 - Digital signal transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for storing data on tape and disk with a limited number of bits. A digital signal transmission method that transmits digital signals through networks, etc., which compresses digital signals effectively using a simple device with the minimum number of bits by appropriately varying the transmission bits of the digital signal based on predictions based on past values. The purpose of the present invention is to provide a digital 5-signal transmission system that can be transmitted using the following methods.

The present applicant previously proposed in Japanese Patent Publication No. 59-53585 (Japanese Patent Application No. 54-163858) that a differential pulse code modulation (DPCM) signal transmitted with a certain limited number of bits is used as an input differential signal. We have proposed a PCM signal transmission system that can reduce gradient overload noise and granular noise specific to DPCM signals by bit-shifting the input difference signal t according to the level. D, which is the applicant's proposal
In the PCM signal transmission system, the configuration of the signal prediction circuit consists of a signal obtained by taking the absolute value of the input difference signal, this absolute value circuit output signal, and a signal obtained by delaying this signal by one sampling period or more of the input. A predicted signal is obtained by adding the difference signals obtained by calculating the difference between the two, and this predicted signal is supplied to the first and second comparators, where each of the upper limit level setter and lower limit level setter is At least one bit or more of a shift register is specified, which compresses and outputs the input difference signal only when the analog conversion level of the predicted signal exceeds the set level/range of the upper limit level at that time by comparing with the output reference level. In addition to generating a shift pulse for shifting in the direction, the upper limit level and the lower limit level are respectively changed so that the analog equivalent level of the predicted signal falls within the set level range. However, according to the method proposed by the applicant above,
If the above setting level range is large and the analog equivalent level of the input digital signal becomes extremely low,
Alternatively, the reference upper and lower limit levels cannot be changed unless they become extremely high, and therefore the transmission bits of the digital signal that is compressed and transmitted/received are not effectively used, and there is a risk that distortion may increase. It was hot.

In addition, in the method proposed by the present applicant, the input digital signal before compression is passed through an absolute value circuit on the transmitting side, and the output digital signal A difference signal is obtained from the above, and a predicted signal is obtained by adding this difference signal and the output digital signal Xn of the absolute value circuit, respectively, and the predicted signal is obtained on the receiving side in the same manner as on the transmitting side.
As shown in the table below, there may be a difference between the predicted signals on the transmitting side and the receiving side.

The above table is an example of compressing a 10-bit input digital signal Art'
→01nnn↓Na~Ria i→S▼L nanny 1 is here.

This is because the signal prediction circuit on the receiving side generates a prediction signal from the transmission signal itself, but in such a case, there is a problem that it has a slight but negative effect on effective bit transmission and reception. The present invention solves the above-mentioned problems, and each embodiment thereof will be described below with reference to the drawings. FIG. 1 is a block system diagram of an embodiment of a transmitting system of a digital signal transmission system according to the present invention, and FIG. 2 is a block system diagram of an embodiment of a receiving system of the system of the present invention.

In FIG. 1, the circuit section indicated by a broken line 3 is a signal prediction circuit that forms the main part of the method of the present invention. Digital signal with n bits of value (e.g. PCM signal)
is supplied to the shift register section 4 in the signal prediction circuit 3. The shift register section 4 performs a shift operation in a predetermined direction based on the output of the comparator 10 as will be described later, compresses the input n-bit digital signal into an m-bit digital signal, and transmits it to the receiving system shown in the second diagram. On the other hand, it is supplied to the absolute value circuit 5 in the signal prediction circuit 3 (where m<
It is n. ). That is, the input signal to the absolute value circuit 5 is an m-bit digital signal output from the shift register section 4. The m-bit digital signal whose absolute value has been taken and extracted by the absolute value circuit 5 is supplied to a difference unit 7 and also to a delay unit 6, where it is sampled when sampled by the AD converter 2. After being delayed for a time equal to the period, the signal is supplied to the differentiator 7. The differentiator 7 is an arithmetic circuit that calculates the difference between the m-bit digital signal output from the absolute value circuit 5 and the m-bit digital signal output one sample before the delay device 6, and outputs the output m-bit difference signal to the gain controller 8. do.

The gain controller 8 is for applying an appropriate weighting coefficient so that the distortion component in the final demodulated output is minimized, and may be configured by a multiplier and a coefficient unit. The m-bit difference signal output from the gain controller 8 is added to the m-bit difference signal output from the absolute value circuit 5 in an adder 9, and is used as a predicted signal of the m-bit digital signal.

That is, in FIG. 3, from the absolute value circuit 5 to the adder 9
If the m-bit digital signal supplied to
2. Assuming that the level changes as shown by the solid arrow at t3, the output difference signal of the differentiator 7 at time T2 is the digital signal between time T2 and time t1, which is one sampling period T earlier. This difference results in a differential signal representing the level shown as d in FIG.
By adding the m-bit digital signal outputted from the absolute value circuit 8 at the time interval by the adder 9 through the time interval, the digital signal representing the level information shown by the broken line arrow in FIG. Time as a predicted signal that is predicted to be output! It can be obtained with That is, the analog conversion value of the output digital signal of the differentiator 7 is P
Let n be expressed as. Therefore, this analog conversion value PO becomes the differential coefficient of the difference signal. Therefore, the analog conversion value P″n+1 of the predicted signal is as follows.

However, in equation (2), α is a weighting coefficient given by the gain controller 8. The predicted signal obtained as described above is applied to the comparator 10, where the analog conversion level is compared with the reference level at the current time from the reference level setter 11.

As a result, the comparator 10 outputs a logic ゜゜1゛ signal when the analog conversion level of the predicted signal is higher than the reference level.
M in the shift register section 4 as an example of a bit selection circuit.
It is applied to shift in the SB direction J (leftward), and on the other hand, when the analog conversion level of the prediction signal is smaller than the reference level, a signal of logic 46-r' is applied to the shift register section 4 to shift it to the LSB. direction (rightward). Furthermore, the comparator 10 causes the shift register section 4 to perform the above shift operation, and at the same time, when the output of the comparator 10 is at logic ゜゛1゛, the output of the reference level setter 10 is set to 6. ~12C1B is changed to a higher reference level, and the delay device 6 is made to perform the same shift operation as the shift register section 4. On the other hand, when the logic "゜-1゛" is output, the reference level is changed from that at the current time. The reference level is also changed to a level 6 to 12 dB lower, and the delay device 6 is caused to perform the same shifting operation as the shift register section 4.

The reason why the delay device 6 is caused to perform the same shift operation as the shift register section 4 is to obtain a correct difference signal in the difference device 7. Shifting operation of the shift register section 4 and delay device 6 based on the output of the comparator 10 and reference level setting device 1
The setting change operation of the reference level 1 takes 1 sampling period T.
The input n-bit digital signal at the time predicted by the prediction signal is transmitted, with m bits selected based on the prediction signal.

In cases other than the above (for example, after changing the reference level), the comparator 10 outputs a logic 0 signal and does not operate any other circuits. A digital signal transmitted via a transmission path such as a tape or a disk is applied to a signal prediction circuit 13 via a register 12 shown in FIG. 2.The signal prediction circuit 13 has the same configuration as the signal prediction circuit 3 or 30 described later. However, the input signal of the absolute value circuit is an input m-bit digital signal of the shift register section, and the shift register section and the delay device are configured to shift in the opposite direction to the signal prediction circuit 3 or 30. As a result, the output n-bit digital signal of the signal prediction circuit 13 is equivalent to the input n-bit digital signal of the shift register section 4, and this digital signal is converted from digital to analog by the DA converter 14 shown in FIG. After the conversion, the signal is outputted from the output terminal 15. Fig. 4 shows a block system diagram of the transmission system of another embodiment of the system of the present invention.

In the figure, the configuration is the same as in Figure 1! The parts are given the same symbols,
The explanation will be omitted. In this embodiment, comparators 26 and 27 are provided, and when the analog equivalent level of the predicted signal is higher than the reference level determined by the reference level setter 28, the comparator 26 moves the contents of the shift register delay device 6 in a predetermined direction. On the other hand, the reference level from the shift register 29 obtained by shifting the output of the reference level setter 28 to the right by 1 or 2 bits (therefore, this is the output of the reference level setter 28). When the analog equivalent level of the predicted signal is lower than the output reference level (6 dB or 12 dB lower than the output reference level), the comparator 27 outputs a pulse to shift the contents of the shift register delay device 6 in a predetermined direction. The reference level setting range in which the shift register section 4 and delay device 6 are not shifted is α.
This uses a signal prediction circuit 30 that is extremely small at B or 12 dB. That is, the predicted signal taken out from the adder 9 is supplied to comparators 26 and 27, respectively, where the level is compared with the output reference setting level of the reference level setter 28 and shift register 29.

The comparator 26 sends data to the left to the shift register section 4 by, for example, 1 only when the analog conversion level of the output prediction signal of the adder 9 is higher than the output reference level (upper limit level) of the reference level setter 28. A shift pulse for bit shifting is output, and the upper limit reference level set by the reference level setter 28 is increased by a certain level. This results in
The output reference level of the shift register 29 also increases by the above-mentioned fixed level. The above operation is repeated until the analog conversion level of the predicted signal becomes smaller than the output upper limit reference level of the reference level setter 28, and is always performed within the time (one sampling period) until the next analog signal arrives. Configured to complete. Similarly, the comparator 27 causes the shift register section 4 to shift the data by 1 bit to the right only when the analog conversion level of the predicted signal is lower than the set reference level (lower limit level) of the shift register 29. At the same time as outputting the shift register, the set reference level of the reference level setter 28 is decreased by a certain level.

Along with this, the output reference level of the shift register 29 also decreases by the above-mentioned constant level. The above operation is repeated until the analog conversion level of the predicted signal becomes higher than the output lower limit reference level of the shift register 29, and the shift pulse is repeatedly output. Here, shift register section 4
is a circuit that outputs a digital signal of m bits (m<n), and a leftward shift pulse can represent a large level signal in m bits, and a rightward shift pulse can represent a small level signal in m bits. It can be expressed as The comparators 26, 27, reference level setter 28, and shift register described above constitute a control circuit.

FIG. 5 is a diagram for explaining the operations of the comparators 26, 27, the reference level setter 28, and the shift register 29. The solid line arrow indicates the analog conversion level of the output signal of the absolute value circuit 5, and the broken line arrow indicates the analog conversion level of the predicted signal obtained at that time (hereinafter abbreviated as predicted signal level),
Furthermore, a dashed-dotted line I shows the upper limit reference level set by the reference level setter 28, and a dashed-dotted line ■ shows the lower limit reference level set by the shift register 29, respectively. As shown in Figure 1, Time Pig! Since the predicted signal level at time T3 obtained at 1t2 exceeds the upper limit level I, the upper limit level I and lower limit level ■ are adjusted so that the upper limit level I becomes higher than the predicted signal level at time T3 by the next time T3. were raised to the same level, and the predicted signal level at time T6 became smaller than the lower limit level ■ at time T6. Therefore, the upper limit level I is set so that the lower limit level ■ becomes lower than the predicted signal level by the next time T6. and the lower limit level ■ are respectively lowered to the same level,
Furthermore, at time TlO, the predicted signal level at time Tll exceeds the upper limit level I, so the upper limit level I and the lower limit level ■ are raised to the same level so that it becomes higher than the predicted signal level by the next time Tll. . For convenience of illustration, Figure 3 shows the time! The analog conversion level of the predicted signal at time ζ obtained at time ζ is illustrated at the following times.
In the figure, the analog conversion level of the predicted signal at time Tn+1 obtained at time Tn is indicated by that time Tn. Further, the reason why the upper limit level I and the lower limit level (2) are respectively raised or lowered by the same level is that the number of bits of the digital signal to be transmitted is constant. According to this embodiment as described above, the input digital signal is bit-shifted based on its predicted signal, and furthermore, the bit shift of the signal can be performed by the maximum number of bits n of the input digital signal, compared to the conventional method. Although the method could only quantize the number of transmission bits m, it is now possible to quantize n stages larger than m, and the input analog signal can be accurately transmitted as a digital signal.

In addition, when the level change of the analog signal is large, bits are transmitted upward from the input n-bit digital signal from the shift register section 4, so a large dynamic range can be obtained. Since the lower bits of the n-bit digital signal are transmitted, the input signal can be transmitted with minimum quantization.
Furthermore, the above prediction signal is generated from the output of the shift register section 4 in the transmission system, and from the input of the shift register section in the signal prediction circuit 13 in the reception system, and the reference level setting range is zero or extremely low. Therefore, the difference between the transmission and reception system of the predicted signal is extremely small compared to the transmission system proposed by the applicant, and the transmission bits can be effectively used to transmit digital signals with little distortion.

In the above embodiment, the difference device 7 obtains the difference between the digital signal at the current time and the digital signal one sample ago, but the difference is not limited to this. For example, the difference between the digital signal at the current time and the digital signal one sample before Digital signal Dn and digit one sample before two samples Dn+Dn-1
signal D.

−, and the average value (complete) may be obtained. Also,
A random access memory (RAM) capable of storing a plurality of sampled signals is used as the absolute value circuit 5, and a second adder is provided on the output side of the adder 9, and the output of this second adder is connected to the output side of the adder 9. A shift register may be provided to temporarily store and feed back the output to the second adder, and the output prediction signal of the second adder may be supplied to the comparator 10 or 26, 27. .

At this time, the output prediction signal of the second adder is increased to the above R. The output digital signal of AM is Xe, from which k
If the output digital signal of the RAM before sampling is expressed as Xe-1, then a predicted signal expressed as Xe-1 may be output. As described above, the digital signal transmission system according to the present invention includes a bit selection circuit which is supplied with an n-bit digital signal and selects m bits from the n-bit digital signal as a transmission output, and a digital signal output from the bit selection circuit which is input. An absolute value circuit that receives a signal, calculates its absolute value, and outputs it; and a difference circuit that outputs a difference signal corresponding to the difference between the current time signal and a signal at least one sample earlier among the output signals of the absolute value circuit. a gain controller that multiplies the output difference signal of the difference circuit means by a constant weighting coefficient; and an adder that obtains a predicted signal by adding the output signal of the gain controller and the output signal of the absolute value circuit, respectively; A reference level setter that outputs the reference level at the current time compares the analog conversion level of the predicted signal with the reference level at the current time,
When the analog conversion level of the predicted signal is higher than the reference level at the current time, the reference level is changed to a higher level, and the bit selection portion by the bit selection circuit is shifted to the left, and the level is higher than the reference level at the current time. When the signal is small, the reference level is changed to small, and a comparator that shifts the bit selection part to the right constitutes a transmission system, and an m-bit digital signal is supplied via the transmission path, and this is sent to the transmission system. A circuit similar to that of the transmission system, consisting of a bit selection circuit similar to the above, an absolute value circuit to which the input digital signal of the bit selection circuit is supplied, a difference circuit means, a gain controller, an adder, a reference level setter, and a comparator. a signal prediction circuit that obtains a demodulated digital signal by performing a shift control operation opposite to the control operation by the comparator of the transmission system on a bit selection circuit of the reception system to which the m-bit digital signal is supplied; Since the receiving system is configured with a circuit that demodulates the output signal of the signal prediction circuit into the original analog signal, the selection of transmission bits of the digital signal according to the analog conversion level of the input n-bit digital signal is compared to the method proposed by the applicant. Moreover, the prediction signal is generated by the transmitting system from the m-bit digital signal being transmitted, and by the receiving system from the m-bit digital signal that has entered through the transmission path, so the transmitting system and the receiving system are It is possible to reduce the difference between the predicted signals that may occur in the system, and also to compare the analog converted level of the predicted signal with the reference level at the current time and set a preset upper limit reference level. When the level exceeds the set level range between and the lower reference level. A shift pulse is generated to shift the bit selection portion by the bit selection circuit in a predetermined direction in accordance with the direction in which the bit selection circuit exceeds the threshold, and the reference level is changed to a level in which the analog conversion level of the prediction signal is higher than the preset upper limit reference level. The configuration of the control circuit that changes the reference level so that the reference level becomes higher when the time is lower than the preset lower limit reference level, and becomes lower when the reference level is lower than the preset lower limit reference level is simpler than the method previously proposed by the applicant. In addition, it is possible to perform quantization with a number of steps larger than the number of transmission bits, maintain signal performance that greatly exceeds compressed transmission bits (twice as much), and generate a predicted signal from the digital signal, based on which Since the bits are selected, there is no need to separately transmit a control signal for bit number compression/expansion identification, and the transmitted bits can be used effectively. A signal prediction circuit can be configured with simple logic, and weighting of the prediction is easy. Some have features such as being variable.

[Brief explanation of the drawing]

Fig. 1 is a block system diagram showing a transmitting system according to a first embodiment of the present invention system, Fig. 2 is a block system diagram showing an embodiment of a receiving system according to the present invention system, and Fig. 3 is a prediction signal generation method. FIG. 4 is a block system diagram showing the transmission system of the second embodiment of the method of the present invention, and FIG. 5 schematically shows signal level changes for explaining the operation of the main parts of the method of the present invention. It is a diagram. 1... Analog signal input terminal, 3, 13, 30...
Signal prediction circuit, 4... Shift register section, 5... Absolute value circuit, 6... Delay device, 7... Differentiator, 9...
Adder, 10, 26, 27... Comparator, 11, 28...
...Reference level setter, 29...Shift register.

Claims (1)

[Claims] 1. A digital device that selects and transmits m (m<n) bits from an n-bit digital signal obtained by digitally modulating an analog signal, and receives the selected bits to obtain the original analog signal. The signal transmission system includes a bit selection circuit which is supplied with the above-mentioned n-bit digital signal and selects m bits from it as a transmission output, and a bit selection circuit which receives the digital signal outputted from the bit selection circuit as an input signal and calculates its absolute value. an absolute value circuit that outputs an output signal, a difference circuit means that generates and outputs a difference signal corresponding to a difference between a signal at a current time and a signal at least one sample or more earlier among output signals of the absolute value circuit; a gain controller for multiplying the output difference signal of the means by a constant weighting coefficient; an adder for obtaining a prediction signal by adding the output signal of the gain controller and the output signal of the absolute value circuit; A reference level setter that outputs a reference level compares the analog conversion level of the predicted signal with the reference level at the current time, and when the analog conversion level of the predicted signal is greater than the reference level at the current time. changes the reference level to a high value and shifts the bit selection portion by the bit selection circuit to the left, and when it is smaller than the reference level at the current time, changes the reference level to a small value and shifts the bit selection portion by the bit selection circuit to the left. A transmitting system is configured with a comparator that shifts the value to the right, and is supplied with an m-bit digital signal via a transmission path, which is then input to a bit selection circuit similar to the above-mentioned transmission system, and the input digital signal of the bit selection circuit is The bits of the receiving system to which the m-bit digital signal is supplied has a circuit configuration similar to that of the transmitting system, consisting of an absolute value circuit, a differential circuit means, a gain controller, an adder, a reference level setter, and a comparator. a signal prediction circuit that obtains a demodulated digital signal by performing a shift control operation on the selection circuit that is opposite to the control operation by the comparator of the transmission system; and a circuit that demodulates the output signal of the signal prediction circuit into an original analog signal. A digital signal transmission method characterized by having a receiving system configured with 2. In a digital signal transmission method in which m (m<n) bits are selected and transmitted from an n-bit digital signal obtained by digitally modulating an analog signal, and the original analog signal is obtained by receiving this, A bit selection circuit that is supplied with an n-bit digital signal and selects m bits from it as a transmission output, and an absolute value that receives the digital signal output from the bit selection circuit as an input signal and calculates its absolute value and outputs it. circuit, a difference circuit means for generating and outputting a difference signal corresponding to the difference between the current time signal and a signal at least one sample or more ago among the output signals of the absolute value circuit, and a difference signal output from the difference circuit means. a gain controller for multiplying by a constant weighting coefficient; an adder for obtaining a predicted signal by adding the output signal of the gain controller and the output signal of the absolute value circuit; Only when the level exceeds the set level range between the preset upper limit reference level and lower limit reference level by comparing the magnitude with the reference level of the time, the bit selection portion by the bit selection circuit is moved in a predetermined direction according to the direction of the exceedance. At the same time, the reference level is set so that the analog conversion level of the predicted signal is greater than the preset upper limit reference level, and is smaller than the preset lower limit reference level. A transmission system is configured with a control circuit that changes the reference level so that the reference level becomes smaller than the current value, and an m-bit digital signal is supplied via a transmission path, and a bit selection circuit similar to the above transmission system selects the bit. absolute value circuit, differential circuit means to which the input digital signal of the selection circuit is supplied;
The control operation by the control circuit of the transmission system is opposite to the bit selection circuit of the reception system to which the m-bit digital signal is supplied, which has the same circuit configuration as the transmission system and includes a gain controller, an adder, and a control circuit. A digital signal transmission system characterized in that a receiving system is constituted by a signal prediction circuit that performs a shift control operation to obtain a demodulated digital signal, and a circuit that demodulates the output signal of the signal prediction circuit into an original analog signal.