JPS6052453B2 - Process control blocks for computer systems - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to computer systems, and more particularly, to computer systems in multiprogramming/intensive processing situations. The present invention relates to systems and methods for controlling data processes.

Fourth generation systems can meet the following requirements:

1 The system is classified as a communication and control system.

2 The system, like previous machines, is primarily controlled by data rather than by programs.

3 Hardware controls communication and control procedures: The use of system control programs is substantially reduced or eliminated.

4 Most processing is performed in real time; operations are performed on inputs at a rate that provides output within the required response time.

5. The system scales easily.

Hardware 1 Air and software are functional modules in design. Processing in first generation hardware/software computer systems was relatively simple.

There, the job or program was considered the basic processing unit. For jobs or transactions initiated by each user, the program typically
until the job or transaction is completed.
Progressed with little or no interruption. In editing and running advanced language programs, many of the simple jobs, such as Fortran, could and did proceed as a single process. However, the more difficult job is
It required multi-tasking operations and typically spawned other processes as it progressed. (Note that a process is a concept that refers to the progression of some activity, and should not be confused with the concept of a program. A program is a description of an activity, used by one or more processes.) When we run a program, we can speak of either a process or a processor.The concept of a process, a basic processing unit,
It was developed to meet the needs of the multiprogramming/intensive processing situations of third generation computers.

In such a situation, where many users request services at the same time, it is natural to imagine multiple processes competing for resources within a computer system.

Each process is a program executed by a computer that operates on data and performs a user's job or some stage of that job (i.e., an organized collection of instructions and other data associated with the instructions). When many such processes demand simultaneous attention from the system, communication tasks with and among the processes, and especially because of the requirements of fourth generation systems, control and control resources. The task that allocates to the process is
It's getting extremely complicated. Burroughs B-6500 and B-7500 computers are referred to as “Burroughs B-650
0/B-7500 Deposition Mechanism, Procedure. AFIPS Spring Joint Computer Meeting. 1968 pages 245-25
1. E. Thompson, Washington Tech. A. Houchi and B. A. Also discussed in the article by Dent, entitled "Process Handling of the Burrows B-650 Call Order. Fourth Australian Computer Conference. Adalid, South Australia, 1969", J. G
．． Discussed in the article by Cleary, the use of deposition mechanisms provides some method of process control.

Essentially, "Each process is a memory selected for storage in which local variables, collations of program steps, data arrays, and current process state are stored... ... Deposition acts outside the storage area, initially in minimal amounts ... Active processes are represented by active deposition.'' (J
．． G. Cleary supra pages 231-232), therefore:
Deposit has the ability to store the dynamic history of a running program. AJ., presented at the ACM Second Symposium on Operating Systems (pp. 60-70, 1969). Bernstein, G. D. Detlefsen, and R. H. The paper entitled 66 Process Control and Communication 1 by Gell describes the structure of processes and interprocess communication facilities implemented within a general purpose operating system. Depending on the system, a single process is made up of up to four parts called its logical segments.These segments are located in physically separate locations when the process is stored. Relocation and protection of these segments is accomplished by four registers.
Generally, processes are controlled through the use of an operating system that implements the native language (ie, pseudo-instructions) issued by the processes, and the mechanisms by which the processes communicate with each other.

First, communication involves shared events in the same way that shared events share files. Each process points to the same AIT (Activity Item Table) containing unique entries for each currently open file.
It has an IT (known item table) entry. With this structure, one process may need to know (by uttering the NOrIFY word) when an event will occur. As a result, the operating system creates an entry on the event queue associated with the event identifying the requesting process having the notification. At this point, the request process may continue to perform or may be interrupted by issuing a BLOCK message.
This event causes some other process to use CAU for the event.
It is said to occur when an SE source word is uttered and can be cataloged and processed in a command mechanism that uses the same source language. Information can then be transferred from one process to another or to processes that otherwise cooperate in performing a certain task. Other languages in operating systems create or give birth to processes, or destroy them. Although this technique of process communication and control does not provide an ordered dynamic history of a running program, it does introduce some concepts of software multiplexing of process and event management.

This technique does not provide for protection of processes from one process to another with privileges. This technique also does not provide an effective way to send process messages from one side to the other. Additionally, address processing and relocation appear to be inadequate in fourth generation systems. What is needed for a fourth generation system is a firmware/hardware system that provides information mechanisms to effectively address, relocate, and ascertain the L states of processes, and that also provides control over these states. It is also a firmware/hardware system that provides an information mechanism that supports a process for protection from other processes and itself through privileges, and that effectively dispatches a process and prevents it from occurring simultaneously with other processes. , is also a firmware/hardware system that allows a user who has created a program in a modular manner to proceed from one program module to another. It is another object of the present invention to provide a system and method for process control that reduces operating costs.

Therein, it is a further object to provide a system and method for process control in which process status information and control information are centralized.

Not only in the running state but also in the preparation and holding state,
It is another object of the present invention to provide a system and method for reporting the time consumed by a process.

These and other objects of the invention will become apparent from the description of selected embodiments of the invention when read in conjunction with the drawings contained herein.

SUMMARY OF THE INVENTION Processes in a multiprogramming environment have four possible states.

namely, proceeding, preparing, having, and suspending. A process is in progress when it has control of a central processing unit (CPU).

The ready state is equivalent to running, except that the process does not have control of the CPU. A process is in a state when it cannot continue until a special event occurs. A suspended process is a process that is stopped for a period of time and then recovers. Each process in a computer system is called a process control block (PCB). - Associated with the software mechanism, this process control program operates as a virtual processor with null speed and also processes the control information required by the logical processor, i.e.
It includes the collection of hardware resources and control information necessary for process execution.

Whenever a processor's only job is to listen to signals sent by a process as they arrive, or after they arrive, a virtual ) is used instead of. The environment in which the process begins using the processor merely as a listening device is as follows. (a) When the state of a process is switched from a running state to a holding state, or (b) When a process state is switched from a running state to a suspended state.

In both cases, the CPU yields to the PCB and is replaced by the PCB.

The absolute address of a PCB is sometimes limited by two integers, J and P, referred to as the logical name of the process. Absolute locations known by firmware include J
There is a table called a table. The entry J in the J table is the absolute address P of a table called the P table.
Contains j. The entry P in the P table is a logical name (
J. ．． Contains the absolute location of the PCB defined by P). DESCRIPTION OF SELECTED EMBODIMENTS GENERAL DISCUSSION The present invention typically comprises hardware/firmware/
adjusted by the software operating system,
It operates effectively in the hardware system environment described below.

With reference to FIG. 1, the subsystems include a processor subsystem 101, a storage subsystem 102, and one or more - up to 32 peripheral subsystems 1.
It is 03. Each peripheral subsystem includes a peripheral control unit (PCU) 106, a number of device adapters (DA
) 107, and peripheral input/output devices 108 up to 256. The storage subsystem consists of one to four solid state storage modules of 32 to 512 kilobytes each. I processor subsystem In the processor subsystem 101, CPU1O4
performs basic processing operations for the system and interfaces with storage device 102.

IOClO5 controls all information exchange between storage subsystem 102 and peripheral devices 106. stomach
Central Processing Unit The CPU includes various elements including a main memory storage unit 109, a buffer store 110, a computing unit 111, and optional emulation equipment 112.

Primary storage concurrency unit 109 resolves conflicts regarding primary storage usage between computing unit 111, buffer store 110, and IOCIO 9. Conflicts are resolved on a priority basis. The IOC has the highest priority followed by memory writes (from computing devices) and then memory reads (buffer stores). The main CPU also controls the 1r main memory addressing and also controls the address controller A which controls the associative memory used to store the most recently used main memory addresses.
Contains CUL3l. Buffer store 110 stores selected portions of primary memory 1. A small, high-speed buffer storage device that interfaces with computing devices to restore minutes and reduce average storage access time. During each memory read, both the buffer store and main memory are accessed. If the information to be retrieved, 2, is already in the buffer store, the main memory read has finished and the information is retrieved from the buffer store. Otherwise, primary storage 102 is read. Each time this is done, CPU 2 selects three
2/ Bring out the ``ite''. This information remains in the buffer store for future memory references. Batsuhua store is
Because it is transparent to software, the program that controls the computer at a given point in time knows whether the information the computer is processing is being pulled from the buffer store or from main storage. unable to decide. The computing device 111 is C
All three data processing and address generation are performed within the PU.

A typical control store 130 within a computing device
(See the book entitled Microprogramming: Principles and Practice, by Samir S. Hutson, Prentice Hall), initializes the CPU1O4
and IOClO5 and includes firmware (not shown) that controls the IOClO5 and decodes defined instructions. Optionally, the control store may provide scientific instructions, test routines, emulation packages, or special purpose features that extend the capabilities of the processor subsystem. Optionally, the CPU provides emulation of a system other than an instant system.

The engineering controller 112 is a piece of firmware, software, and, in some cases, hardware.
j The IOClO5 portion of the input-to-output controller processor subsystem is connected to the peripheral subsystem 10.
3 and the storage subsystem 102.

This path allows for the initiation of peripheral commands and controls the resulting data transfer.

The IOC can typically handle up to 32 channels of control equipment (not shown). -) Peripheral subsystem In the peripheral subsystem 103 of FIG.
is the only microprogramming processor that relieves the load on CPUIO4 by controlling 1/O devices 108 during I/O operations.

The PCU does this by executing instructions contained in the channel program. Since this program is implemented within the PCU, it results in arithmetic operations, logical operations, transfer operations, shift operations, and branch operations.

There are several types of PCUs, depending on the type of control of the device. i.e. unit recording, mass (magnetic disk) storage, magnetic tape, communication, etc. Device adapter 107 coordinates between any PCU and the devices it controls.

Each includes dedicated firmware and logic necessary to perform communication on a particular type of equipment. Depending on its type, the DAlO7 controls one or several devices. The PCU resolves conflicts between devices attached to it for primary storage.

However, the IOC resolves conflicts between PCUs. 2. Storage Subsystem Primary storage 102 consists of capacitive storage media in the form of metal oxide semiconductor (MOS) chips.

This medium operates on a memory update principle to maintain information. Each storage location is typically updated at least once every 100 seconds. The design ensures that there are very few conflicts between memory update timing and memory accesses. (In case of a conflict, memory updates have priority of 1.) At the beginning of main memory, a portion is reserved for software and firmware.

The upper limit of this portion is limited by the contents of the Boundary Address Register (written after the BAR) that are clear to the system software. The contents of the BAR are set during system initialization.

The storage area under the address defined in the BAR contains peripheral subsystems, firmware that controls the two CPUs, or IOC tables that limit the configuration of microprograms and tables for emulation.

The size of the lower part of the address defined in the BAR varies depending on the system configuration.

Whether the microprogram is in main memory or in the control store depends on the system configuration. The application 31 is then executed on the system. Basic Mechanisms There are typically three basic data mechanisms utilized in this hardware.

That is, data format, software visible registers, 3! and instruction format. Data format information is transferred between the storage device and the CPU in multiples of 8 parallel bits.

Each 8-bit unit of information is called a byte. Parity or error correction data may also be
Transferred with data. However, it cannot be influenced by software. Therefore, in this patent specification, the term data excludes association parity or error correction data.

Bits in a byte are counted from 0 to 7 from left to right.

Bytes may be processed individually or in groups. 2 bytes make up a halfword, 4 bytes make up a word, 8 bytes make up a doubleword, and 16/<ite make up a quadword.

These are the basic formats for all data, including instructions. C. Data Display All data is in binary form and may be described in binary, binary, or alphanumeric format.

Data bits are described as binary W-adic data in groups of 4; 8 as alphanumeric and 16 to 6 as binary numbers. The latter may be described as binary encoding, fixed, or floating point numbers. The number of contiguous bits leading up to a double word can also be manipulated as a string. The alpha anonymous character to be set is EBCD.
Displayed on IC. ASCII is supported as an alternative interchange code. The byte location in main memory starts from zero, and the groups of bytes are successively divided if the address of the left byte is a multiple of 2, 4, 8, or 16, respectively. , halfword one, word one, doubleword one, and quadword one.

Whenever a halfword, word, doubleword, or quadword is so aligned, the unit can be retrieved from that address. The location of data in primary storage is revealed by a data desk lifter that is accessed indirectly during address development.卜Visible Registers There are 33 user-visible registers in CPUIO4.

In FIG. 1, the contents collectively define the state of the CPU.

There are four types.

(See Figure 2) 1 General register 2 Base register 3 Scientific register (optional) 4 Multidirectional register Go to 5 General register The general register (GR) is used to manipulate fixed-point binary digits and bit strings. It will be done.

There are typically sixteen 32-bit general 1r registers from CPU104-GRO to GR15. General registers GR8 to GRl5 can also be used as index registers. When used as index registers, they are referred to herein as x0 through x7. The indexing is done using the 32-bits contained in the register.
is implemented using the complement of integers. Base Register The base register (BR) has a similar format to the instruction counter and stack registers 202-203.

Base registers are used during address calculations to limit portions of storage.

There are typically eight 32-bit base registers, BRO through BR7. 2CH Scientific Register A scientific register (SR) is any device for floating-point binary calculations.

There are typically four 8-byte scientific registers called SRO through SR3. The scientific register has the format 204-205 of FIG. There are 5 other multi-register registers.

That is, an instruction 3 counter with format 202-203, a status register with format 207, an accumulation register (called T register), and an instruction 3 counter with format 202-203.
Hardware control and mask registers with format 208. Boundary 4 address registers with format 202-203.

The instruction register contains the address of the instruction to be executed.
- bit register.

Status register (STR) 207 is an 8-bit register that records facts about the procedure currently being performed, for example; whether an untablo has occurred due to the most recent operation. The stack register, known as the T-register, is a 32-bit register that contains a pointer to the top of the descending stack associated with the current active procedure. The deposit described below provides a workspace, stores local variables, and
and provides a mechanism for storing procedure entries and return information.

Boundary address register (BAR) 206 is a 28-bit register that specifies the lowest absolute primary storage address that software can access. This register is transported during system initialization and can only be read by software. Hardware control mask register 208 is an 8-bit register that records machine condition information.

There are approximately 200 instructions in the instruction format, if any at all.

Each command is one of four different lengths, but always
An even number of bytes long. Instructions are stored in contiguous storage locations. The address of the leftmost byte is a multiple of 2 and is the address of the instruction. The eight most important bits of the instruction (and in some cases 8 to 11 or 12 to 15) indicate the operation code, while the remaining bits
Display one or more operands.

The operand may be a register designator, a displacement designator, an address syllable (logical address), a literal value, a direct literal value. The type and number of operands are determined by the instruction format.

System Organization Job Steps and Tasks The work performed on the computer system is externally defined by a series of job steps via a job control language.

A job step is a unit of work to which hardware resources are allocated. Typically, a job step consists of several tasks. A task is the smallest unit of user-defined work that consists of a stream of instructions that are executed in nonparallel ways. The user-visible concepts of process tasks and job steps are, respectively,
Processes and groups of processes are represented in the hardware.

A process is defined as an organized sequence of instructions that can be executed asynchronously by a CPU (i.e., several processes can be active and share resources, but only one Two processes are actually going on at one point in time.

) A process group is a set of related processes necessary to perform a job step.

C. Process control programs and system base processes can relinquish control of the CPU at various points during their execution. This is used to prepare the CPU conditions before reasserting control of the CPU.

3. The storage area designated for the process is called a process control block (PCB) 400 in FIG.

The data contained in the PCB includes the address of the storage area designated for the process, the contents of all appropriate registers, and the state of the process. Thus, the PCB serves as a temporary storage area for information needed to initiate or re-enter a process without information loss.

Each PCB is visible to the hardware and addressable by the operating system via a set of hardware that is developed during system initialization and modified during system operation. (Figure 5). There is an absolute primary storage area called the system base (Figures 5 and 6).

This air field is developed by firmware and includes a base address register (BAR) 50 that can be read but not written to.
1 can be accessed via.

System base 502 contains a number of system attributes, each including a job step number and a process group number (J.P.), for a process currently in progress.

Another attribute in the system base is a pointer to a hardware-specific data mechanism known as a J-table 503. This table contains entries for every job step currently in the system.

Each entry in J table 503 is a hardware limited data mechanism. Points to the relation P table.
This table defines the process group and contains entries for every process in the process group. Each P-table entry points to PCB4OO. With reference to FIG. 5, via communication unit 506, J-table pointer 505 indexed by J-number provides access to J-table entries 503.

This entry includes a P-table guideline that, when indexed by P-number via communication unit 506, provides access to P-table entry 504.

The P-table entry contains the PC of the currently ongoing process.
It includes a pointer 507 pointing to B. Thus, the operating system can access the active PCB using the contents of BAR5Ol and other PCBs given their associated logical names (JP).
can be approached.

Memory Segmentation In a multi-process environment, as described throughout this document, there are many processes in storage at a given time.

These processes differ in scale and require storage, creating storage allocation problems.

The hardware described herein in cooperation with an operating system (not shown herein) solves the problem by allocating memory space 5 dynamically.

Due to the random nature of storage requirements, storage is allocated in variable size segments, and storage allocations can be reconfigured during process progress time.

Thus, a process is allocated many non-contiguous storage segments. This memory allocation method is called segmentation. Segmentation presents an additional problem in that storage addresses must be modified whenever part or all of a process is relocated.

To alleviate this problem, the system described herein provides techniques. Thereby, the addresses used by the process are logical rather than absolute primary storage addresses.

These logical addresses are used to develop absolute addresses.

Segmentation also allows each process to access its own or associated storage segments via a system of segment descriptors.

By accessing the segment desk lifter, the process obtains the address of the segment.

The segment desk lifter is contained within the primary storage and maintained by the operating system.

Each process stores up to 2068 storage segments 3. may have access to

Typically this would require an equal number of segment desk lifters for each process. However, since segments can be shared, operating system group 4 separates desk lifters into segment tables. This grouping consists of one process (
access capabilities (tasks), process groups (job steps), or overall (system breadth). Each process may have up to 15 segment tables associated with it. This technique requires only one segment descriptor for each segment, which the process can access via the segment table.

Thus, the storage space required for segment descriptors is reduced. Memory updates during relocation are reduced and some program protection is provided. (The primary mechanism for program protection is the ring system.) A process must be able to decide which segments it accesses.

Therefore, the system provides the process with two segment table word arrays (STWA). These arrays contain the addresses of all segment tables that can be accessed by the process.

Since there are two segment sizes, large and small, there are two segment table word arrays for each process.

A large segment has a maximum size of 7P2 bytes.
A small segment, on the other hand, has a maximum size of 216 bytes. All segments are 16-
The increase in bytes varies depending on the size. The system can typically accommodate up to 28 large segments and 2040 small segments.

The segment table word array may be relocated by the operating system.

Therefore, a process must know the absolute address of its associated STWA. The PCB for the process contains this information and, on FIG. 4, includes two words known as address space word ASWO-1.
Each word is a segment table word array STWA
is pointing to. The operating system updates the contents of the ASW whenever the associated STWA relocates. Gradually advancing the chain of guidelines;
And decoding the segment descriptor is
It is a function of the firmware and thus, once started, is invisible even to the operating system. Segmentation limits more than 200 million bytes of address space as it is available to processes.

This number exceeds the capacity of main memory. Therefore, secondary storage (magnetic disks or magnetic drums) is used in conjunction with main memory. Operating systems create the illusion that the system has a much larger main memory than it actually has.

This concept is called virtual memory. At a certain point in time,
The limited segment may or may not be physically located in main storage.

The contents of a segment descriptor indicate whether the associated segment is in main memory. The hardware detects a process' attempt to access a segment that is not in main memory and notifies the operating system. The operating system causes the desired segment to be transferred from secondary storage into main memory. Operating system 2 then places the storage address of the segment into the segment descriptor, which is the only place where the absolute address of the segment can be found. This operation is invisible to the process, thus it does not care whether the segment is not in main memory or whether the segment has to be relocated in main memory. . The computer system described herein provides data and procedure protection by preventing processes from interfering with each other and from arbitrarily sharing each other's address space.

This protection can be achieved by limiting addressability via storage segmentation and also by ring systems. The segment table is
Separate the address spaces of various processes in the system.

Processes always use segmented addresses during execution. A segmented address consists of a segment number and an associated address within that segment. The hardware checks that the address used by a process is part of the address space given to that process. If the address is outside the given address space, an exception is raised.

Because the hardware uses the matching process's segment table, processes cannot match data within the address space of other processes.

Thus, there is no possibility for a process or a process group to match entities belonging to other process groups. Generally, duplication in address space within a system occurs due to these segments being shared by all processes.

These well-known segments are created by system programs that check to ensure against address collisions. Segmentation thus protects user programs from each other and the operating system from user programs.

A segment shared by several processes is not protected from misuse by one of those processes.

A ring system is used to solve this problem. This groups the procedure and data segments into a four-class hierarchy. The four ring classes are numbered from 0 to 3.

Each ring displays a level of system privilege, with level 0 having the most privilege (the most inner ring) and level 3 having the least privilege (the most outer ring).

Every procedure in the system has a minimum and maximum execution ring number assigned to it, and
The number reveals who is calling the procedure. Procedures are subroutines that can call other procedures and can pass parameters to other procedures. The general rules for the ring system are as follows.

Procedures in one inner ring have free access to data in the outer ring.

Conversely, procedures in the outer ring cannot access the inner ring.

A procedure in the 2 outer ring can branch to a procedure in the inner ring 5.

However, the opposite cannot be observed. 3 Each segment containing data is given two ring values.

One is for reading (RO) and the other is for writing 1θ (WR).

These ring values define the maximum ring value.

In this case, the procedure can be performed when accessing data in either a read or write manner.

15 Each time a procedure instruction is executed, the ring number (Effective Address Ring, EAR) for that procedure is checked against the ring number assigned to the segment containing the data being matched.

EAR is the maximum number of 2C process ring numbers in the instruction counter and in the base register and data descriptor found in the address path.
Maximum number of all ring numbers. Data access is based on comparing ring numbers! It will either be approved or rejected. For example, if you have a system table in a segment with a maximum read ring value of 3 and a maximum write ring value of 1, a user procedure execution in ring 3 may read the table in ring 3; may not be updated.

By pre-design, rings O and 1 are configured as Liza 3. for the operating system. -Blocked, Ring 2
and 3 are reserved for the user.

Ring O contains these segments that are critical to overall system operation. Ring 1 contains a large number of system segments, the failure of which will not be catastrophic and will allow recovery. The user may utilize ring 2 for checkout programs and ring 3 for revised programs. , Procedure CallsProcedure calls are important operations in the systems described herein.

Procedure calls are used to pass from one procedure to another, are used to allow user procedures to use operating system services, and are used to implement modular mechanisms within the operating system. It will be done. Procedure calls are implemented by instructions and by authorized entities of hardware called deposits (FIG. 7A). Deposit is a mechanism that accepts, stores, and allows retrieval of data on a last-in, first-out basis.

The deposits are in special segments called deposition segments. The deposition segment is attached to the deposition frame 701 (FIG. 7).
A and 7B) and consists of a number of contiguous parts, which are dynamically assigned to each procedure. The first stacking frame is transferred to the top of the segment, followed by the next frame. The last frame transferred is considered the top of the pile. T-register 702 gates the top of deposition for the current active process.

Virtual T-registers exist in the PCBs of all other processes in the system. The deposition frame 701 of FIG. 7B consists of three areas.

That is, a work area 702 for storing variables, a save area 703 for storing register contents, and a communication area for passing parameters between procedures. Before the procedure call, the user must define those registers that he wishes to store.

The user must transport the parameters passed to the called procedure into the communication area.

When the call is made, the hardware registers the instruction counter I
A base register is defined to store the contents of C and to facilitate return from called procedures. Each procedural call creates a deposition frame within deposition segment 701, and subsequent nested calls create additional frames.

Each exit from one of these called procedures causes the stack frame to be deleted from the stack. Thus,
A history of calls is maintained, which facilitates orderly returns. Different deposition segments are used to ensure protection between procedures performed in different rings. There is one deposition segment for each guard ring for each process. The PCB contains three deposition base words that point to the start of the deposition segment for rings 0, 1, and 2 associated with each process. A ring 3 deposited segment can never be entered by an internal call. Therefore, the deposition start address is not needed within the PCB.

Process Management and Synchronization The system herein uses a combination of software, hardware, and firmware to provide multiprocessing operations controlled by an operating system.

Software creates and destroys processes within the system. On the other hand, hardware and firmware are CPU
Multiply the above process. Additionally, the combination of software, hardware, and firmware provides synchronization between processes. Processes are typically, but not always, used at the beginning and end of input/output operations during associated job handling, and at other times deemed necessary by the operating system. Started and stopped for a purpose.

Therefore, the communication system can effectively
It is necessary to start and stop related processes, and it is necessary to effectively pass information between processes. The hardware herein provides internal messages called traffic lights to provide communication links between processes. B Process states A process is always in one of four possible states.

i.e. proceeding, preparing, having, or suspending. The hardware recognizes the state of these four processes, and
Performs process submissions, state changes, and performs various firmware procedures to maintain data mechanisms based on process state. The PCB includes a status field that defines the current state of its associated process. The process is CP
When you have control of U, you are in a state of progress.

This state includes providing address space and starch ink addresses to the CPU. After that, the CPU
Implementing instructions in a procedural segment of a process.
For the currently ongoing process, each process J on the PCB
Table words (logical addresses) are system-based (
In FIG. 6), the progress process word (BAR+60) is maintained.

(Note: The system base shown in Figure 5 is the same as the system base shown in Figure 6, except for the omission of some details.) The ready state is the state in which a process is not visible to the CPU. This is equivalent to the progress state, except that it is not under CPU control.

A process in the ready state is a CP with other ready states.
The U and the process are in dispute. When a process cannot continue until a special event occurs, such as a message passing through a traffic light, it is in a hold state.

The holding process is not in dispute for the CPU. However, it may be in conflict with other processes for the required event. A suspended process has been suspended for a certain amount of time by the software,
It is a process that may be restarted later.

Decisions to stop and restart a process are external to the process. Thus, the suspended process is inactive and therefore cannot be notified of the occurrence of events and cannot utilize the CPU. A process suspends: (1) by executing a termination instruction (as a result of all its functions completing);

{2) Due to execution of an abort instruction by the operating system.

(3) Due to the occurrence of an exception condition.

Control is thereby transferred 5 to the operating system. Process Dispatching A process moves from one state to another as it progresses, at will, by the action of another process, or from one state to another, involuntarily, by the action of another process. Move.

CPU firmware, known as a dispatcher, controls the handling of processes between states. The dispatcher uses a set of queues (described below) to manipulate processes that are in the ready or hold state. The suspension process is controlled by software. 6, 8 and 9, ready or held processes are represented by special queue entries called PCB and process links.

FIG. 9 shows (1) an exploded view of the contents of segment 802 and also process links 803a--
803b and 803c-803g1 and free process links 805a-805c. Each process Σlink defines a process name (JP), a process priority, and guidelines for the next process link in the queue. Holder key 803a1b and preparation key 803c
There are various types of keys such as -g. A hardware device similar to the J-table and known as the G-table (Figs. 6 and 8)
- Contains guidance for 802n (known system widths).

The first element of the G table 801, (1), points to the segment 802 that contains the despatches. G table guidelines for G table 801 are found in system base 502 in FIG. Also, GO segment 80
At 2, there is an entry in the system base called the Internal Process Queue Word (IPQW) that identifies the head of the preparation queues 803c-803g. Thus, the dispatcher can test all preparation processes by consulting the preparation queues 803c-803g.

When a currently ongoing process changes state, the dispatcher removes the process link at the head of the preparation queue and uses J.D. to access its PCB. Use P name. The process bounded by the PCB then becomes the new progressing process. Since more than one process may be waiting on the same event, the holding process 803a-
A queue 803b exists for each event.

Morimochi processes are also stringed together via process links 805 that exist in the GO segment.
Guidelines for the head of the holding queue are present at traffic light 903 (described later). There are many events that a process may be waiting for. Therefore, there are many signals, each of which has an associated traffic light 90,904.
has.

The number of ready or held processes changes dynamically.

Thus, the number of process links required for preparation and storage also varies. This fact introduces a memory management problem for dispatchers. The problem is solved by other queues called free process link queues 805a-c.

This queue combines all of the process links in segment (1) that are not used by the prepare or hold process and can be used to expand the special queue of the prepare or hold process. contact.

Pointer 901 for head 902 of free process link queue 805 is (1) near the beginning of segment 802; C. Process Synchrony Process synchrony requires coordinating the activities of two processes working on the same task.

Synchrony is a traffic light 903-9, which is a data mechanism that exists in the address space of communicating processes.
This is achieved using 04. Traffic lights are used to signal the occurrence of events and to process messages.

An event in this context is something observed by a process and of interest to other processes. The event is
It might be the completion of an asynchronous operation, or it might be the availability of a resource. The process,
Two traffic light operations are used to signal the occurrence of an event.

One operation sends the signal to the traffic light, the other
Capturing a signal from a traffic light. (The outgoing operation is
Often referred to as V-operations, receive operations are referred to as P-operations. ) The sending operation (ThesendingOperationOn) causes a process to send data or a signal that the data is ready.

A traffic light stores the signal until another process is ready to capture it.

Thus, the originating process is free to proceed now that it has sent the data. The receive operation tests the specified signal and takes the signal. If there is a signal, the receiving process continues to perform. but,
If there is no signal on the traffic light, the receiving process enters a holding state. Thereafter, the traffic light serves as a guide to the head of the handler.

The process remains in the queued state at the traffic light until some other process sends a signal to the particular traffic light. Thus, a traffic light can hold a signal until some process captures it. Ru. Alternatively, the traffic light can hold the process until a signal is sent to it. Messages can also be passed from process to process.

The message ζ has the same current quality as the signal and the additional information, or it has no such quality.

Some of the information is supplied by the hardware and some by the procedure of the process that sent the message. Metsu sage is the outgoing process (Thes
endingprOcess) process name. Thus, many processes can send information labeled with the originator's name through a traffic light. A message traffic light may have a queue of messages waiting to be captured by a process.

For traffic lights, storage space requirements increase and decrease, presenting storage management issues. Again, the problem is
The problem is solved by using the free message link.

These links exist in known locations on the segment where they can be easily found when it is necessary to supply or absorb message links. Since the traffic light and the queues created on the traffic light are shared by different processes, the entire traffic light mechanism is protected.

This is accomplished through hardware and software provisions that restrict access to segments containing traffic lights. Thus, traffic lights must be in signal descriptor segments, some of which may be G segments (if system communication is required). However, all G segments (except GO) are traffic light descriptor segments. Each traffic light descriptor includes guidelines for the traffic light.

Thus, while providing additional protection for traffic lights,
Traffic light addresses are developed via traffic light descriptors. Traffic light segments can be logically addressed using a segment number and associated location within the segment, or directly using a GND number.

Process Control Block Mechanism Regarding Figure 4, the process control block (PCB
) format is shown.

Process control block 400 is a storage area in main memory that is available to processes to store CPU status. Addressing the PCB is performed as described above in connection with FIG. PCB pointer 507 (FIG. 5) is connected to the PCB control program PCB at storage location 0 in FIG.
Pointing to B. In the downward progression the storage location increases by 4 bytes, while storage location 0
It will be noted that in the upward progression from , the storage location increases by 8 bytes. Lower storage locations are considered positive from 0. On the other hand, locations upward from 0 are considered to be in the negative direction. The upward location is optional and may or may not be included in the process control program. Also, the locations of 148 to 176 are also arbitrary. (Note: The number under storage location specifies the displacement in bytes from the 0-verification location of the process control block PCB.) Starting with bytes 0 through 16 (but not including 16). , four process main words PMWO to PMW3 are stored, with each process main word PMW being 4 bytes in length. Process main word 0 occupies byte 0 and consists of four parts. i.e. capability byte, priority byte, status byte, decoder extension byte DELTO Figures 10a to 10
For d, the capacity byte 100 shown in Figure 10b
Process main word PMWO with additional details of 1
details are shown. With respect to Figure 10b, the first bit 1005 is an accounting mode bit to indicate whether a time accounting function is being performed for the process. When accounting mode 1005 is set to binary 0, no time accounting functions are implemented for the process. On the other hand, when accounting mode 1005 is set to binary 1, time accounting is being performed. When the scientific mode bit 1006 is set to zero, no storage of the machine's scientific registers is performed and the storage area of the scientific registers, gated from bytes 148 to 176 in FIG. It does not exist in the Tsuku PCB. When scientific mode bit 1006 is set to a binary 1, any scientific attributes are present and used in the process. and,
The scientific register storage area is used to store the contents of scientific registers when needed. With a binary zero in the position indicating that the standard code set is being used, the code mode bit 1007 indicates whether the standard code set or the qualified code set is being used by the process. On the other hand, a binary 1 in the third bit possession 1007 indicates that the proper code set is being used. The remainder of the bits in the capability byte are set to zero. Priority byte 1002
Details are shown in Figure 10c.

With respect to FIG. 10c, the first four priority bytes 1002
Two bits 1008 are utilized to set the priority level of processes associated with certain process control block PCBs. Each process is given one of 16 levels of priority, which is used to order competing processes. That is, (a) To select the process to be carried out during the preparation process.

This is to keep the process in one place.

The priority decreases from 0 to 15. A FIFO (first in, first out) rule is applied for a certain priority level. Four bits 1009 of the next priority byte 1002 are zero.

With respect to FIG. 10d, details of status byte 1003 are shown.

The status byte is the process control block PCB4.
Used to provide information about processes associated with OO. Active field bit AlO
lO is set to binary 1 when the process is active. The suspend field SlOll is set to a binary 1 when the process is suspended. - The substate field SSlOl2 is a 2-bit field and defines the following substates of the process. stomach
When set to binary 00, the process is inactive.

．． When set to binary 01, the process is waiting in the queue of the preparation process (Q/BR/RDY).

C. When set to binary 10, the process is waiting at the traffic light at the traffic light queue (Q/PR:i:S).

When set to binary 11, the process is being performed by the processor.

The intermediate operation field (MOI) 1013 is set to a binary 1 when an interrupt occurs;
Provided during execution of the instruction - ie, prior to completion of the process.

Extended equipment mode bit EXTDlOl4 is set to 1 when the process is operated in extended equipment mode, which is the machine's emulation mode. Bit 1
015 and 1016 are set to 0. The fourth byte of the process main word PMWO contains the device expansion number;
Used when the system is in emulation mode. The process main word PMWl is stored in bytes 4-7 of the process control block PCB.

Details of PMWl are shown in Figure 10e. Status byte 1016 is the first byte in PMWl and stores the status register contents. Multiprocessor bytes 1018 are important in multiprocessor architectures. Otherwise, this field is 0. The second and fourth bytes of the process main word are MB2 fields 1017 and 1019, respectively, which must be zero for normal operation.

Process main word PMW2 occupies bytes 8 to 11 of the process control block and is shown in more detail in Figure 10f.

With respect to Figure 10, the field bits 4 through 31 contain the logical name of the signal SEGlSRAlO that the PCB binds to when the process is in the hold or suspended state.
Contains 2l. Exception class and type 1023 indicates that the process is suspended after an exception. Contains the class and type of the interrupt-like exception that will cause it to occur. The field bits 4 through 15 are meaningless 1022 when the process is in a different state prior to the bits listed above. Process main word PMW3 is PCB4OO
, occupies bytes 12 to 15 and points to the device expansion table.

Regarding figure 10g regarding details of PMW3, DETSZ
Field 1024 limits the number of entries in the table, and if this field is zero, no device growth is allowed to the process. The DETA field 1025 is the absolute address of the device extension table in units of 16/< bytes and is only significant if DETSZ is non-zero. The device enlargement table is DETSZ
It consists of entries. Each entry is 1 byte in size. The DEXTtl entry in the table limits the ability of a process to operate in device expansion mode DExT. When the DEx6 byte is 0, the device extension number DExT is not allowed, whereas if the DEXTth byte is 1, the device extension number DEXT is allowed. DEXT values other than 0 and 1 are illegal.

(See Figure 10a DEXT number 1004) PCB4O
Bytes 16 to 23 of O each contain two address space words ASWO and ASWl.

Each ASW includes a pointer that points to an array of segment table words. Both ASWO and ASWl each have the same format as shown in Figure 10h.

The size of the array of segment table words is limited by the number of segment table words in the array, typically including 6 for ASWO and 8 for ASWl. STWSZ field 1026 is
Display the size of the segment table word array. Segment table word array field STWA
lO27 contains the absolute address of the array in units of 16/<ite. That is, the absolute address of the array is 1 byte.
It is 6 times STWA. Bytes 24 to 27 are shown in Figure 10.
1 includes an exception word EXW, shown in further detail at 1.

The exception word includes a guideline (SEG.SRA) 1029 that points to an exception class table that limits the actions to be taken following a process exception, depending on its class, as stored in the process main word PMW2. (Figure 10
f) MBZ field 1028 of exception word EXW
must be 0. The deposition word SKW, located in byte 28 through 31 of the PCB, contains the value of the top of the process's deposition T register when no process is in progress, and is shown in more detail in FIG. 10j. Figure 1
For 0j, bytes 0 and 1 are TAG field 1
030 is limited. TAG indicates the type of descriptor by its contents and must be 0 for SKW. Bits 2 and 3 of the SKW contain a RING field 1031 containing the ring number associated with the deposit's distinct address for security purposes. Bits 4 to 31 contain the segment number SEG, and the segment related address SRAlO32 is a field that confirms the segment written in the segment table and confirms the segment related address within the segment. The deposition word SKW is updated each time the process leaves the progress state. The deposit word is used to restore the contents of the T register each time the process is in progress. In this last case, TAGlO3O and Rf
sJGlO3l is tested to be zero. Otherwise, an illegal PCB exception will occur. Bytes 32 to 35 of PCB4OO are sometimes referred to as the ICC.

Contains the instruction counter content word ICW. With respect to FIG. 10k, details of the instruction counter word ICW are shown. In it, the TAG field 1033 is the binary number 00
must be included. (That is, non-zero values are illegal in the instruction counter. The current RING field, which occupies bits 2 and 3, limits the current number of rings for a process that is used to determine access rights to maso storage. 4 to 31 define a segment number and segment related address (SEG1SRA) 1035 that define the address of the next instruction to be executed.
The MBZ field in bytes 36-39 must be O.

(Note: The MBZ field displays a field that must always be 0). MW is the name J. It is tested every time it is accessed from P. If it is not O, an illegal PCB exception is raised. Deposition base word S
BWO-2 occupies bytes 40-51 in process control block 400. These words are shown in Figure 10.
It has the same format as shown in more detail in . These are utilized during the deposition operation. And whenever used, their TAG field 1036 and RING field 1037 must be zero. Otherwise an illegal PCB exception will occur. Bits 4 to 31 are rings 0, 1, and 1, respectively.
and 2 contains the segmented address (SEG,.SRA) 1038 of the first byte of the deposited segment.
Bytes 52-83 of process control block 400 are space reserved for the base register storage area (8 words).

Bytes 84 to 147 contain the values of all general registers (
16 words). Bytes 148 to 179 are in the scientific register (8
This is a storage area used for storing (words). Five doublewords are provided in PCB4OO on the PCB zero address for time accounting purposes when the accounting mode bit in the PMWO word is set.

These words are from PCB address minus 8 to
Gate to B address minus 40. Each word is
The first 52 bits, with bits 52-53 filled with zeros, contain the time, or time interval, expressed in 100 seconds. The remaining timeout doubleword RTO (the first eight bytes above O in the PCB) contains the amount of time actually spent by the processor on behalf of the process before a timeout exception occurs. The RTO word is updated in the following manner. That is, each time a process leaves the progress state, the process timer value is stored in the RTO word. Each time the process enters the progress state, the process timer value is transferred from the RTO. The Progress Time Accounting RUA doubleword in bytes 7 through 15 is a time counter that defines the total amount of processor time when the process is in progress.

The time accounted for is the time actually consumed by the processor exclusively on behalf of the process. R.U.A.
Words are updated in the following manner. Each time a process leaves the progress state, the value of the process timer is read. RTOI:. The difference in the content of RT is
Added to RUA.

(Thus, the threshold value is stored in the RTO.) Note that the time the process is suspended is not calculated. R
T.O. ! :． The RUA word is updated even if the accounting mode bit is set to zero.
However, CET. The RTAl and WTA words (described below) are provided to the process control program only if the process main word PMWO is set to one. They will only be updated in this case.
The holding time accounting WTA word in bytes 17 to 23 is a real-time counter that defines the total amount of real time when the process is in the holding state. The WTA word is updated in the following manner. Each time a process leaves its current state, the time TOD of the sundial value is
is read and the TOD value minus CET value word is W
Added to TA word. Ready Time Accounting RTA, located in bytes 24 to 31, is a double word RTA that is a real-time counter that defines the total amount of real-time when the process is in the ready state.
is updated in the following way.

That is, each time a process leaves the ready state, the sundial time value 10D is read. The contents of TOD minus the contents of CET are then added to RTA. The current entry time CET doubleword in bytes 32-39 contains the date and time the process enters one of the following states.

namely, preparing, having, proceeding, and suspending. System Base Mechanism Referring to FIG. 6, the format of a system base 600 is shown.

The system base is a boundary address register (BA) that resides in absolute main memory, is developed by firmware, and can be read but not written.
It can be accessed via R).

The boundary address register BAR underlies the area in main memory reserved for hardware and resolves this area in storage reserved for hardware and system base 600.

6, the system base 600 includes a number of system characteristics for one of the processes currently in progress, including job step number and process group number (J.P.). Process J. The absolute address of the corresponding process control block PCB is obtained from the logical name of P. The size and address of the J-table is limited by the contents of the J-table word (JTW).

This word is located at the address defined by the BAR register. The format of the JTW is shown in Figure 11a. Size (JTSZ) 1101 or J-table 1204 on FIG. 12 limits the number of entries in J-table 1204, which may be up to 255 entries.

JTSZllOl is an 8-bit positive integer. If J is greater than JTSZ, a J table exception out occurs. The absolute address of the J table 1204 is J
It is obtained by multiplying the table pointer 1102 by 16.

J-table 1204 contains J-table entries, the format of which is shown in more detail in Figure 11b.
Each J table entry has one J table guideline 1104.
The absolute address of the P table 1205 obtained by multiplying by 6 is limited. P table size PTS
ZllO3 limits the number of entries in the P table. PTSZ is an 8-bit positive integer that may typically vary from 0 to 255 to indicate the number of entries in the P table. If P is ・PTS
If it is larger than ZO, a P table exception out occurs. Each entry in P table 1205 is entered into process control block (PCB) 120 by multiplying process control block pointer 1107 by 16.
6 absolute addresses are limited. Current indicator Pll
O5 indicates the absence of PCB12O6 when set to a binary 0 and indicates the presence of a PCB when set to a binary 1. When the current indicator PllO5 is found to be 0, an empty P table entry exception occurs.

Bits 1 to 7 of the P table indicator (Figure 11c)
must be 0(MBZ)1106. Otherwise, an illegal P table entry exception will occur. System base 600 address BAR plus 4, Figure 1
The G table word (G
There is a format byte of TW).

The size and address of G segment table 1212 in diagram 1200 is limited by the contents of the G table word (GTW).

The size (GTSZ) 1108 of the G table 1212 is
Typically, we limit the number of entries in the G table, which may be up to 255 entries. GTSZ
is an 8-bit positive integer. If G number one is GTS
If it is larger than Z, a G table exception out occurs. The absolute address of G table 1212 is obtained by multiplying G table pointer 1109 by 16. The format of a G segment table entry has a 2 word size (8 bytes) and is called a G segment descriptor. The format of the G segment descriptor is shown in detail in Figures 11e and 11f.
All G segment descriptors are direct, so indirect bit 1,1111 must be zero. Otherwise, an illegal segment descriptor exception will occur. Current indicator PlllO is a 1-bit field that, when set to a binary 1, indicates that the segment is limited in main storage for the segment number to which the descriptor corresponds. On the other hand, if the indicator PlllO is now cleared to 0, then the segment is not qualified and a match to the segment descriptor will result in an unspecified segment exception. The resulting bit All2 is a 1-bit field that indicates whether a segment is available or not. It is only checked if this segment is limited (ie, P equals binary 1).
Otherwise, it will be ignored. The flag field Ull3 used indicates whether the segment is being accessed. If the U bit is set to binary 0, the segment is not being accessed. On the other hand, if the U field is set to a binary 1, the segment is being accessed. Written, flag field Wllll4 indicates whether the segment is being written. If w is binary 0
If it is not set to , the segment has not been written. On the other hand, if W is set to binary 1, then
Segment has been written. The gate indicator GSllll5 of the G segment descriptor is binary 01.
Must be set to . Otherwise, an illegal segment descriptor exception will occur. The reason for this is that the G segment must always contain traffic lights. (That is, it is not necessary that all traffic lights be in the G segment, even though the reverse is not true.) And the instructions on the traffic lights require that the GS code be binary 01. The absolute address of the base of segment 1214 is defined by the 24-bit base field 1116 in FIG. 11ef) G segment desklift. The contents of this field are multiplied by 16 to obtain the absolute address. The second word of the G segment descriptor in Figure 11f is:
In the G table 1212, bit possessions 32 to 63 are occupied. RSU field 1117, bit 3
2 to 39 are reserved for software use;
And when used as a G segment descriptor, as in this case, it is generally ignored. M
BZ field 1118 must be zero. Otherwise, an illegal segment exception will occur. MBZ
Field 1118 occupies bits 40 through 50, so it sets SIZN field 1119, which is the field for small segment SIZN.
Therefore, all G segments must be of small segment type. Segment SIΔ1119 is a 12-byte positive integer that limits the number of bytes in the segment, and segment size is described as a multiple of 16. Therefore, the segment size for G segment 1214 cannot exceed 216 bytes (small segment). System base 6 in Figure 6 again
Associated with 00 are 9 system exception cell words located between BAR plus 8 and BAR plus 44.

The format of the system exception l cell word EXC is shown in Figure 11g. Since traffic lights are used to transmit messages to the destination process when an out-of-system event occurs, the guidelines for these traffic lights are based on location-specific system exception cells called system exception cells. are found in nine locations of storage, one per class. MBZ field 1120 is 2
Must be set to base 0. Otherwise,
System tick occurs. Each exception cell (EXC) has a system name G, . Contains Dll2l and 1122.
The Channel Exception Cell, located in BAR Plus 44 of System Base 600, has a format similar to the System Exception Cell previously discussed, and is a traffic light used to transmit messages to the intended process when a Channel Exception occurs. Contains the system name (1).

The internal processor keyword 1PQW begins and is located at BAR plus 48.

Details of its format are shown in Figure 11h. The IPQW word is used in the preparation process queue (Q/P) as shown in FIG.
R/RDY). The preparation process queue (Q/DR/RDY) combines all processes in the preparation state. It is the Q/PR/RD of the IPQW word by pointing to the top of the preparation process queue.
Verified by Y-field 1124 HEAD.
Q/PR/RDY-HEAD of field 1124 is
(1) Contains 16 sets of positive integers that are the displacement from the base of G segment number 0 to the first byte of Q/PR/RDY, called segments. If this Q/PR/
If the RDY bit field is 0, the reserve queue is considered empty.

MDZ field 1123 must be zero.
Otherwise, a system check will occur. Storage of initial and current retry counts is shown in BAR Plus 52 of System Base 600.

The format is shown in detail in FIG. 111. NFS field 1125 is a non-functional storage field and is not utilized by the system base. The initial retry count field 1126 and the current retry count field 1127 are used to control the number of times automatic instruction retries are performed before a machine error is made and causes a machine fail exception condition. They are transported with the same number by the reset retry count (not shown here). As shown in Figure 11j, the progress process word (R
PW) is stored in the BAR Plus 56 of the system base 600 and is used to store the name of the ongoing process 1 along with its priority in the case of a monoprocessor architecture.

NFS fields 1128 and 1131 are each non-functional storage fields that can be used by any facility for any purpose, but are generally not used by the system base. The priority level for the ongoing process is stored in PR field 1129.
Asynchronous trap bits are stored in AB field 1130. On the other hand, asynchronous trapping is stored in ARN field 1132. In the case of a monoprocessor structure, the logical name JP of the ongoing process is stored in the JP field 1133. The absolute table pointer word shown in FIG.
+60 and is used at the initial system load to initialize the absolute addresses in the initial system, load (ISL) program by adding the contents of BAR to all absolute addresses in the ISL program.

Absolute table pointer 1135 defines the position of an absolute table (not shown). The absolute table size is A
It is indicated by TSZ field 1134. Figure 11
The CPU serial number word shown in 1 is BA
It is a 4-byte word located at R plus 64 and the CPU
In the serial number field 1136, the CPU
Contains serial number. The main storage cap word shown in Figure 11m is located at BAR plus 68;
Displays the main storage limit 1139 by giving the absolute address of the last available word in main storage. Initial system load I with BAR Plus 72
SL device channel number one (CN) 1140 and hardware device channel number one (CN) 114
1 to provide the word position shown in FIG. 11n.

The type and subtype of equipment used in the computer system are shown in fields 1143 and 1144, respectively.
Hardware device type word in (Figure 110
), where the RSU field 1142 is reserved for software.

This word is found in the system base at B, AR plus 76. Similar words with similar type formats shown in Figure 11p include the type and subtype of the device used in the initial system load. This word is located at BAR plus 80. When the computer glue start button is pressed, a simulated V-operation is performed on the traffic light and a ready state is entered.

The guideline for this traffic light is System Base 600 B.
It is detected by the AR Plus 84, is called a restart cell call, and has the format shown in FIG. 11q. This format is similar to the system exception cell described above, with the system names of the traffic lights G, . D
including. MDZ field 1148 must be zero. If the computer system has more than one processor, words are provided in the BAR Plus 88 and System Base 600 for multi-process expansion. Details of this word are shown in Figure 11r. Example of System Base and Process Control Block Usage Referring to Figure 12, how the system base addresses a user segment, a system segment, or a process queue preparation (Q/PR/PDY) segment;
An example of how it can be used in combination with a process control process to access is shown.

Main memory 1200 has a portion 1200 reserved for hardware use. Boundary address register BARl2O2 separates system base 1215 from the portion of memory 1203 reserved for hardware. Boundary address register B
ARl2O2 is requested on a system basis for the contents of the boundary address register. System base 1215 by adding to the dislocation in units of 4 bytes of the item.
used to address items. This address then points to the first byte of the item on the requested system basis. In FIG. 12, B
ARl2O2 points to the J Table Word (JTW). The J-table word has a pointer pointing to the J-table 1204, as previously discussed. By indexing to the J number shown in FIG. 5, a J table end 216 is obtained. In the J table entry, there is a P table pointer that points to the absolute address of the P table 1205. By indexing the P number (see FIG. 5) in P table 1205, the absolute address of process control block 1206 is obtained.
In the process control process PCBl2O6, the two address space words ASWO are input as shown previously.
and ASWI. The high order bit of segment table number field STW in base register 1201 is used to access one of these two address space words. In this case,
ASWI, which has a segment table word array STWA pointer pointing to segment table word array STWA12O8. Base register 1201
With segment table number STN, one of the eight segment table words is accessed at STWAl2O8, which points to one of the eight segment tables 1210. After that, the segment table entry STE from the base register 1201 is 256 in the segment table 1201 where the segment descriptor is located.
Used to make one entry. Then the segment descriptor is set to user segment 1
211. The G table word GTW is utilized at the system base 1215 to access the system segment 1214 that is utilized for storing traffic lights. The address of the G table word is obtained by adding the transposition of the G table word on a system basis to the boundary address register BAR12O2. (See Figure 6) G table word GT
W includes a G-table pointer that points to G-table 1212.

The G segment descriptor is accessed by utilizing the G number available to the system and indexing in the G table. It is then utilized to address system segment 1214. Similarly, the system base 1215 stores the preparation process queue segment (Q/PR/RDY) segment 1
The internal processor keyword n) pointing to 213 is used to access Q/PR/RDYl2l3 by gating QW.

Control Device With reference to FIGS. 13a-13c, details of the control device are shown.

Even though the control unit is shown separated from the central processing unit (CPU), it is actually part of the CPU and includes a control unit CSUl3Ol, a control unit interface adapter CIAL3
O2 and attached subunit, control store rotor C
SLl3O3, and control unit CLUl3
It consists of O4. control unit CS
Ul3Ol is the control and load unit CLUl
It receives microcommands from the control store rotor CSL13O3 via the control store rotor CSL13O4 and the control store interface adapter CIAl3O2.

Under normal operating conditions, microprograms are transported from external sources during system initialization and
It becomes a permanent control function of the machine. however,
The control store unit CSU13O1 has the ability to be re-transported and initialized in a manner that provides various central processing unit CPU13O6 modes of operation. The following modes of operation of the CPU are obtained under the control of CSUl3Ol. {B) Native mode (口) Emulation mode (C) Simultaneous native and emulation mode (
d) Diagnostic mode This ability allows the microinstructions present in the CSU to
It is the source of micro-operations used to control the operation of all other CPU functional units, such as the instruction fetch unit 1FU 1318, the address control unit ACU 1319, and the data management unit DMUL 321.

In addition, the central processing unit FCPU13O6 includes the general register 1307, base register 1308, and
Scientific register 1309, T-register 1310, status register 1311, instruction counter ICl3l2, and hardware control mask register 1313
is shown. Typically, the control store unit C
SUL3Ol is a 9K integrated circuit program read-only memory (PROM) combined with a read/write, random access store (RAM).

It has typical 150+1 second read cycles and 450+1 second write cycles. Is each location in the control store one? It stores bit microinstruction words (described more fully below), each microinstruction word controlling one CPU cycle. As each location of the control store of control store unit CSU13O1 is read, its contents cause each signal to cause a specific operation within the CPU. It is decoded by a micro-operation decoder which provides micro-operation control signals. Grouping locations within microinstruction words (described in more detail below) provides control store sequences that can perform specific CPU operations or instructions.

As each instruction is initiated on the CPU, certain bits in the opcode are used to determine the control store starch ink sequence. Testing of certain flops (not shown) set and reset by the instruction decode function allows the control store memory to branch to more specific sequences when necessary.

Control Store Interface Adapter CIAl
3O2 is the control store memory 133 in FIG. 13b.
3, the control store unit 1301 and the data management unit D
MUl32l, address control unit ACUl
3l9, and arithmetic logic unit Al. Communicate with Ul3l7.

CIAl3O2 changes control store address,
Contains testing, error checking, and hardware address generation logic. Hardware address generation is commonly used to develop starting addresses for error sequences or for initialization sequences. Data management unit DMU
132l provides an interface between CPU 13O6 and main memory and/or buffer store memory as shown in FIG.

It is the responsibility of the data management unit to recognize which units contain information needed by other units and to stroke that information into the CPU registers at the appropriate time. Data management unit D
The MU also performs masking during partial write operations. Instruction fetch unit IF'Ul3
l8 is DMUl32l, ACUl3l9, ALUl3
It interfaces with I7 and CSUl3Ol and is responsible for maintaining the CPU given instructions.

The instruction fetch unit has the next instruction available in its registers before the current instruction completes. To provide this capability, instruction fetch unit IFUl3l8 includes one 12/<item instruction register (not shown) which typically contains one or more instructions. Furthermore, f'U is
Under the control of the CSU, requests information (instructions) from main memory before the instructions are actually needed. Thus, the 12-byte instruction register is constantly updated.
Instructions are thus executed by means of memory cycles that are not normally used. The instruction fetch unit also decodes each instruction and communicates the length and format of the instruction to other units. Address control unit ACUL
3l9 was sent to IFU. ．． ALU. ．． DM
Communicate with U and CSU.

ACUl3l9 is responsible for all address evolution on the CPU. All ACU operations are
Directed by CSU microoperations and logic in the units, including inter-unit and intra-unit transfers. Normal cycling of the ACU depends on the type of address in the instruction rather than on the type of instruction. Depending on the address type, the ACU can perform different operations for each address in the instructions. The ACU also includes a content addressable memory 1319a that typically stores the base addresses of the eight most recently used memory segments along with their segment numbers.

Each time a memory request is made, the segment number is checked against the content addressable memory to determine whether the base address of the segment has already been developed and stored. If the base address is addressable memory 13
19a, this address is used in absolute address evolution and a significant amount of time is saved. If the base address is not contained in content addressable memory 1319a, it is developed by accessing the main memory table. However, after a segment's base address is developed, it is stored in content addressable memory along with the segment number for future reference. The arithmetic and logic unit ALU1317 includes ACU1IF'I, . DMU
1 and CSU.

Its primary function is to perform arithmetic operations and data manipulation required by the CPU. Arithmetic logic unit operations are completely dependent on microoperation control signals from control store unit CSU13O1. Scratchpatch memory unit LSUl3l5 is combined with ALUl3l7 and CSUl3Ol (often referred to as a local store unit). It typically has 256 locations (32 bits per location) solid-state memory, and selection and read/write logic. Scratchpad memory 1315 is used to store CPU control information and maintainable information. Furthermore, scratchpad memory 1
7315 contains a working location used primarily for temporarily storing operands and partial results during data manipulation. It is also typically used to store other state of the computer system.
Seven auxiliary memories 1317a consisting of flip-flops are
It is combined with ALU1317. The CPU also
The clocking unit 1320 is essentially a two-in-one clocking system.

The first clocking system generates timing for the coat roll interface adapter CIAL3O2, and the second clocking system generates a timing palace for the operation of the functional units within the central processing unit. . With reference to FIG. 13c, the format of control store word 1325 is shown.

Control store words are typically 8 bits wide and divided into 6 fields. B. Sequence type field 1326 (3 bits) Branching and/or micro-operation 1327
(23 bits) C Constant generation and designation 1328 (14 bits) Data for two buses 1329 (8 bits) is used as a sequence control field.

For an instant computer system, there are typically seven different sequence types and one reserved type. In connection with block 1335 of FIG. 13b,
Branching field A. of microinstruction 1325 when E field equals binary 0, 1, or 2.
sB. sC. ,D,. E is used to generate the next address. The first six pitches of KS register 1337 are utilized in conjunction with B field, C test result, D test result, and L field to provide the next address of the next microinstruction placed in address register KSl 337. . When the E field is set to binary 4 (see block 1335), the next address selected is obtained from interrupt return register KAl 339. The address stored in the KA register is the address generated by the next address generation logic when a hardware interrupt occurs. When the E field is set to binary 5, the branch is used to initiate a subreturn from a microprogram subroutine. When used, the contents of return register KRl 346 is used as the next control store address. Return register 1346 is transferred by issuing a control store command that transfers the current control store address in KS register 1337 plus one from incrementer 1338 to KR register 1346. One level nesting subroutine capability is provided via KT return branch register 1347.

Each time the KR register 1346 is migrated, the old contents of the Xiang register are transferred to the KT register 1347 each time microprogram return is called. K.T.
The contents of the register will be transferred to the KR register.
Third level nesting subroutine capability is provided by KU register 1340. Fourth level nesting subroutine capability is provided by KV return branch register 1349. When the E field of the control store word is set to binary 6, the next control store load addressed is equal to the current address in KS register 1337 plus one in incrementer 1338. E field is binary 7
When set to CSU13O1, CSU13O1 enters diagnostic mode and the next address will be until the current address plus one. In addition to the branching sequence control for the following controls described above and shown in block 1335, block 1336 of FIG.
It is shown in There is hardware generated sequence control.

(Note: PROCs 1335 and 1336 are actually hardware registers drawn to depict the various forms that the microinstruction word takes.) The hardware-generated branch overrides the E field and An invalid condition (error. initialize, control store scan, etc.) that forces the address into the control store address register KSl 337. The branch is executed by pushing the interrupt line high (not shown) into the interrupt return register 1339 for one clock period and by storing the address generated under the control of the E field into the KA interrupt return register 1339. It is carried out. The hardware generated address will be placed in the control store address register. Certain hardware/firmware-generated interrupts can be triggered by an interrupt block (not shown) that prevents additional interrupts in that class from being executed until the interrupt condition is met. , take priority. Firmware microoperations exist to control the interrupt program reset for sequences that are under firmware control.
These sequences under hardware control automatically generate a program flip reset at the end of the sequence. The following conditions, listed in order of priority, are present in this category. (a) Control store load (b) Control store scan (c) Hardware error (d) Software error - The remaining hardware condition does not set the interrupt program block, but causes a direct action when it occurs. .

The following conditions, listed in order of priority, exist in this category: (a) Initialize (b) Soft-clear (c) Entertainment maintenance panel (d) Entertainment maintenance panel (e) Hardware exit initialization signal is a binary 0 in CSUl3Ol
address, clear a hardware reset error, and perform a control store load operation, followed by a control store scan sequence under hardware control.

It also performs system initialization. The soft-clear signal causes CSU13O1 to address a binary 0, clear the hardware reset error, and set the interrupt proclock.
The enter maintenance panel signal branches the CSU to the address present in the CSU address switch on the maintenance panel (not shown). The entertainment channel signal causes the CSU to branch to the generated address via the maintenance channel (not shown).

The address to be transferred is one of the maintenance channels.
from the maintenance bus QMBl 344, which is part of the maintenance bus, and is justified. The hardware exit signal causes the CSU to branch to binary address 2. This sequence is used as a maintenance facility. At the end of the sequence, the return is the binary number 4
It is initialized by generating an E field branch with the E field set to . The control store load signal causes the CSU to branch to address binary zero.

It also stops the CSU read cycle flop (not shown), system clock 1320, and
Place SU in the load store. In the loaded state, the CSU:
Control store rotor CSUl3O3, IOCl3
O5, main memory 102, or maintenance 1355. When transferred from the CSU, an automatic scan is generated until the end of the load. When transferred from some other media, a scan can be issued either by generating a micro-operation signal on the maintenance panel or by setting a scan switch. The control store scan signal causes the CSU to branch to address binary zero. The control store scan is under hardware control during the sequence. During scanning, system block 1
320 is off, so no commands or tests are performed. At the end of the scan sequence, the hardware transfers the contents of interrupt return register KA to address register KS. The system clock is applied and control is returned to the firmware. The hardware error signal causes the CSU to branch to address binary 4.

In normal processing mode, a hardware error detected in the CPU functional unit activates a hardware error line (not shown). The control store sequence that is generated tests system conditions 9 to determine the action to be taken. Hardware error conditions detected in diagnostic mode are visible to microdiagnostics. Microdiagnosis controls the actions to be taken. On the other hand, a software error signal causes the control store to branch to address binary 1. This address is the start of the software error reporting sequence under microprogram control. Referring again to FIG. 13c, E field 1326 is a 3-bit field for the branch code, as previously described.

Blanching and/or micro-operation field 1327 may include A, . B. ．． C. ．． DlLl
field (shown in block 1335 of Figure 13b). In it, the A field is the top 6 bits of the next address, the B field is the middle 4 bits of the next address of the mask field on the one-way branch, and the C field is one of the 64 tests. The D field is a 6-bit test field for
Another 6-bit test field for one of the 4 tests, the L bit being the least important bit. The K field 1328 is a 14 bit field of which 6 bits are for constant fields, 4 bits are for constant or manipulated fields, and 4 bits are for constant manipulated fields. The data for bus field 1329 is QA of QMB bus 1344.
QA with 4 bits to control information for parts
The QB field consists of QMB bus 1344.
It has 4 bits for controlling information for the B part.
The F field is a 32-bit field coded to generate micro-operation subcommands. It is old. P field 1331 consists of 4 bits reserved for testing. In operation, the microinstruction word is stored in control store array 1.
Stored at 333.

During the operation cycle, the control. - The store array is addressed by the contents of the KS address register 1337. This causes the contents of the location specified by the address to be read into the group of read releases. The word content part of Reading Relaxation is C.
Within each of the functional units of the PU, it is allocated or transferred to storage registers. Each functional unit includes a decode logic circuit for generating the necessary subcommands defined by the control store word under control of the system clock source. Generally, decoding is performed centrally to minimize the decoding time typically required to transfer command signals and to reduce the number of cables, if decoding is performed centrally. Rather than being
It is implemented within each functional unit of the CPU. Therefore, decoding is performed within each unit to avoid timing problems resulting from differences in cable delays. Furthermore, by decoding subcommands in each unit, these signals representing certain conditions that exist within a functional unit can be
This is necessary for the generation of certain subcommands that should not be returned to unit 1302. A typical decoder unit 1359 is shown in Figure 13b as accepting various fields from the microinstruction word and generating microoperation signals A, b, c, d...Q, r. It is being used. A typical micro-operation 1359 receives commands from a micro-instruction word. Fields from the microinstruction word are decoded and distributed over multiple lines S, t
, u, . . . Y, z Set one of the altitudes. The matrix is s- at points α, β, γ...ψ, ω.
It is formed by predetermining the control line impedance coupled to the z-line. Then typically one of the lines sz goes high when the field from the microinstruction is decoded. The black points shown in the matrix by the Greek letters α to ω represent the impedance coupling between the two sets of lines, so the increase in electrical signal along the horizontal wires indicates the impedance coupling (black points). will be coupled in an increasing manner along vertical wires a-r. Each vertical line a-r is then
They can be combined as one input for each of the ND gates 1360-1365. Other input signals also include the timing signal Ts from the central timing unit and the AND gate 13.
60-1365 can be combined as one input for each one. Therefore, as each timing signal Ts becomes higher, these gates with all other input signal heights are enabled,
It will then provide microinstruction signals to predetermined functional units in the CPU. For example, if the command from read latch 1357 is decoded,
If the horizontal line is high, the A, b, cl and q vertical control lines will be high and the Ts timing signal will continue to be applied to these gates, so
AND gates 1360, 1361, 1362 and 13
64 is enabled. Thus, the combination in which the vertical control line is joined to the horizontal control line at each point drawn from the Greek letters controls the functional units within the central processing unit by the microinstructions provided by the control store array 1333. In order to do this, a permanent switching matrix is displayed for supplying micro-operation signals to the central processing unit. Thus, permanent firmware with changeability characteristics can be constructed in the machine of the invention by simply specifying the sequence of micro-operations required as a capability of the computer system. Under normal conditions, data is transferred to control store array 1333 via the CPU write data register, known as local register YOl343.
written inside. A control flop (not shown) defines whether the top or bottom half of the storage array must be written to. Data from the control and port unit (LUl3O4 arrives at the CIA/CSU via maintenance bus QMBl344 and is buffered by storage local register YOl343 before being written into control store array 1333. 1343 is a shared time as both a read and write local register.Multiplexer KQMl 345 can be controlled by either a maintenance panel 1355 or microdiagnostics and provides a read out path from the registers associated with it. Compare register KPl
35O is provided for non-functional use, primarily
Used for maintenance purposes, compare logic 1
352 and decode logic 1351. A description of the functions performed by the dispatcher is shown in flowchart FIGS. 14a-141.

For example, the description of the functions performed by the dispatcher 1402 of FIG. From I
Search PQM and scratchpad memory 131
5, the adaptive part of the CPU is controlled via an appropriate series of micro-operation signals 1360, 1361, etc. At the same time, the dispatcher retrieves the 1404G0 segment descriptor (Fig. 1
(see 2).

Bits 16-31 of the IQW word are (1) Q/
PR/RDYl Contains a positive integer of 16/<ite, which is the transfer to the head (first byte) of the queue in the ready process.
If bits 16-31 of the IPQW word are O, then the 140 bits are considered vacant.
If Preparation Kiyuichi is vacant, it is currently Q/PR/
Indicates that there is no process waiting in RDY and the ready queue is empty. Desi Shop Lock 14
The next question that must be decided in 05 is:
Determining whether the bakeant indicator is set determines whether a process is currently progressing within the machine. (The bakeant indicator is a flipflop located in auxiliary memory 1317a. It is set when there is no current process CJP progressing within the processor.)
If the bacant indicator is set (i.e., there is no process currently in progress), then
Since it has previously been determined that there are no processes in the ready queue waiting to use the processor, the machine proceeds in the idle state 1406.
However, if there is no process currently progressing in the machine, but no process waiting to use the machine, then the current process
Access 07. In relation to the decision shop lock 1403 of the float chart in Figure 14a, if IPQW (
That is, in the pointer area of bits 16-31),
If there is a positive integer, the head of the ready queue pointed to by the IPQW word in the GO segment is fetched into scratchpad memory.

(Note: To avoid repetition and clarity, the intermediate functions of the control unit and the dispatcher associated with the CPU will be omitted. However, by way of example, the intermediate functions as previously described are typically At this point, it has been determined that there is a process waiting in the readiness queue. Before any further action is taken, it is necessary to determine whether there are any processes currently underway in the central processor. This is measured at decision lock 1410 in the flowchart description. If the central processor does not have any processors currently in progress (i.e., CJP
), the head of the preparation queue will proceed 141
2. However, if there are processes in progress on the central processor, the dispatcher must decide who has priority...the processes currently in progress or the preparation queue. Is it the first head? Therefore, the progress process word of the system base 600 or the process main word 0 of the PCB4OO
The priority byte of the current process (CJP) located in PMW0 is retrieved 1413. A determination is then made 1414 as to whether the currently running process CJP has priority over the new process NJP waiting at the head of the preparation queue. (See Decishop Lock 1414) If CJP is not a lower priority than NJP, CTP remains in control of the central processor and the contest indicator is reset 1415. (Since the beginning of the last instruction is executed on behalf of CJP, thereby creating the possibility of a conflict, the contest indicator is always is set to 0. Under these conditions, the contest indicator is set to a binary 1.
) However, before the current process CJP is allowed to continue and execute further instructions, CJP enters decoder extension mode 1415.
Measures are taken to see if progress is being made. If C.J.P.
is proceeding in decoder extension mode, the next instruction is executed in emulation mode (ie, decoder extension). Then, if it is not proceeding in decoder extension mode, the next instruction is executed in native mode. Returning again to decision shop lock 1414, if the NJP at the head of the preparation queue has a higher priority than the CJP (i.e., its priority number is higher than that of the CJP).
If the priority number is lower than the priority number, it is the CJ that is currently in progress.
P is the “゜rollout” of the machine and the new process N
JP is a roll iso for machines. Therefore, by initially rolling out CJP under the command of firmware subroutine RLLOl4l9, L
The IF commands to queue the current process CJP in the preparation queue according to the priority order and priority number. The RLLO subroutine stores CJPs stored in general registers, base registers, scientific registers, T-registers, status registers, and instruction counters.
This information is written to the appropriate storage area of the process control block in main memory. It then commands an update of the RUA. Furthermore, P
Process main word 0 (PMWO) in CB4OO
) is updated 1420. The new process NJP is now prepared to be 64 rolled in 33.

The boundary address register BAR is fetched 1422.
The progress word PRW is then retrieved from the system base address BAR plus 56. See block 1423. The name of the new process NJP is then written into the progress process word RPW. The name of the new process NJP is written in the process link PL of Q/PR/RDY, so the process link PL
Therefore, the name is now RPWlProc 1
424. Therefore, NJP from preparation Kyuichi
is now CJP and is given the authority to control the central processor, so it also does not wait on Q/PR/RDY, but by taking its name from the process link PL of Q7/PR/RDYl process 1425. Kiyuichi must be released. When this is done, the preparation process queue Q/PR/RDY is updated by the farm subroutine UQLKll425a. Therefore, the JP number of the process removed from the machine is Q
/PR/RDY in the process link. This is because it is no longer under the control of the machine and must wait for it. 1426.

At this point, a transformation is accomplished in which this control of the central processor is given to the new process and the old process is placed in the preparation queue. Then, since there is a process (new CJP) in control of the central processor, the bacant indicator is set to 0,1427. On the other hand, if there is no CJP in control of the central processor, the bakeant indicator may be set to one. At this point, the processor's work is complete and the new process has acquired the central processor, while the old process has been placed in the reserve queue. However, the new process is also not ready to proceed. This is because general register 1307
, base register 1308, scientific register 1309, T
- The hardware of the central processing unit 1306 of FIG. 13a, such as registers 13101, status register 1311, and instruction counter 1312, must be provided with controller reinforcement from the process control program of the new process. Therefore, the firmware subroutine 1430 initially
From the PCB (Figure 4), scratchpad memory 1315
Then, take out the PMW3, and then take out the PMWO.

The MBZ field of the PMWO is examined. And if it is not a binary 0, it results in an illegal PCB exception. However, if the PMWO's MBZ field is 0, the PMWl is retrieved 1434
. Again, the PMW(1)MBZ field is tested to determine if it is a binary zero. If it is not a binary 0, there is an illegal PCB exception.
On the other hand, if it is equal to 0, the despatcher is C
Proceed to. Therefore, address space word 0ASW
0 is taken from the appropriate space on the PCB.

The segment table word size STWSZ is then tested 1437 to determine whether it is less than or equal to seven. If it is above 7, this results in an illegal PCB. If it is less than or equal to 7, ASWl is removed from PCBl block 1438 and its STWS
The Z field must be less than or equal to 8.
1439 is tested to determine whether it is equal to . If the field is 8 or more,
The result is illegal PCBs. However, if
If the STWSZ field is equal to or less than or equal to 8, the exception word EXW is retrieved 1440. The MBZ field is then tested to determine whether it is equal to zero. If the MBZ field is not equal to 0, then the result is an illegal PCB.
occurs. On the other hand, if it is equal to 0, the deposited word SKW is retrieved 1442. And that MB
The Z field is tested 1443 to determine if it is equal to zero. If the MBZ field is 0
, the result is an illegal PCB.
On the other hand, if it is equal to 0, instruction counter word 1CW is fetched from the PCB and instruction counter 1CW is fetched from the PCB.
placed in C. The TAG field is then tested 1445 to determine whether it is equal to zero. If the TAG field is not equal to O, then the M counterword is retrieved 1446. And that M? The field (bits 0-31) is tested to determine if it is equal to O. 1447.

And if it is not equal to 0 then the result is an illegal PC
B occurs. On the other hand, if it is equal to O, the deposited base words 0,1 and 2SBW0,1 and 2 are retrieved 1448. The contents of the 8 base registers (in base registers storing areas of the PCB) are then retrieved 1449 and stored in the machine's base registers 1308.

Thereafter, the contents of the one-carrier register from the general register storing area of the PCB are retrieved 1450 and stored in the general register 1307 of the machine. However, before retrieving the contents of the scientific register, we use 1451 to determine whether scientific mode is being utilized.
, a check is made regarding the capability bytes of process main load 0 (PMWO). If scientific mode is used, the contents of the scientific register are retrieved and stored from the scientific register storing area of the PCB.
52. Thereafter, 1453 to determine whether accounting mode is utilized. The firmware continues to check the PMWO's capability bytes. If accounting mode is utilized (i.e., the accounting bit in the capability byte is set to binary 1), the accounting word is present on the PCB and
The preparation time account word RTA is updated. The firmware then continues to measure whether the DEXT number is set to 0, 1454, if it is not set to 0, it indicates that the machine may be in emulation mode. (i.e. decoder extension capability is utilized). Therefore, the PMWO's DEXT number is checked 1455 to determine whether it is greater or less than the DETSZ field of process main word 3, and if it is greater than the DE'YSZ field: As a result, illegal PCB exception 14
56 occurs. Since the DEXT number is less than the DE thousand field, but not equal to 0, the machine operates in legal emulation mode. and proceed to F. Returning to the decision shop lock 1454, if the DEXT field is a binary 0,
Native mode is achieved and the machine retrieves the SBS. 1457.

The PCB's remaining timeout word RTO word is retrieved 1458 and the process
P is transported with a time limit consuming in progress.
Up to this point, (a) there is an old process C in the machine;
When JP is present and a new process, NJP, has a higher priority than the old process, CJP, the new process, NJP, takes control of the CPU.
Either it is rolled in, or the CJP is not in control of the CPU and the head of the preparation queue is progressing.

Briefly, under condition (a), CPJ was taken out of RPW and placed in process link PL of Q/PR/RDY. Process link PL(7)NJP in Q7/PR/RDY is placed in RPW. Thus,
I gave the NJP control that is +CJP, removed the control from the old CJP, and switched the 2-process position to effective. After that, NJP (7)
The PCB was accessed and the information required to proceed with the NJP was placed in scratch pad memory, or in the eye of a register in the ACU. If C
If there is no CJP in the control of the PU (conditional exit),
The first head of preparation is underway...i.e. N.J.
P became CJP due to the dispatcher taking the NJP from the process link PL from the head of the preparation queue and placing it in the RPW word.

By doing this, the process link PL becomes Q/P
Vacant in R/RDY. And it is required to take it out. Therefore, now starting with the decision lock 1461, the firmware measures whether or not CJP is in control of the CPU.

If a free process link (FRLS) was present, it was accessed and queued. and P
CB was written into it. However, if C
If CJP did not control PU, NJ
The state byte of P's PMWO is updated 1460.
Then, again, there is a measurement as to whether there was a CJP in the machine 1463. If CJP was not in control of the processor, the process link of NJP (which was in Q/PR/RDY but is now in control of the machine) would be taken from Q/PB/RDYl 446 (i.e. Q/PR/RDY is unified), and it becomes a free link signal FLSP,
It is currently queued in the free process link queue (805 in FIG. 9) and becomes part of the printer process link queue 1466a. Boundary address register BAR
The contents of are retrieved 1464. Then, NJP (currently CJP) located in System Base B, AR Plus 56
) progress process word RPW is in RPW block 14.
Updated by NJP's confirmation on 65. C.J.
If P is absent, the bacant indicator is set to O. Next, the contest indicator (i.e. CJP
and an auxiliary memory used to display possible conflicts in priority between processes placed in the preparation queue.
The flip-flop at river 317a) is 0,146
It is set to 7. and a segment alligiator (ASl3 in Figure 1), which is a typical content-addressable memory.
2) is cleared. 1471, after which the process mode is entered 1470.

(Process mode means that exceptions are handled by the process running on the processor, rather than by the operating system.) The firmware then
Followed by ABl48O.

The asynchronous trap bit AB is binary 1, 148.
Tested to determine if it is set to 1. If the AB bit is set to binary 1, a test is made 1428 to determine whether the process link number PRN is greater than or equal to the asynchronous trap bit ARN. (A
B and ARN are located in the priority byte of each process's PCB and are meaningful when the process is in progress. The pigeon and ARN are obtained from the RPW located at the system base BAR plus 56. RPW (7)
AB < 15 ARN in BAR Plus 56 is reset because the next step 1484 is an asynchronous trap routine that may affect the conditions that cause the asynchronous trap bit or ring number to be set in the first place. be done. If these are not set by the firmware on the next pass, it will give an indication that something is wrong when in fact there is nothing wrong, and therefore always They probably went ahead and never implemented it. Return to Decishop Lock 1481 and 1482,
If the AB bit is not set or
If the bit is set and PRN is greater than ARN, the firmware will continue to determine whether the processor will proceed in normal mode or emulation mode. Therefore, DEX
The T number is checked to determine if it is set to O. And if it is set to 0, the normal mode of the machine is proceeded. However, if the DEXT number is not set to 0, emulation mode will proceed.
86.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a program diagram of a multiprogramming device utilizing the present invention; FIG. 2 is an illustration of the various hardware mechanisms utilized by the present invention; FIG. , a legend of the terminology used for the reserved areas of storage in the registers depicted in FIG. Figure 4 is a schematic diagram of the process control program. FIG. 5 is a schematic diagram of an apparatus for addressing process control programs. Figure 6
is a schematic diagram of the system base of the present invention. 7A and 7B are illustrative drawings of the deposition segment and deposition frame, respectively, and FIG. 8 is a schematic diagram of the apparatus for addressing the G-segment and, in particular, for curating the process in the GO segment. be. Figure 9
1 is an exploded diagram of (1) segments illustrating process queues and process communications; FIG. Figures 10a to 101 are block diagrams of the features on the PCB. Figures 11a to 11r are block diagrams of the mechanism in the system base. Figure 1
2 is a schematic diagram that addresses the user's plan and also the system segments that utilize the system base and PCB features. FIG. 13 is a schematic diagram of the control unit. Figures 14a to 141 are flow diagrams of the dispatcher unit in the firmware. FIG. 15a is a diagram showing the time structure of the sundial JODl interval timer 1T1 and the process timer book. FIG. 15b is a configuration diagram of the accounting word of the PCB, FIG. 16 is a firmware update diagram of the running time account RUA, and FIG.
FIG. 6 shows a hardware diagram for updating time accounting WT entry and preparation account RTA. In the figure, the relationship between the main components and reference numbers is as follows. 1 to 4 are memory modules; 101 is a processor subsystem; 102 is a storage subsystem; 103 is a peripheral subsystem; 104 is a central processing unit; 106 is a peripheral control unit; 107 is a device adapter;
8 is the peripheral nip/output device.

Claims (1)

[Claims] 1 a central processing unit (CPU) that executes a plurality of processes (i.e., ordered execution of instructions) and a virtual memory, wherein a selected one of said processes is in progress (i.e., the execution of said CPU's control), and selected other processes of the plurality of processes are in multiprogramming mode, in preparation, waiting, or suspended states.
A computer system comprising: (a) a first data field (PCB 400, FIG. 4) in virtual memory, a portion of memory associated with each process processed in the computer system; (b) a system memory portion (system base 600, Figure 6)
and includes a second field (RPW, Figure 11j) providing the name and address of the process in progress, the second field providing the address (J,P) of the process in progress. a third field (1133 part, 11th part) for storing a predetermined first part (J) of
j) and the address of the process in progress (J, P
) for storing a predetermined second part (P) of (part 1133, FIG. 11j); and (c) when a process in progress is stopped. storing the contents of said CPU register in said first data field associated with this process;
a dispatcher mechanism 801, 802 controlling said system memory portion to copy into said CPU register the contents of said first data field corresponding to a process that is ready and taking control of the CPU;
, 803a-803g, and 905.