JPS6051943A - Series-parallel multiplier - Google Patents

Abstract

PURPOSE:To reduce the number of gates, and to reduce a circuit scale by constituting so that a result of addition is outputted successively. CONSTITUTION:When each bit of a data A1 is applied to a terminal 24, and the least significant bit x1 of a data X1 is supplied to a signal line 7a, each AND output is supplied to all adders FA1-FA4, and contents ''1'' of an FF8c are outputted to a signal line 29 by the next clock. When the next bit x2 is applied to the signal line 7a, addition is executed, and as a result, contents 2 of the FF8c are outputted to the signal line 29 by the next clock. When the next bit x3 is supplied, contents 3 are outputted to the signal line 29 by the next clock. Subsequently, contents of 4-10 are outputted successively to the signal line 29. In this way, multiplication of the data A1 and X1 is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION The invention relates to a series-parallel multiplier that performs multiplication between digitized data. Digital multipliers are broadly divided into series-parallel multipliers and parallel multipliers. These multipliers are described in the 14th volume of "Digital Signal Processing" (authored by Miyayo et al.) published by the Institute of Electronics and Communication Engineers in November 1975.
You can refer to pages 4 to 150.

The former inputs the first data all in parallel and the second data all in parallel, and the latter II'i inputs both the first data and the second data in parallel. Furthermore, the series-parallel multiplier has two circuit configurations as shown in FIGS. 1(b) and 1(C). In fig.

Reference numeral 101 is a full adder, reference numeral 102 is ant, p7
0. FF (FF) and the same number 103 are AND gates. Details of the full adder 101 are shown in FIG. 2, where:
i and Si are human input data *C1-1 is the m1 stage carry signal e Yl is the output signal C, is the carry number 1a.

Figure 1(b) 6C'! ? The critical path (path with a long signal propagation time) is composed of the full adder output Yi. 'Also. The method (pipeline multiplier) that divides the critical path with 7 lips and 70 tubes between full adders is R-F-LIUN's 2's Compl.
ement Pipeline Multiply −
ers''(IEFfl, Tranj, Com+nu
nication, VOI.

C0M-24, PP, 418-425. April
, 1976).

However, in such conventional multipliers, many 7 rip and 70 tug are considered safe for high-speed one hit,
There is a drawback that the overall circuit scale becomes large.The purpose of the present invention is to eliminate the above-mentioned drawbacks and create a multiplier that can perform the same number of multipliers and multipliers with a smaller number of gates than the conventional pipeline multiplier. It's all about providing.

The inventive multiplier uses the first bit of the binary encoded
and second data are input in series and parallel, respectively, and a series-parallel multiplier for performing all multiplications of the it data and the second data is inputted to the first and second input terminals, respectively. and multiple AND circuits that are given data.

a signal line through which first input terminals of the plurality of AND circuits are all commonly connected and the first data is propagated;

The corresponding output of the AND circuit is applied to the first input terminal, the addition output from the subsequent stage is applied to the second input terminal, and the carry signal is connected to the carry No. 1a input terminal of the subsequent stage. a plurality of full adder circuits, and at least one full adder circuit inserted at at least one predetermined location on the line 1a.
at least one second temporary storage means for temporarily storing the carry signal from at least one of the plurality of full adder circuits and outputting it to a subsequent full adder; It is equipped with

The present invention will now be described in detail with reference to drawing t.

FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a time chart showing No. 1a of each part in FIG. In the non-embodiment, a delay type control 7 is connected to each first input terminal.
8 logical products (A
NI))Ge) 2a and 2b and the first input terminal is 1
A No. M7a is connected and the second input terminal is grounded (logical
0') and the first control signal applied from the terminal 26 is "1", the input to the first input terminal is connected to the signal line 1.
Output to 2a and 81! When the control 1 of l is logic 10'', the selector l outputs ``'o'', and the first input terminal is connected to the output terminal of the selector l, and the second input terminal is AND (2a). Eight exclusive OR (EX-OR) gates 3a connected to the output terminal of the workpiece 2b
and 3b, the first input terminals of which are ax-on,
9 delay type 75-lips connected to the output terminals of 3a and 3b and each connected in cascade to receive the addition outputs of the 9 fc full adders FAI to FA9 and the valley full adders FAI to 1-A9. The first input terminals of the flops 8a and 8b are connected to the output terminals of the troughs 8a and 8b, respectively, and the output terminals are connected to the full adders Ii'A1 to FA3'.
J? Seven ANI) gates 8a, 23b and 8c are connected to the circuits FA5 to FAg, respectively, and the full adders FAI to f'A are connected to the first input terminals via seven lip-flops Ba, Bb and 8C. 6 selectors 27, 10a and 10b which output the human power to the first input terminal only when the signals on the signal lines 28, 30M and 30b are logic @1''; 108
and four delay-type 7-lip 70-tubes 11 inserted between the second input terminal and output terminal of 10b, and EX-(
JR game) 3b is connected to the second input terminal of the fc signal line 12b, and the AND gate 9a! and 9b (D second (D signal lines 13a and 13b connected to the D input terminal), a dividing circuit 14 provided for dividing the carry signal path,
Signal line 1 in which delay type flip 70 tubes 15 are inserted
It consists of 6. Furthermore, the 5-divider circuit 14 is composed of delay type 7-lip 70 tubes 176--21, an ANI gate 22, and an inverter 23.

Next, the operation V of the non-embodiment will be explained. 8-bit data AH (as, a7. aa, as, a4. a
a, a2°ax) and 3-bit data x1 (X3.
X2. Consider multiplication with XI) (X3 is the sign bit). This multiplication is performed as shown in FIG.
10-bit multiplication result Y, (yto,...'s
)” ) is obtained.

In FIGS. 3 and 4, each bit of the data Al is applied to the signal line 16Vci[column by valving the terminal 24;
Next, when the lowest pitch (xl) of the stored data can get. At this time, when the selector l sets the terminal 26 to logic "0" so as to select and output the input 'fr: to the second input terminal, the obtained logical product outputs are l(
X-OR, gate) 2a and full adders A1 to Ii
'Given to A4. At this time, since the signal line 13a is at logic "0", the outputs of the valley full adders FAI-F9 are as shown in the first column of FIG. Further, the outputs of the full-power multipliers FA1 to FA4 are stored in the flip-flop 8a at the same time as the primary clock. , the first input terminal 'l-7, the 8th valley (6th
The value (■) in the figure (y1=81x5) is output to the signal line 29. In addition, xl and logic 10'' are stored in the clip-flops 17 and 18, respectively, and are output to the signal lines 7b and 12b, respectively, and p)xl is given to the terminal 25, similar to the case of bi!1l)Xl. iC@
The logical pile output is given to the adder F A I - F A4. This and 'f! , in each of the full adders FAI to FA4, the addition result of the subsequent full adder and the AND output are added, and the result is output to each Furi, Pflodp 8a and 8C, and when there is a one-digit carryover, outputs a carry signal to the subsequent full adder. Each full adder FA5 to FA
9 outputs the AND of bit x1 and the contents of valleys 7, 7, and 7, respectively. Valley full adder 1i' at this time
Write the outputs of A 1 to F A 9 in the second column of Fig. 6.
In the next cycle, the output of the full booster FAI is stored as 7 rip 70 lub 8CK, and this 7 rip 7
0 Tube 8C (1) Contents (I1i (Yz”a of ■ in Figure 6)
sXs +atXs )) is output to the other pair of wires 29.

7 at the same time) x3 is given from terminal 25, but
Since l is a sign bit, selector 1 selects all the input terminals of @1 in order to display the complement by logic ``'' terminal 26.
1''. At this time, full adders FA1 to Ii'& 9
From this, the output shown in column 3 of FIG. 6 is obtained. Furthermore, at the next clock, (grain value (3'5=at
X1"asXs+arXs) is output to the signal line 29 at the 0th order, selector 2'lt, signal i[16!
Since the signal line 30a becomes logic "0", the selector 10a is switched to selectively output the human power to the second input terminal, and since the signal line 30a becomes logic "1", the selector 10a selects the input to the first input terminal. Switched to output all selections. As a result, llα(Y+=a* Xs + asXz
10a x @) outputs to No. 11 #29.
, 9- At the next clock, selectors 10a and 10b set signal lines 30a and 30b to logic IIO'' and 1, respectively.
1'', the inputs to the second and first input terminals are switched to be selectively output, and the 61st value (Ys=as a4+aaXs+alXl) is output to the signal line 29. Similarly, at the next clock, the value of ■ in Fig. 6 (Y s = aaXt + a@x@ + a
aXs) is output from the signal line 29. Below, the values of (ri and @ in Figure 6) (7g==a@XI +a
HatakeX2 +ayXs and)'to ” as X++
a @ In this way, the multiplication of data A1 and Xl is completed. In the non-example, the case where data AI and Xl are each 8 bits and 3 bits, and the output is lθ bits is described, but other bit numbers may be used. However, it is also possible to insert the tubes 17 and 18 at multiple locations.

Second, the present invention has the advantage that it is possible to completely reduce the scale of the circuits constituting one multiplier.

[Brief explanation of the drawing]

Fig. 1 is a diagram to clarify the conventional example, Fig. 2 is a diagram showing the details of the full-length chrysanthemum device, Fig. 3 is a 1ρ1 road diagram showing an embodiment of the present invention, and Fig. 4 is The diagram showing the timenayat and FIGS. 5 and 6 are diagrams for explaining the embodiment. In the figure, 1, 27. 1 (J a, 10 b, ,,,,
Selector, 2a. 211, 9 a, 9 b, 22 =...ANI) Gate, 3a. 3 b =----E X −(J l(, gate, 6
a, fil), 8a. 8b, He, 11, 15, 17, 18, 19, 20°2
1...Flip-flop s 7as 7b, 1
2a. 12b, 13a, 13b, 16, 28, 29, 30a. ：＋ o b・・・・・・Liquor fklb 24.25.
26...Terminal. 232-

Claims (1)

[Claims] In a series-parallel multiplier, a plurality of binary-encoded first and second data are input in series and in parallel, respectively, and multiplication of the first data and second data is performed. a plurality of AND circuits to which the first and ifg2 data are respectively applied to two input terminals; and an interface in which the first input terminals of the plurality of AND circuits are all commonly connected and the first data is propagated. A pair of wires and the corresponding output of the AND circuit are given to a first input terminal, an addition output from a subsequent stage is given to a second input terminal, and in the case of a carry, the signal is sent to a carry signal input terminal of the subsequent stage. a plurality of full adder circuits connected to give
and at least one second temporary storage means for temporarily storing the carry signal from at least one of the plurality of full adder circuits and then outputting it to a subsequent full adder. A series-parallel multiplier with all the following features.