JPS6051716B2 - voltage divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When three or more potential levels are required, such as in a dynamic type (dynamic or scanning type) liquid crystal drive circuit, the present invention is applicable to This article concerns a voltage divider circuit for obtaining .

In recent years, in various digital electronic devices such as electronic desktop calculators, electronic circuits are integrated into so-called complementary circuit configurations formed by P-type and N-type dual channel IG-FETs (MOS transistors). Furthermore, there is a strong demand for lower power consumption and smaller sets by using liquid crystals (LC) as display devices.For example, calculators can already be used for 1,000 to 150 hours without the need for battery replacement. have been commercialized.

On the other hand, due to the chemical properties of this LC which is excellent in reducing power consumption, it is important to apply an alternating voltage to it and to reduce the integrated voltage component to zero in order to extend its life.

By the way, one electrode of a plurality of LC segments is made common (for example, for each display digit), and the other electrode of the segment is made common among different segment groups in which the one electrode is made common. In a dynamic drive method that selectively scans each shared segment group in a time-division manner, the response speed of the LC is extremely slow compared to other display devices, so when dynamically driving an LC, three or more voltages are usually used. A drive signal with a level is required. Therefore, if this voltage level is obtained within an integrated circuit, the power consumption of the circuit for this is large.
The excellent characteristics of low power consumption of the LC display device could not be fully utilized. Furthermore, when obtaining a voltage level between the highest and lowest of the three or more voltage levels from outside the integrated circuit, it is difficult to reduce the number of individual components, which is inconvenient for downsizing and cost reduction of electronic equipment. It was hot. The present invention has been made in view of the above circumstances, and by making it possible to obtain within the integrated circuit a voltage level between the highest voltage level and the lowest voltage level used within the integrated circuit.
The present invention provides a voltage dividing circuit that reduces the number of individual parts, enables lower power consumption, and is suitable for reducing power consumption in the lower layer by lowering the voltage.

Embodiments of the present invention will be described below with reference to the drawings.

In addition, in the following explanation, the low level (upper o level) is established (also called logic ゜゜1゛ or set), and the high level (
A negative logic is used in which the ground level (ground level) is not established (also referred to as logic "0" or reset).Figure 1 shows the dynamic driving method of LC, of which 1/3 duty (Duty),
This is an example of wiring an LC display section using the 1/3 Prebias method, where the display digits are composed of 8 segments per digit (7 segments arranged in a Japanese character arrangement and 1 segment for the decimal point) in a calculator etc. showed that. Figure 2 is.
Fig. 1 is an equivalent circuit diagram of the liquid crystal segment, Fig. 3 is a signal waveform diagram for driving the LC in Fig. 1, and Fig. 4 is an N
1 is a schematic configuration diagram of a calculator or the like using a circuit according to an embodiment of the present invention in which a type semiconductor is integrated as a substrate. In FIG. 2, CLO represents the capacity of LC, and RLO represents the country's leak resistance. The capacitance CLO is usually from several PF to several 109 F' per segment, and the leak resistance RLO is 100 MΩ or more.

In FIG. 4, reference numeral 10 denotes a power source, which is connected to a high potential power source end 11 and a low potential power source end 15, which are power receiving ends. The low potential is set to -FO [V] level.

20 is a logic section that operates between the ground level and the upper O level, and this logic section includes a basic timing generation circuit for pressure display, a decoder circuit that converts the data signal in the BCD code into each pressure component drive signal, calculation part of a calculator, etc.
Consists of clock circuits, etc. in watches.

30 is a voltage dividing circuit, and this circuit 30 is connected to the terminal 11.
, 15, the first resistor and the first switching means (M
OS transistor or InsulatedGate
FleldEffectTranslstOrI
G-FET) are connected in series, and a second
The resistors connected are connected as a unit, and these are connected in a row at four single positions.

The above units are indicated by U1 to U4, the first resistors are Rll to Rl4, the first switching means (transistors) are Pl, P2 and N3, N2, Nl, and the second resistors are R2l to R24. shown. A pulse φ, which will be described later, is applied from the circuit 20 to the gates of the P-channel transistors Pl and P2, and the N-channel transistors Nl and N
2″″, N3 is supplied with an inverted pulse A of pulse φL via an inverter 21, and the connection end 12 between the units,
13, 14 to -114E0, -11 sand. , -314E
It is designed to obtain a voltage of 0. Here, both types of transistors are integrated using the same semiconductor (in this example, an N-type semiconductor) as a base.
The substrate electrodes of all P channels are the same as the substrate and have the highest potential of 0. On the other hand, an N-channel transistor has a P-type semiconductor region (current-carrying P
-Well), the P-Well
By separating the N-channel transistors into individual N-channel transistors, the substrate electrodes can be arbitrarily connected. Therefore,
By connecting the substrate electrodes of the N-channel transistors N1, N2, and N3 independently to the end of the channel of each transistor near the low-potential power supply, or the resource end, as shown, the transistors become suitable for low-voltage operation. Figure 5 shows
It is a cross-sectional view showing the structure of these integrated double channel type transistors, 21 is an N-type substrate, 22 is a P-Wel.
l region, S is source, D is drain, G is gate, Sl
lb is a substrate, 23 is a P-channel transistor, 24 is an N-channel transistor, and 25 is an insulating film.

Further, in FIG. 4, 40 indicates signals H1 to H3, α1 to α8, and β for driving the LC display section 50 shown in FIG.
This circuit 40 is a (1) drive circuit that generates signals h1 to β8 and γ1 to γ8, and this circuit 40 generates signals h1 to H from the logic section 20.
3, W, etc. as input, a circuit group consisting of a ground potential, an upper potential, and three potentials derived from a voltage divider circuit 30, for example, a phase suitable for low voltage driving of an LC as shown in FIG. Signals α1 to α8, β1 to β8 using an inverter 41 etc.
, γ1 to γ8 (here, only the circuit that obtains α1 is shown) or a circuit 43 that provides a multi-level output suitable for low voltage driving of an LC as shown in FIG. 7 is used to generate the signal H1.
It has a circuit that outputs H3 (here, only the circuit that obtains H1 is shown). Next, before explaining the operation of the voltage dividing circuit 30, each waveform in FIG. 3 and the operation of the LC will be explained. φo is a pulse generated for a certain period of time at the start of one display cycle, and defines one cycle of display. Although the desirable period of the pulse φ varies depending on the characteristics of the LC, etc., it is generally considered to be 2.4 msec. The pulse width of φL is determined by the circuit configuration within the logic section 20 or the characteristics required of the circuit 30, but here it is assumed to be 25 μSec. Hl, h2, and h3 are pulses that specify the scanning timing of the scanning pulses Hl, H2, and H3. For example, when the pulse h1 is established, the pulse h1 is set to the selection level (A) [■], -EO [■]), and when the pulse h1 is not established, the pulse h1 is set to the non-selection level (-■M1=-112E0). w is the pulse Hl, H2, H3 is Hl, h2, h3
This is a pulse that specifies the polarity of the selection level and the polarity of the segment signal when the scanning timing is reached. That is, when the pulse w is established, the pulse Hl,
The selection level of H2 and ratio is 0 [■], and when the pulse w is not established, the selection level of pulses H1, FI2, and H3 is 1EO [■]. Each segment signal is at the display level at the -314E0 level when the pulse w is established during the corresponding display cycle, at the non-display level at the '6+3 level, or at the -114E0 level, and when the pulse w is not established. Each segment is driven as a display level at the '6-'3 level, that is, the -314E0 level, and as a non-display level at the 66+2' level, that is, the -114E0 level. α1-1,
α1-2 and α1-3 are the respective positions in which the segment SE1 of the first digit in FIG. The voltage applied to the segment is shown based on the common terminal. That is, the segments in which the applied voltage alternates in timing at 314E0CV] are in the display state, and the segments in which the applied voltages also alternate in timing at 114E0CV] are in the non-display state. However, the conditions required for the drive waveform are that the leak resistance RLC per segment is usually 100 MΩ or more, and the LC is several PF to several tens of pins.
Since it is a capacitive element of F, firstly, the output resistance of each level may be of any value as long as it can sufficiently compensate for the leakage current by the RLO. In other words, if RLO is ±300MΩ, it can be increased to about 400kΩ, which is sufficiently small compared to 10MΩ.
Each output resistance of ~γ8 may be a higher resistance. The second condition is that the LC is capacitive so that each drive signal can successfully switch the LC capacitance during switching. That is, if the capacitance CLO is 30 pF, the pulses H1 to H3 in FIG. 1 need to drive a capacitance of about 1000 pF, so the output resistance must have a sufficiently low resistance. For example, if the output impedance for the 112E0 level of the pulses H1 to H3 is 400 kΩ, which is much larger than the output impedance for other levels, the operating waveform of the pulses H1 to H3 will change to the switch state to the -112E0 level in FIG. The delay time constant shown by this dotted line to reach the state shown by is 400k
Ω×1000pF=400μSec, and due to this delay, the segment applied voltages α1-1, α1-2, α1
The -3 state still results in a dotted line waveform. As a result, the segment SE1 in FIG. 1, which is originally in a non-display state, is not displayed properly, that is, it is not completely displayed but is displayed in a weak display state, which is extremely inconvenient. It will be fully understood from the following description that the present invention takes into consideration the improvement of such problems, and that it is capable of stably operating an LC and is suitable for low voltage operation. "The output resistance for the LC drive signal is represented by the sum of the internal resistance of the power supply source and the output resistance of the LC drive circuit, but it is important to note that the output resistance for the LC drive signal is the sum of the internal resistance of the power supply source and the output resistance of the LC drive circuit, but it is important to note that the output resistance for the LC drive signal is the sum of the internal resistance of the power supply source and the output resistance of the LC drive circuit section. The output resistance can be easily increased or decreased depending on the dimensions of the elements constituting the circuit, such as MOS transistors, and can be considered operationally negligible compared to the internal resistance of the power supply source. Voltage divider circuit 30
This is the equivalent circuit of

That is, the resistance value is set to 1=Rl2=Rl3=Rl4+40kΩ, and the on-resistances of transistors Pl, P2 and N3, N2, Nl are set to a small value that can be ignored compared to the above resistance value, or the on-resistance of transistor P1 is and the sum of Rll,
On-resistance and Rl of the parallel circuit of P2 and N3. , the sum of the on-resistance of N2 and Rl3, and the sum of the on-resistance of N1 and Rl4 may each have the same resistance value of 40 kΩ. and R2l
=R23=R24+400kΩ, when transistors Pl, P2 and N3, Nl, N2 are both turned on, switches SW-1 to SW-3 are closed, and when transistors Pl, P2 and both N3, Nl, N2 are turned off, switches SW-1 to SW-3 are closed. -1～
It is easily understood that when SW-3 is open, the circuit 30 of FIG. 4 becomes as shown in FIG. 8 based on Thevenin's theorem.
Here, the power source 10 is a battery 10-1 of 114E0 [■],
It is shown by a series circuit of 10-2, 10-3, 10-4, and the internal resistance to the output voltage (-114E0 [■]) of the output terminal 12 is the transistor Pl, P2, Nl, N2, N3.
When both transistors are turned on, the parallel resistance becomes 30kΩ and 300kΩ, and when both transistors are turned off, the resistance becomes 300kΩ. Furthermore, the internal resistance to the output voltage (-112E0CV) of the output terminal 13 is 40kΩ40 when the transistor is on.
0kΩ parallel resistance, 400k when transistor is off
Ω, and the output voltage of the output terminal 14 (-314E0C
The internal resistance to V) is a parallel resistance of 30 kΩ and 300 kΩ when each transistor is on, and 300 kΩ when the transistor is off. Transistors Pl, P2
, Nl, N2, N3 have at least LC
In order to turn on these transistors for a certain period of time at the start of one display cycle, the gates of transistors Pl and P2 are supplied with 25
A pulse φ having a pulse width of μSec is applied, and a pulse WL as a complement of φ5 is applied to the gates of transistors Nl, N2, and N3.

Therefore, the drive signal switch for each country is 1-112E0 [■
] for the switch to 100 with an output resistance of 40kΩ.
Since it drives 0 pF, the time constant is 40 psec12-11
As for the switch to 4E0CV] or -314E0[■], since 1000pF is driven with an output resistance of 30kΩ, the time constant is 30psec, which shows good characteristics against "゜display leakage." is not established, and when FET Pl, P2, Nl, N2, and N3 are turned off, each output level is slightly -112E0 [■],
-114E0 or -314E0CV] level, the resistor 400kΩ, 30Ω shown in Figure 7
Along with switching to each level at 0kΩ and 300kΩ,
These resistors compensate for the leakage current of the LC and drive the LC stably. In the case of dynamic display method,
Power supply voltage E.

Usually, 2.5 to 10 [■] is used, but 3.0 [■] or 4.5 [■] is often used to reduce power consumption. Now E. Voltage divider circuit 30 as = -4.5 [V]
The average current consumption is approximately 3.3 μA. On the other hand, in a calculator, the current consumption of the logic section 20 is generally about several tens of μA to 200 μA, so even when dynamically driving an LC, the current consumption required for this is ignored compared to the current consumption of the logic section 20. This is effective for energy saving. And in recent years,
Since ion implantation technology has been introduced to the manufacturing of integrated circuit chips, it is possible to stably form a semiconductor layer with a low impurity concentration and a shallow thickness of about 1 μm from about 1000 A on one main surface of a semiconductor. Each resistor in the logic section 20 and the LC drive circuit 4, regardless of its size,
Since it can be stably integrated on the same chip as 0, it is extremely effective in downsizing electronic devices and further reducing the number of lead terminals of integrated circuits, improving characteristics (reliability) and reducing costs. Note that the arrangement of each transistor in FIG. 4 is not limited to the case shown in the figure, and the order in which the resistors and transistors are connected may be reversed. However, considering the operating characteristics of each transistor, N It is suitable for low voltage operation that channel transistors N1 and N2 are placed closer to low potential power supply 15, and P channel transistor P1 is placed closer to high potential power supply 11.

In addition, since the substrate electrodes of the N-channel transistors Nl and N2 are connected to the electrode located at both ends of the channel path of each transistor, the electrode on the side closer to the low potential power supply end 15, or the resource end, there is a gap between the source electrode and the substrate electrode. The back gate bias effect due to the potential difference that exists at the transistor's threshold voltage (ThreshO
ldVOltage) is modulated in a direction that increases the enhancement characteristic.

Then, for the P-channel transistor P2 whose back gate bias effect cannot be removed, an N-channel transistor N3 is connected in parallel, and its substrate electrode is connected to the N-channel transistor P2.
It can be understood that the circuit of the present invention is suitable for low voltage operation because N3 has the effect of compensating for the characteristic deterioration of P2 by connecting it to the terminal resource on the electrode 15 side of the channel path in the same way as N2. FIG. 9 shows another embodiment of the present invention, in which the fact that LC is capacitive is actively utilized.

That is, in FIG. 1, if the leak resistance at the supply end of the pulse H1 is 10 MΩ or more and the load capacitance is 400 PF, the fluctuation in voltage level caused by this leak resistance will have a time constant of 4.
It is indicated in msec. Therefore, the voltage divider circuit 3 in FIG.
The opening/closing means φL, iL of each transistor of
μSec), pulse φL with pulse width of 25 μSec
'' and its complement pulse IL'', it is possible to stably operate the LC without using the resistors R21 to R24 of the voltage dividing circuit 30. The current consumption in this case is EO
= -4.5■, it becomes approximately 1.5 μA, which further improves low power consumption characteristics. FIG. 10 shows an embodiment that has even better low power consumption characteristics than FIG. 9.

That is, resistors R2l and R2. , R23, and R24 are connected in series with transistors serving as other switching elements, thereby reducing power consumption. For example, a P-channel transistor P4 whose gate input is a pulse φL'' in series with a resistor R2l is connected to a P-channel transistor P4 whose gate input is a pulse φJ in series with a resistor R2l.
A parallel circuit of an N-channel transistor N6 whose gate inputs are 5 and pulse BL'' is connected in series to a resistor R24 by a pulse i.
N-channel transistor N4 whose gate input is
An N-channel transistor N5 having a gate input of a pulse IJ is connected in series with the resistor (2), or a parallel circuit of R-channel transistors P6 and N5 having a gate input of φJ is provided. In this way, each of the above transistors P4, P
While 5, N6, N4, and N5 are 0FF (off), there is no pulse. ~Since no current flows through R24, the power supply voltage is E. =
-4.5■, the power consumption can be reduced to about 0.5μA or less. In the embodiments shown in FIGS. 4 and 10 above, for example, the series circuit of the resistor Rll and the transistor P1 is provided with the resistor R2l or the series circuit of the resistor R2l and the transistor P4. 1 or a series circuit of this and transistor P4 may be connected in parallel only to transistor P1.

This means that resistor R22 or it and transistor P5
The same applies to the parallel circuit of R23 and N6, the resistor R23 or the transistor N5, and the resistor R24 or the transistor N4. Fig. 11 shows an example in which the LC is driven using four potential levels with a duty of 1/3, and Fig. 12 shows its operating waveform (pulses h1 to H3 and φ are omitted). It is.

That is, in each of the above embodiments, the unit U1 is connected in parallel with the P-channel transistor PlO, which receives the inverted pulse W of the polarity specifying pulse w as its gate input, and the unit U4 is connected in parallel with the N-channel transistor Nl, whose gate input is the pulse W.
O are connected in parallel, and the potential level of the output terminals 12 to 14 changes with the same polarity as the pulse w, as shown in FIG. Therefore, the on-resistance when the pulse W is established and the transistor PIO is on is smaller than the sum of the resistors R, 2, R, 3, R, and 4, and the on-resistance when the pulse is not established and the transistor PIO is on. is smaller than the sum of resistors Rll, Rl2, and Rl3. The circuit configuration of the LC drive circuit 40 in this case is the fourth one.
The configuration illustrated in the figure may be used. FIG. 13 shows an embodiment aimed at further reducing the power consumed for LC display.

That is, when changing the normal LC display state to a predetermined specific display state such as all segments being lit or not lit after a certain period of time has passed, each unit U as shown in FIG.
A specific display state can be achieved by interposing at least one switching means (transistor) for closing the paths 1 to U4 for a certain period of time and opening them for other periods in order to achieve the normal display state. The current consumption in the voltage dividing circuit during this period is kept at about the level of leakage current. Here, the control signal T, which is one means for setting the above-mentioned (1) to a specific display state, is transmitted to the logic section 20 in FIG.
In the clock circuit or frequency dividing circuit, RS-Fllp-Fl
When the signal T is established, the display state is a normal display state, and when the signal T is not established, the display state is a specific display state. FIG. 14 shows the signal T and the corresponding potential states of the terminals 12 to 14. In this case, as shown in FIG. 14, when the signal T is reset, the terminals 12 and 13 are at the ground level, and the terminal 14 is at the upper o level, so in order to make the integrated value of the voltage applied to each LC segment during this period zero, This is accomplished by controlling the input signals of the drive circuits shown in FIGS. 6 and 7 using signals T and 〒. For example, if we use h1+〒, H2+〒, H3+〒 and their inverted pulses instead of the pulses Hl, h2, h3 and their inverted pulses as the drive circuit inputs of Hl, H2, H3, then the signal T Only HL
, H2, and H3 each operate between ground and upper O level, and output the inverted level of the signal w. Therefore in this case, the output of the segment signal drive circuit is grounded and on. If the inverted output of W having a certain level is used, all LC segments can be satisfactorily rendered non-displayed. On the other hand, if a signal having the same polarity as W and having the ground and upper O levels is obtained as the output of the segment drive circuit, all LC segments can be brought into a good display state. Alternatively, Hl
, H2, and H3 are fixed to either ground or upper O level when the signal T is reset, and all segment signal drive circuit outputs are fixed to the same level as H1, H2, and H3, thereby reducing the applied voltage of all segments. It is possible to set all segments to a good non-display state by constantly setting the value to zero. In this case, as shown in FIG. 15, when T is reset, the N-channel transistor N3O whose input is
By cutting off the voltage supply to the voltage supply end to the upper o supply end of FIG. 7 that generates H2 and H3, the signal level applied to the electrodes of all LC segments can be easily grounded. Note that N3O of P-channel transistor P3O is 0.
When in the FF state, it turns ON and fixes each electrode of the circuit 30 to the ground level. Note that the present invention is not limited to the above-mentioned embodiments, and may be applied to, for example, low resistance Rll, Rl. , Rl3, Rl4 may be connected in series with forward diodes having the same characteristics, and the high resistances R2l, R22, R24 may be connected in series with forward diodes each having the same characteristics. In this case, especially the resistance 21, R22, R23
, R24 have the same resistance value, the voltage applied to each resistor is about 0.5 to 0.7 V less than the forward voltage of the diode, making it possible to reduce power consumption. Since no current flows until it is applied, power consumption can be reduced in this respect, and by providing a diode, the integrated circuit area required for high resistance can be greatly reduced. Furthermore, in each of the embodiments, a case has been described in which an N-type semiconductor is used as a vapor to form an integrated circuit, but a P-type semiconductor may be used as a base. In this case, the P-channel type 1G-FET is replaced with an N-channel type 1G-FET, and each voltage level -114E0
, -214E0, -314E0, upper o to 114E0 respectively
, 214E0, 314E0, E0, etc. Further, in the embodiment, a case has been described in which the number of units is four, U1 to U4, but the number of units is not limited to this, and for example, a configuration may be adopted in which unit U3 is omitted. In addition, in the embodiment, one parallel circuit of the IG-FET of the unit was provided in order to enable low voltage operation.
The present invention is not limited to this, and a parallel circuit of the 1G-FET may be provided in a plurality of units other than the units disposed at both ends of each unit connected in series. As explained above, according to the present invention, power is supplied to a low-resistance series circuit, and then the leakage amount is supplemented by a high-resistance series circuit, and the on-resistance of the IG-FET, where a back gate bias effect occurs, is reduced. Since the IG-FETs are connected in parallel and the substrate electrode and source end of the other IG-FETs can be connected, good LC drive, low voltage operation, and low power consumption are possible. and I
Since the G-FET can be incorporated into an integrated circuit together with other circuits, it is possible to provide a voltage dividing circuit that can be easily miniaturized and integrated into an integrated circuit.

The simple explanatory diagrams in the drawings are for explaining the embodiments of the present invention, and FIG. 1 is a wiring diagram of the LC display section, FIG. 2 is a partial equivalent circuit diagram, and FIG. FIG. 4 is a circuit diagram showing an embodiment of the present invention, FIG. 5 is a partial integrated circuit structure diagram thereof, FIGS. 6 and 7 are LC drive circuit diagrams, and FIG. 8 is a time chart showing the operation. FIG. 4 is an equivalent circuit diagram of the voltage division circuit section, FIGS. 9 to 11 are circuit diagrams of other embodiments of the present invention, FIG. 12 is a time chart showing the circuit operation of FIG. 11, and FIG. 13 is 14 is a circuit diagram of a different embodiment of the present invention, FIG. 14 is a time chart showing the operation of the same circuit, and FIG. 15 is a circuit diagram of still another embodiment of the present invention.

11, 15...Power supply terminal, 12-14...Output terminal, 30...Voltage divider circuit, Rll-Rl4...Low resistance, R2l-R24...High resistance, Pl, P2, Nl,
N2, N3...IG-FET.

Claims (1)

[Scope of Claims] 1. A circuit in which a plurality of IG-FETs with low resistance and a certain channel type are connected in series as a unit, and an IG-FET with low resistance and a channel type different from the above-mentioned channel type. - FETs connected in series are used as a unit unit, and one or more series units are connected in series between the first and second potential supply terminals, and each unit unit connected in series is connected in series between the first and second potential supply terminals. I of at least one unit other than the units placed at both ends in
G-FET with a channel type different from its channel type.
A signal supply end that connects G-FETs in parallel, connects the substrate electrode of the IG-FET to the source end of the IG-FET, and turns the gate of each IG-FET on or off simultaneously. , and the series connection end between the units is used as a divided voltage output end. 2. A unit comprising a series circuit in which first IG-FETs of low resistance and a certain channel type are connected in series, and at least a high resistance is provided in parallel to the series circuit or the first IG-FET. A series circuit is provided in which a plurality of units of this are connected in series, and a second IG-FET with low resistance and a channel type different from the channel type is connected in series, and the series circuit or the second IG-FET is connected in series. A unit unit consisting of at least a high resistance provided in parallel is connected in series between the first and second potential supply terminals, and one unit or a plurality of series units are connected in series between the first and second potential supply terminals, and the series-connected IG-FE of at least one unit other than the units arranged at both ends in each unit
IG-FE of a channel type different from that channel type to T.
T are connected in parallel, and the substrate electrode of the IG-FET is connected to the source end of the IG-FET, and each of the IG-FETs is connected in parallel.
1. A voltage dividing circuit characterized in that the gates of the FETs are connected to signal supply terminals that simultaneously turn on or off the IG-FETs, and the series connection terminal between the units is used as a divided voltage output terminal.