JPS6051011A - Synchronous detecting device - Google Patents

Abstract

PURPOSE:To compensate and reduce an error caused by a residual phase modulation noise and an addition noise by poviding a phase lock loop having a constant loop filter band width, and also providing an effective value detector. CONSTITUTION:In a loop filter 408, a micro-processing device varies an effective value of a feedback resistor 404 by using a multiplication type D/A converter 402. In this case, if a capacitor 406 is large enough, a constant transfer function H(S) is shown, and a PLL band width of a synchronous detecting device is kept constant irrespective of an input signal level, by which an error induced by a phase modulation is eliminated. Also, an error of a DC output 412 of a synchronous detector 414 is calculated from an S/N ratio in the loop, and corrected by using an RMS detector 502 as an analog calculator. In this way, the PLL band width can be made equal to a band width of a noise filter 410, and an influence of an addition noise in a system is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a synchronous detection device used in an electronic/veda/s measuring instrument or the like.

[Prior art]

Accurately measuring radio frequency signal levels is important in license fee measurements and many other applications. Such measurements are particularly important when measuring unmodulated or continuous wave (CW) signals, such as signal generator calibration and attenuation measurements. Random noise added to the signal under test when the signal level is low becomes an error factor in signal level measurement, and as the signal level decreases, the error ratio due to noise increases.

In the past, several solutions have been proposed to improve the measurement accuracy of low-level signals buried in random noise. One solution is to calculate the RMS (effective Ji) before detection.
It involves filtering the signal with a narrow-bandwidth filter before performing re-detection or average direct conversion. By doing so, the influence of noise is reduced. However, narrowbanding before detection makes it difficult to tune the signal to the center of the narrow bandwidth filter during the measurement process. Furthermore, as the detection bandwidth narrows, measurements of the signal's residual phase modulation (
PM) and residual frequency modulation (FM). PM and FM effects result in errors due to modulation components falling outside the filter bandwidth. This makes it difficult to accurately center the signal within the filter bandwidth. Furthermore, if the filter bandwidth is narrow, it will be more susceptible to signal frequency drift. Therefore, errors occur if the signal drifts outside the filter passband. A qualitative analysis of these errors is described below.

Another conventional solution is to correct for noise errors after detection. However, this solution has a signal-to-noise ratio (
The signal-to-noise ratio) must always be known. To know the SNR, the noise level must be measured.

This requires removing the signal from the instrument and measuring the noise, thus complicating the measurement process.

Furthermore, when the difference between the noise level and the signal level is very small, 5NFL measurements become impractical and inaccurate.

Note that one of the conventional solutions is a synchronous detection device, which can remove DC errors caused by noise. One major problem is where to obtain the necessary synchronization signals. Even if high-level samples of the signal under test are obtained, the drawback is that at high frequencies the necessary synchronization signals within the system leak into the measurement system. This adds to and masks the low level signal you are measuring.
To deal with this problem, it has been proposed to derive a reference signal for a synchronous detection device using a phase-locked loop (PLL) that always operates at a low frequency.The reference signal obtained by Asahi PLL masks low-level signals. Although it reduces the problem of locking, it also reacts to noise and phase or frequency modulation of the locked signal. By reducing the loop bandwidth, the level of phase noise can be lowered.

However, by reducing the bandwidth, it becomes more difficult to track drifting or broadband signals. This is clear from the following analysis.

In an ideal synchronous detection device, synchronous detection mixes the input signal with another signal that has the same frequency and phase,
Dropping to OHz is realized by trapping. The mixer used here is a switching multiplier. Input signal ■ B coswct, switching signal 2 (cosw
ct+ (1/3) cos 3wct ten (115
)cos 5 wct+...], the multiplier output Vo is Vo(t)==(Vs)(1+cos2w
ct-(1/3 >C082WCt+-...'J...
......(1) It is expressed as follows. This output is processed through a low-pass filter, leaving Vs, a DC component proportional to the input signal level. If the input signal is amplitude modulated, it is demodulated and appears at the output of the coherent detection device.

When the input 5NI is high, the linearity of the detection is determined by the characteristics of the switching multiplier, resulting in a nonlinearity of about 0.003 dB for input changes of 10 dB. However, as the SNR decreases, A complication arises, in which significant nonlinearities result.

In conventional synchronous detection devices, most of the synchronous detection circuitry is used to generate the high level local oscillator (LO) input signal required by the mixer. This signal must be in phase with the test input signal and must be able to track inputs that drift by, for example, a few kHz or more. To achieve this, a voltage controlled oscillator (VCO) is phase-locked to the input signal to generate an LO multiplied signal. In a phase-locked loop for this purpose, the VCO is phase-locked quadrature to the input signal. As a result, the output of the VCO is phase shifted by 90 degrees to bring the phase relationship between the LO and the input signal to zero degrees.

FIG. 2 is a block diagram of a conventional coherent detection device.

In FIG. 2, 201 is a phase detector, 202 is a loop filter, 203 is a vCO1204 90° phase shifter, 2
05 is a synchronous detector, and 206 is a low-pass filter.

Similar to the overall loop response, the error performance of the synchronous detection device is determined by the phase-locked loop filter 2 in this system.
02.

In general, synchronous detection provides considerable improvements in noise performance compared to traditional envelope detection techniques, but it also has drawbacks. for example,
Considering an input signal consisting of an unmodulated carrier of 455 kHz surrounded by additive white noise of 30 kHz bandwidth, the noise can be separated into 2111i1 independent components. That is, the in-phase component n i (t)
and the orthogonal component nq(t). These components are uncorrelated stochastic signals and are bandwidth limited to 15 kHz in this example. As a result, the composite input signal Vi(t)
can be expressed as follows.

Vi(Vg coswct +n1(t) cos
wct −nq(t) sinwct・・・・・・(2
) By regarding the LO multiplied signal as an ideal signal, ie, 2coswct, and performing basic linear analog multiplication, Equation 1 can also be expressed as follows.

Vc(t)=Vg+nl(t)+(Vl+nl(
t) ) CO82wct-nq (t) sin 2
wct --- (3) This result reveals two facts regarding the use of coherent detection. 1st
At the output, the noise is additive. Noise is not multiplied by the input signal as in the detector. As a result, the desired signal vs can always be reproduced. Output noise can be reduced by adding a low pass filter to the output whenever necessary. The second fact is that only the in-phase noise component is converted to baseband. The orthogonal component is removed. When downconverted, the summed noise sidebands on both sides of the input carrier are folded together, and the power levels are summed since the two sidebands are uncorrelated. Conversely, since the LO is synchronized with the carrier, the peak value of the input signal is directly converted to the output.

As a result, the power of the given sacrificial output component is related to the peak of the input signal voltage. The unwanted noise output power is related to the RMS noise input voltage. However, these two facts of synchronous detection are valid only for ideal synchronous detection, which is exactly in phase with the LO multiplied input signal. Most of the problems associated with implementing coherent detectors arise from the inability of phase-locked loops to provide accurate in-phase LO signals.

One of the realities faced by any conventional coherent detection device is the unavoidable presence of residual phase modulation (PM) in the input signal. Even though conventional synchronous detection devices are specifically designed to use KCW signals, if there is a phase variation in the input signal, the phase-locked loop attempts to follow the phase modulation.

If the PLL's bandwidth is wide enough to accommodate all phase modulation sidebands contained in the input signal, the vCO will perfectly follow the phase of the incoming signal, and the two inputs of the in-phase detector will It becomes positive 1i1iiK in phase. However, the bandwidth of the conventional PLL must be kept narrow in order to be robust against noise. As a result, some of the phase modulation side bands fall outside the PLL's bandwidth, and the input of the coherent detector cannot remain completely in phase, thus producing PM noise.

This PM noise can be easily understood by considering the input of the synchronous detection device as a multiplication of phase vectors as shown in FIGS. 3A and 2B. The output of the synchronous detector is proportional to the cosine projection of the long phase vector on the LO phase vector. As shown in FIG. 3A, when the two phase vectors are exactly aligned, the output is maximized. The slight PLL tracking error caused by residual input phase modulation causes relative phase jitter between the inputs. This phenomenon is illustrated in FIG. 3B, where the jitter causes the average output level to fluctuate and become smaller than the ideal maximum output level.

The effect of the actual output of the in-phase detection device being lower than the ideal level is illustrated in the following example.

Assume that there is a small amount of sinusoidal phase modulation in the input signal 1c wm, and the peak LO phase shift is B radians.

By analysis similar to that used to derive Equation 1, the output of the synchronous detection device in this can be shown as follows.

Vo(t)=(Vs) cos(Bcos vw
nt −1(cos (wmt+Ep)+・・・・・・
]・・・・・・・・・(4) Here, B′ is the equivalent peak phase shift of the VCO PM in radians, Ep is the phase error between the two inputs, and “・"..." represents a higher frequency order. If wm is much smaller than the PLL bandwidth, the VCO will almost perfectly follow the input signal. This ideal case results in a synchronous detector output Vs.

If Wm is much larger than the bandwidth of PL,L.

vCO barely tracks the incoming phase modulation. The detector output can be approximated by the following equation.

Vo(t) = (Vs) cos (B cos w
mt )−−・−・・−・−・・−(5) Vessel (B
e5sel) Series representation cos (Xcosy) = Jo(X)-2J2 (X
) cos 2y+2J4 (X) cos 4 y+
・・・・・・・・・・・・・・・・・・(6) Equation 5 is expanded as follows.

Vo(t)=(Vs)(Jo(B)−2J2(B
) cos 2 wmt -4-...----)...
......(7) Here, the 5th term is a Bessel series number.

When the deviation B is small, the synchronous detection output is the first two terms above,
That is, it can be approximated by DC component and AC component terms. The term Jo(B) is less than 1, which indicates that the DC component ring is suppressed and there is an error for inputs with phase modulation. As shown in FIG. 4, the average value of the actual coherent detection output is smaller than that in an ideal case without PM.

If the ratio of phase error and DC component output is constant, they will cancel out in any comparison measurement. Unfortunately, the percentage error varies with input level. In conventional PLL phase detector design methods, the equivalent loop bandwidth is proportional to the input level. This change in bandwidth also changes the amount of input phase modulation that the VCO follows as the input level changes. Assuming that the spectral purity of the signal is constant as the input signal level changes, the percent error in the DC side of the conventional coherent detection device also changes when the tracking of the PLL changes. The end result is non-linearity in relative level measurements.

The second major problem that must be overcome when using conventional tracking coherent detection devices is input additive noise.

This error occurs regardless of the spectral purity K of the input carrier. It depends only on the input summation noise level.

The error increases as the input SNR decreases.

The additive noise error is caused by the phase modulation of vCO. In mathematical analysis, the input signal with additive noise is as follows.

V i (t) = Vl, cos wct -1-n
l(t) cos wct −nq(t) sinwc
t・・・・・・・・・・・・(9) The vCO signal is expressed as follows.

2 sin (wct +Eo(t)) where E o
(t) is the error caused by input noise. Since the phase detector is essentially a switching mixer like a synchronous detector, the phase detector output Ve(t) is obtained by the following equation.

Ve(t), = Vs sin Eo(t)-1-ni
(t) sin Eo(t) ・-nq(t) co
s Eo(t) −−α [Equation 10 does not include the high frequency order removed by the loop filter. V
To find the error caused by the phase modulation of CO, K must determine Eo(t). This decision is not trivial due to the intermodulation in the PLL between <vcO phase modulation quadrature sidebands and the in-phase and quadrature components of the incoming summation noise. The best solution is go(
t) is statistically expressed. According to the above analysis, the relationship between Eo(t)'' and the SNR in the loop can be expressed as follows.

go(t)”:: l/2 S N R−-αυ where SNR is defined as Ps/n 2 B L and P
s is the signal power of the PLL input, n is the same (noise spectral density of the input, and BL is the PLL equivalent noise bandwidth.

To understand errors due to input noise in conventional coherent detection devices, it is assumed that the VCO phase noise modulation is represented by go(t). By definition, this phase modulation is in quadrature with the vCO carrier signal.

The phase modulated signal is mixed with the input signal and additive noise within the synchronous detection device. If the VCO noise is correlated with the incoming quadrature noise component, a DC component will result in the coherent detection output. This component is added to the DC output from the VCO carrier mixed with the input carrier,
Produces a positive DC error.

However, in reality the opposite happens. The DC output of a conventional synchronous detection device is lower than the DC output for an input signal of the same level without additive noise.

Because of the intermodulation that occurs within the PLL, the VCO phase modulation is uncorrelated with the incoming quadrature noise, and the input phase vector of the coherent detector appears to be the same as in Figure 2A. The average DC flux of the detector is reduced due to the relative jitter between the phases of the inputs of the two synchronous detectors.

The magnitude of the reduction depends on the 5NRK of the detector input. This results in nonlinear behavior of the detector as the input signal level changes.

[Purpose of the invention]

An object of the present invention is to compensate for and reduce errors caused by PM noise and addition noise in a synchronous detection device.

[Summary of the invention]

The synchronous detection device of the present invention includes a phase-locked loop (PLL) having a constant loop filter bandwidth. The PLL provides a correction signal to a local oscillator, which provides a reference signal to a synchronous detector. Further, the PLL has variable gain.

The RMS detector is used for primary correction of additive noise within the synchronous detection device. The noise bandwidth of the resolution filter that passes the signal to the RMS detector is made to match the loop noise bandwidth. The synchronous detection device of the present invention has a wider loop bandwidth than conventional synchronous detection devices. Accordingly, the tracking problems associated with narrow bandwidth filters of conventional coherent detection devices are much reduced.

〔Example〕

As shown in FIG. 5, the synchronous detection device according to the embodiment of the present invention uses a PLL filter to reduce the phase that causes nonlinearity, that is, residual PM. Also, the gain may be varied and controlled by, for example, a microprocessor. The microprocessor uses a multiplying digital-to-analobe converter (DAC) 402 to vary the effective resistance of a feedback resistor 404. What if the condensation in Figure 5? 406 is sufficiently large, the transfer function of this loop filter 408 becomes H(s)''((R2/FLI)+1/5ctR1):
]・・・・・・・・・・・・(8) This loop filter 408 keeps the PLL bandwidth of the synchronous detection device according to the present invention constant regardless of the input signal level, thereby eliminating errors induced by PM. remove.

FIG. 1 is a block diagram of a synchronous detection device of the present invention using the loop filter of FIG. 5.

In the figure, 401 is a phase detector, 408 is a loop filter, 403 is VC0, 416 is a 90' phase shifter, 41
4 is a synchronous detector, 41o is a filter, and 418 is an RMS detector.

In the figure, the PLL bandwidth is equal to the bandwidth of noise filter 410 to remove the effects of additive noise in the system. The principle of this technology can be explained qualitatively as follows. Since the DC output 412 of the synchronous detector 414 is proportional to the mean cosine projection of the input phase vector onto the VCO 4030 phase vector, the error in the detector DC output 412 is calculated from the SNR in the loop.

The procedure is as follows.

Vo(t)cc cosgo(t)kan cos(goRM
s) -4"2) EO ratio MS meeting α 1/2n (1/2S
NR)'/2... Haze error (dB) = 20 log (cosF, o RM
S ) = 20 log cos ((2SNR) ”2
) If this error has a constant ratio to the input signal level, the present invention measures the level ratio and cancels it out. However, the error is a function of SNR, which changes with changes in input level, resulting in nonlinearity in the synchronous detector output. If the SNR is known, the error in the DC output of the detector can be corrected mathematically using the following relationship.

Error (dB) = 201ogcos ((28NR)
/2)・・・・・・・・・(15) As shown in FIG. 6, in the embodiment of the present invention, RMS
Errors can be corrected by using the detector 502 as an analog calculator. In the illustrated invention, it is not safe to determine the SNR independently. The synchronous detector output voltage is the input to the RMS detector. The DC component is just the average value of this voltage. In other words, Vo = Vs cos possible ・Song・
...α0th order permutation is possible.

Vs cosEo(t)'; Vs (1,-(1/2)
) Eo(t)2]: VsCl-(1/2) E
o (t)2) = -0'f) But we must remember the following equation.

co(t)2” 1/2 SNR, -song,,,
, (11) Therefore, Vo == Vs(1-(1/2) (1/25N)
L) ) ·--(18) By substituting SNH2Ps/2nBL, the following equivalence relation is obtained.

Vo=Vs(1-D/2)(t/2PS/2nBL)=VsC1-(1/4)(2nBL/Ps)] ・
]++-+-+-1!1 Equation 19 represents the DC component of the synchronous detection output. It is the true value Vs and the error term (-Vs/4
) (2nBL/Ps). They are both DC voltages and cannot be distinguished. Based on this equation, the total input Vi to the RMS detector 502
can be written as follows.

Vi = Vdc -1-Vac At this time, Vdc is expressed in Equation 19. 4L<VaC represents a noise voltage with an average value of zero. Vac is down-converted to the baseband by the noise applied to the input of the synchronous detector and filtered by the BN.

Vi is the input to the RMS detector. Since the FLMS detector calculates the square of Vi, the average f-square of Vi2, and the square root of Vi2, the RMS detector output 0 is expressed as follows.

Vo = (Vi2) Therefore, from equation 19, Vi = Vs (1-(1/4) (2nBL/Ps)) + (
Vs/Vs) (Vn(inBN)). However, Vi”= (Vdc-1-Vac)2= Vdc 10V
ac +2 Vdc Vac=vd♂+-Vac2・-
=-(20) Substituting the Vdc and Vac terms into this last equation yields the following result.

Vi2=Vs2(1-(1/4)(2nBL/Ps)
)2+Vs2(Vn(inBN/Vs)2=Vs2
(1('/2)(2nBL/Ps))+Vs2(P(1
nBN/Vs2]...(2L1) Here, p(inBN) is the average power of noise.

Since P(1nBN)/Vs2=2nBN/Vs2, Vi”=Vs2(1-(1/2) (2n B L
/ Ps ) + 2 n B N/ Va2]---(
22') The term 2nBL/Ps represents SNR-1 at the input to both PL, L and the synchronous detector. Since Vs is the peak voltage of this human power signal component, Vs2=2Ps. Substituting Equation 22 into Equation 21, the final result can be expressed as follows.

Vi”=Vs2(1-(1/2)(2nBL/Ps)+
(1/2) (2nBN/Ps)) --- (23) This last equation is BN281. By doing so, the last two terms cancel each other out, leaving W=Vs2.Vo=Hyakumenou/2−[vS2]1/2=Vs It is shown that the final output of this RMS detector is derived.

Therefore, the error due to the addition JE/is is advantageously canceled out. Therefore, according to the present invention, the loop bandwidth BL and the noise filter bandwidth BN in FIG. 1 are made equal. Furthermore, filter bandwidths BL and BN are kept constant.

According to embodiments of the present invention, the CO power is book-constant. When the PLL transfers phase noise onto the vCO, the vCO carrier power is reduced by the amount of power in the phase noise side band. Since the dc small output of the synchronous detector is proportional only to the CO carrier, the output according to the present invention is suppressed by this amount. When BN=BL, the RMS detector adds the voltage equivalent to the noise power removed from the VCO carrier line and the noise power of the transposition.

FIG. 7 shows another embodiment of the present invention.

The same parts as in FIG. 1 are given the same reference numerals.

The operation is almost the same as in FIG.

〔Effect of the invention〕

According to the present invention, it is possible to provide a synchronous detection device that does not generate errors due to noise or the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a synchronous detection device according to the present invention. FIG. 2 is a block diagram of a conventional synchronous detection device. 3A and 3B are explanatory diagrams of the synchronous detection device of FIG. 2. FIG. 4 is an output waveform diagram of the synchronous detection device of FIG. 2. FIG. 5 is a block diagram of a filter used in the synchronous detection device of the present invention. FIG. 6 is a partial block diagram of the synchronous detection device of the present invention. FIG. 7 is a block diagram showing another embodiment of the synchronous detection device of the present invention. 401: Phase detector 408: Loop filter 403: VCO 416: 90' phase shifter 414: Synchronous detector 418: RMS detector 410: Band pass filter. Applicant Yokogawa Yokogawa Neeret Bano Card Co., Ltd. Agent Patent Attorney Tsuguo Hasegawa

Claims (1)

[Claims] synchronous detection means having a first input terminal into which a first signal is input and a second input terminal into which a second signal synchronized with the first signal is input through a first bandpass filter; A synchronous detection device comprising a second bandpass filter provided at the output section.