JPS6049936B2 - Control device for data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system, and more particularly to an apparatus for controlling peripheral devices related to the data processing system.

One objective of the invention is to optimize the performance of multiple microprocesses within a multiprogram for data processing.

It has been common in data processing systems to use input/output control programs, or channel programs, to determine the types of transfers that occur between the central processing unit and peripheral devices.

In the program in which the input/output operation to be performed is performed, the instructions indicate the address of the peripheral device and the corresponding channel program or control address on which the operation must be performed. Peripheral addresses and control addresses are transferred into input/output registers. The peripheral device's address is carried on a bus connecting the peripheral device to the central unit, and the peripheral device recognizes its own address and responds to the central unit with its status. If the peripheral device is not available, the control information and peripheral device number are stored in a holding queue and used at a later time. If a peripheral device becomes available, a connection is made and information transfer begins. The channel program is started and execution of instructions called by the peripheral continues until the final instruction is executed. Transfer initiation may also occur in other directions. In this case, the peripheral device requests the command. The central unit determines which of the requested orders has the highest priority. Once that step is completed, the connection between the peripheral device and the central unit with the highest priority is made. The peripheral then sends a transfer request indicating whether the transfer is an input or an output. A transfer is made and may or may not be followed by another transfer. The end of the exchange is indicated by the end of the order request message. In multi-program data processing systems with several peripheral devices, the combination of input/output operations is done with interrupt messages.

Interruptions usually occur at the end of task performance on a peripheral, but may also be interrupted for other reasons. When an abort message is detected, it is used in an operational mode to test the operating microprogram and prepare it for execution. The scheme continues by transferring control to the microprocess that has a higher priority than other microprocesses being executed. There is a way in which lower priority microprocesses are controlled when these microprocesses are long filed for execution. Using channel programs within the process equipment, the central unit is completely independent of peripheral device management.

However, the channel program itself cannot manage multiple peripherals at the same time, requiring microprocesses to complete each time. A certain number of peripheral devices may be queued for a considerable time before control of the corresponding channel program is allowed. This commonly occurs with slow peripherals. One purpose of this invention is to generally provide a mechanism that makes it possible to control multiple microprocesses simultaneously.

In other words, the invention is to make the ring between the central unit and the various peripheral devices "transparent". This invention has a data processing system and is a multi-program system, and has a central processing unit (CPU) connected to a peripheral control unit PCU, and each peripheral control unit operates in a master mode with respect to the central unit and peripheral devices. However, the processing power of the central unit is increased, the connection between the central unit and the peripheral devices through the peripheral control unit is fully transparent, and the performance of various micro-processes is performed simultaneously in the peripheral control unit.

As a result, microprocesses are fairly distributed in both space and time. The distribution of space takes place within appropriate memory fields, and the distribution over time is obtained by linking microprocesses with specific times of start and when an interruption occurs or when a microprocess completes.
In order to achieve these, the present invention provides a PCU having firmware. The firmware is a micro-operation system (MIO) that cooperates and optimizes microprograms and operations within the table or CPU.
S).

The firmware includes a set of microprograms and tables to control peripheral devices. The microprograms that make up the MIOS control the multiprogram clock, handling of hardware interruptions, and control for executing microprocesses. The entire microprogram and peripherals necessary to control a uniform group of peripherals, such as a group of various types of card readers, are designated as an "Affiliate Firmware Package" (AFP).
. There is a firmware form suitable for each particular type of peripheral device attached to a PCU, and each firmware form operates under the supervision of the MIOS. AFP is MIOS
or by the channel program (through MIOS) and takes into account peripheral signals. ．． The AFP includes the following elements. 1 Peripheral Adapter (DA) one or several control blocks (
DACB).

Each DACB forms the space for the zeta and the microprogram in memory, ie all the resources to control the peripherals connected to the peripheral adapter. 2. A group of microprocess control blocks (MCBs).

Each MCB controls a microprocess that is operated to perform a specific function of the attached device. 3. A group of microprograms.

Microprograms are reentrant, making them easy to split into several jobs. 4 Data field containing permanent or transient data regarding various jobs of AFP. A microprocess, when performed in a series of microprogram operations, generates a sequence of non-simultaneous microinstructions; within the scope of this specification, a microprocess is defined as a sequence of asynchronous special actions under the control of an AFP by means of a microinstruction. This is to ensure that the

A microinstruction corresponding to a microprocess is "active" when the microinstruction is being executed.A job is "active" when the microinstruction corresponding to the microprocess is being executed. Microprocesses are activated when one of a variety of special events occurs or when called upon. Microprocesses belong to one or the other of two classes: The first class is called jobs EVl and EV2 and consists of jobs that have the characteristic of being automatically started by the initiation of events EVl and EV2 (i.e. notification of events NO.1 and NO.2). and cannot be addressed by other microprograms. That is, other Jimobs cannot affect it. The second class is called the ordinary microprocess class. Ordinary microprocesses control other microprocesses in the control block MCB of the associated microprocess. can be addressed at The name of an ordinary microprocess is determined by the address of its MCB. The name of each MCB is AFP
is known as , and is determined at the time of assembly (see definition of the word). Other objects, features, and advantages of this invention can be seen in the accompanying drawings.
This will become clear from the following explanation of surfaces.

FIG. 1 shows that a central processing unit CPUlOO is connected to a control unit PCUlOl via an interface PSI. All information that has to be conveyed from the central processing unit to the peripheral devices is conveyed through the PCU at the interface PSI. Blocks 102 to 105 constitute an adapter for various peripheral devices and are connected to the peripheral control unit PCUlOl and associated blocks 106 to 109, which represent the various peripheral devices P1 to Pn. FIG. 2 shows the PCUlOl shown in FIG. 1 in more detail, but only those hardware elements necessary to understand the PCU are shown.

A detailed description of the PCU invention is contained in French Patent Application No. 740,579, dated February 20, 197. The control part of the PCU consists of a multiprocessing peripheral unit MPU2OO, an interface control unit ICU235, n adapter gates for peripherals DAI to DAI234 (each gate is connected to a corresponding adapter DA-DAIl).
(from which only DAIn is shown), p boats PSI (7) PSI to PSIpl (only PSI port 233 is shown) for the interaction between the central processing CPU and the peripheral control unit PCU. It consists of a timer boat 236 that occurs at regular times of E1 timer interruption. Each gate is given a number and PSI boats are numbered 0.
DAI boats are given numbers p to p+n-1 and timer boat numbers p+n.

The processing unit MPU2OO is a microprogram and MPU2OO.
a memory M2O2 for storing IOS tables and microprograms and tables for each N thousand; a ROSAR register 204 containing the address of the next instruction to be executed and governing the various transfers of MPU and CU operations; data received by a microinstruction, or a flip-flop that can be tested or divided into an upper register bank URB and a lower register bank LRB and act as working registers to transfer or accept data from the ICU; or memory 202
or from an external event received by a hardware interruption of the arithmetic and logic unit 211 or a dual register bank 210 that can exchange data with the register DNR2O8 storing the number of the adapter of the peripheral device on which the work is or is to be performed. It mainly consists of an operator 206 that calculates the address of .

The selection of the upper register bank or the lower register bank of the double bank register 210 is performed using a flip-flop UL2l.
It will be held at 7.

The bank of upper registers is selected when UL is set to logic 1. Flip-flop UL is brought to logic 1 when there is a signal EVl indicating that an event EVl has occurred. This process can use the lower bank of registers to perform normal microprocesses and the upper bank for EVl microprocesses. Therefore, when a priority EVl event occurs, there is no need to protect the data of the aborted ordinary microprocesses in the lower bank. To re-associate an interrupted ordinary microprocess, the flip-flop UL is returned to O and selects the lower register bank in which the data of the ordinary microprocess that existed at the time of interruption was stored. Setting the flip-flop UL to 1 indicates the presence of EVl at the input of the logic NND gate 216. In this way, one EVl
Microprocesses cannot be interrupted by other EVl microprocesses. flip flop EE2
l5 makes it possible to mask EVl interruptions. Its value can be changed by a microprogram. The logic value 0 of flip-flop EE2l5 indicates that the EVl signal is AN
This prevents the signal from being transmitted through the D gate 216 and prevents the microprocess being performed from being interrupted. ADNR register 209 saves the number of the peripheral adapter when a microprocess performed on the peripheral adapter is interrupted.

Register 209 is loaded at the same time as the DNR register.
When the suspended microprocess is restarted, the number stored in the ADNR register is restored into the DNR.
This operation allows the peripheral adapter to be connected and restarts the interrupted microprocess which requires resetting the flip-flop UL to zero. Register SP2l2 is combined with logic arithmetic unit 211;
Identifying zero results or overflows during operations within arithmetic unit 211.

The interface control unit ICU 235 includes a coding device 221 implemented with the aid of combinatorial logic circuits to identify each EVl signal by a corresponding gate number.

The logic circuit gives priority to the EVl signal present in the DAl or timer gate and having the lowest number (E1 timer has lower priority). ICU 235 also includes a decoding device 222 to decode the contents of register DNR, select ports DAI, PSI or timer 236, or signal the presence of 0R gate 220 or signal E1 to the MPU. The primary function of timer gate 236 is to provide the EVl signal from clock 230 at regular times. The EVl signal is transmitted to a coding device 221, which provides a CEVl code corresponding to the E1 signal having the highest priority in the form of a binary code, and the code CEVl is sent to the register DN.
loaded on R.

One or more E1 signals are on the DAI or timer boat, and the logic 0R gate 220 is the logic AND gate 2.
16 gives a signal which is transformed into the EVl signal when activated, interrupts the microprocess if it is being executed and starts the microprocess EVl indicated by the code CEVl found in the register DNR. let

The EV2 signal is sent to the 0R gate 2 in the timer boat 236.
The output of gate 224 is connected to the input of AND gate 223. The other input to the AND gate 223 is the signal ゜゛SELp+.゛(Decoding device 2
22). The output of AND gate 223 provides a signal 2s which is tested in AND gate 214 by the contents of the microinstruction in register ROR. Gate PSI233 is EV2
Issue signals, especially when a channel program is waiting or when other instructions are waiting in the central unit. The PSI boat then inputs C to the input of 0R gate 231.
PW and INW signals are received and these signals are input to AND gate 23 when a PSI boat is selected by decoder 222.
Enabled by inputting 2. Briefly, there is only one hardware interrupt with at least one EVl signal appearing on the DAI and one of the timer boats. When the EVl signal appears, if it is not masked, it sets the logic value 1 of the UL2l7 flip-flop and register DNR in the ADNR2O9 register.
Back up the contents of 2O8 and save the ICEVl code to D.
Transfer to NR2O8 register and double register bank 2
Register RE.10 in the upper bank. Backing up the return of the address to the normal microprocess that was interrupted within the l5RF (not shown), an unconditional branch and MIOS
The EVl microprocess is executed under the control of the EVl microprocess. The return of an interrupted microprocess is initiated when the microinstruction RMI (Return after Interruption) is reached during the operation of the microprocess EVl.

Instruction RAI resets the UL2l7 flip-flop to zero, transfers the contents of the ADNR2O9 register into the DNR2O8 register, and transfers the contents of the ADNR2O9 register into the DNR2O8 register, in the direction of the address that was interrupted and returns to the normal microprocess found in the upper register bank's register RE (5RF). and the contents of register SP2l2 are restored by the contents of register R7 of the upper register bank of the double bank of registers 210 by the microinstruction preceding the microinstruction RAI. Processed in MPU2OO with the help of microinstructions located within.
The 16-bit format of these microinstructions is fixed, with the first 4 bits indicating the operation code.
The operation code has one of the following meanings.
A logical or arithmetic operation, an input, an output operation, a read/write operation in memory, a conditional or unconditional connection branch with or without registers, or a state to be performed by the microprocess with respect to the control mechanism of the microprocess. shows the transition of Figure 3 shows a simple form of the transition states of various microprocesses,
Its status is as follows.

Associated with each job at any given moment is a variable state called the current performance state. The current execution state is running, suspended (interrupt), or inactive. The running state means that the microprocess is in the process of being executed. In other words, J. Data corresponding to a job is being transferred between the central processing unit and the peripheral devices. Information resulting from the execution of microprocesses resides in the PCU's registers. A suspended state occurs when a microprocess loses control of the PCU because another microprocess with a higher priority is placed in a running state. The interrupted microprocess is restarted after a short time. The information generated in the PCU registers while the microprocess is being executed is saved (saved) before the microprocess is interrupted.
and the contents of these registers are restored when the microprocess is restarted. An inactive state indicates that the microprocess has not yet been started or has completed. one of three successive states that determines the handling of the microprocess in the next period of process states, namely the readiness state;
It is also possible to combine one of the standby or unplanned states with each normal microprocess at any moment.
These states only exist for regular jobs, and they are controlled in the associated job control block or MCB. A microprocess is in a ready state when it is required to perform as soon as possible. The MCB that controls the microprocess is stored in the preparation queue RQ. A microprocess is in a standby state when a request is made to execute the microprocess at the end of a time determined at the moment of request. This microprocess remains in a waiting state until the time interval has elapsed. The MCBs that control the microprocesses are stored in a "timer queue" called "TQ". A microprocess is said to be in a haphazard state when it is neither in a ready state nor in a standby state.
For example, a microprocess that moves out of RQ and into a running state moves into an unplanned state. Successive states of normal microprocesses as described can be found in the associated MCB, and they can be modified by other microprocesses or the same microprocess or by decisions of the MIOS. In the first two cases, microinstructions controlling microprocesses were executed. The transitions (TRNSITIONS) indicated by dotted lines in Fig. 3 are caused by MIOS or E
Determined by the data for the Vl microprocess.

The transitions shown in solid lines are provided by microinstructions with the following meaning: Microinstruction RAI is the last microinstruction of the EVl microprocess. An interrupted microprocess can be restarted after the interruption has taken place when its execution state moves from the "Running" state to the "Inactive" state. Microinstruction 44 End 51 (TER
MINATE) is the last microinstruction executed in a microprocess that is not an EVl microprocess, and when the execution state moves from the "running" state to the "inactive" state, it is determined only for normal microprocesses. Subsequent performance states are not modified. The following microinstructions do not modify the "running" state of the jobs that perform them.

Microinstructions modify successive states of the normal job specified in the MCB. '6 Activation'(ACTIVA'IE
) A microinstruction places the value of the successive execution state of a microprocess into the "ready" state, regardless of the state that precedes it. Modify the value of the successive state: − If the current value of the successive execution state is unplanned or waiting, the value of the next state is moved to the waiting state, deciding to put the microprocess into the ready state. The specific time for the MIOS is stored in the MCB and used by the MIOS.

- If the current value of the successive performance state is the "Ready" state, its value is not modified.

The microinstruction "SUSPEND" allows the value of successive execution states to be unplanned, regardless of the previous state of the microinstruction.

Although not shown in FIG. 3, there is an STDA microinstruction that kills all microprocesses in AFP. There are two ways to interrupt a microprocess.

One is an interruption due to the appearance of event EVl, the other is the start of a normal microprocess. Only one level of hardware interruption is reserved for the EVl microprocess. Generally speaking all microprocesses are suspended by their level, but the execution of an EVl microprocess cannot be interrupted by other EVl's of the same level. As shown in FIG. 2, the start of the microprocess forces the UL flip-flop to a logic 1, so that the output UL does not enable the other inputs of the N1 gate 216.
The appearance of a new EVl signal has no relation to the execution of the EVl microprocess in the 4 "running" state, the appearance of the EVl signal, the flip-flop EE2l5 is logic 0, or each DAI port is not shown. It can be masked by a microinstruction when forced to a logical 1 by a flip-flop.The other level of interruption is at the firmware level.

Any normal microprocess can be interrupted with a normal microprocess or an EV2 microprocess with high priority. However, ordinary microprocesses can be made uninterruptible by microinstructions. Microinstruction MSKP can mask all non-E1 jobs. A running microprocess is considered to be temporarily at level 2 and cannot be interrupted by another normal microprocess. The mask removal operation is performed by the UMSP microinstruction. In addition, the E
It can also be masked with the MSKE microinstruction performed by MSE. The action diagram shown in FIG. 4 summarizes the arrangement of actions performed by interrupting the hardware EVl.

an operation that starts at the top of the diagram and works its way down, if any, to interrupt the running microprocess;
The link with the analysis of the holding matrix of microprocesses at each level of priority is as follows, with the purpose of starting a microprocess with a higher priority, if any.

The event EVl comes from the clock impulse every millisecond given from the DAI boat or from the timer boat 236 when set. If EVl comes from the DAI boat, then if there is a microprocess running, it will be interrupted. , the EVl microprocess associated with the corresponding DA is started in step 401.The last microinstruction RA
The execution of EVl to return to the suspended microprocess, if any, may also come from the timer board. In that case, the timer matrix is configured such that the respawn time of the first MCB in the timer matrix is determined in steps. 402 is reached. If so, the MCB is placed in the ready queue (step 403), and the next MCB respawn time is updated (step 404). Otherwise, The resurrection time of the first MCB is updated. When the timer matrix update is complete, the microinstruction tests the input of AND gate 214 of FIG. Check if one exists.Then, the line of EV2 microprocess is scanned (step 405).If the EV2 signal is present, the corresponding EV2 microprocess is
It starts with (steps 406 and 407). one EV
2 signals connect the central unit to the peripheral control unit or DAI
It may belong to the physical channel of the PSI interface that connects to the boat and signals that an incident has occurred to the central unit or to one of the peripheral devices.

Once the last EV2 microprocess is executed, scanning of EV2 microprocesses resumes to see if there are any other microprocesses to start. If it exists,
The previous process is repeated, traversing the various levels of otherwise normal microprocess priority starting from the highest level of priority and working down (step 40).
7), if one common microprocess is found at a certain level, the microprocess is performed (step 4).
08) and is executed to the instruction until the instruction ゜゜end゛ is reached, allowing the EV2 microprocess to be scanned again. Of course, normally the microprocess can be interrupted by the appearance of the EV2 signal.

The folding process is resumed at step 400 from the top of the drawing. The scanning of the holding matrix just explained is performed within the PCU 44 and the Dispatcher 52
It is called. Figures 5 to 8 are memory M2O2 of Figure 2.
and is used for microprocess control 4
The table below shows the parameters that make up the firmware elements.

FIG. 5 shows the format of the peripheral adapter control block DACB.

The algorithm is to look again at the associated DACB address from the DAl boat number. allow it to come out. Each DACB occupies space in memory M and controls the operation of the DAI boat associated with it. Word 0 is MS of microprocess EVl
Contains the absolute starting address specified by Al. Word 2 contains 3 the absolute starting address of microprocess EV2. Word 3
is specified in AFP and contains the absolute address of the data necessary for the execution of microprocess EV2. Word 4 consists of a first byte specified in H° C. containing the first number of the logical channel and a second 4 BYTE indicating the number of the logical channel associated with the DAI port. (See the glossary of terms that define logical channels). Word 5 contains the absolute address FMCBA of the first MCB associated with the DAI boat. word 6
The two bytes contain bits E and S of the peripheral adapter status. If bit E is equal to 1, the DAI vote event EV2 is masked. If bit S is equal to 1, all operations of the DAI boat have been aborted (the associated microprocess cannot yet be performed). FIG. 6 shows the format of the microprocess control block MCB.

Each MCB occupies space in memory M2O2 of FIG. 2, which contains the information necessary to manage and perform the associated microprocesses. The MCB consists of 8 memory words,
Each word has a size of 16 bits. Bit 0 of word 0 ~
3 establishes the number of the DAI boat to which the MCB is connected. Bits 8-10 of word 0 determine the priority level of the microprocess associated with the MCB. Bits 12 and 13 of word 0 (TQ and RQ, respectively) establish the sequence state of microprocess execution. Logical product TQ-RQ
has the following meaning: That is, πtRQ is equal to 00...no state is provided for the microprocess.

TQ-RQ is equal to 01...The microprocess is waiting in the timer line Q.
Ru.

'IQ-RQ is equal to 10...The microprocess is in the ready state with the readiness matrix (RQ)
It is in.

Terms 1 and 2, designated NLP and PLP respectively, will be discussed below.

Word 3 is not important to this invention.

Word 4, denoted ABSA, indicates the starting address of the associated microprocess.

Word 5, ABWZA, indicates the absolute address of the work field that will be used in the microprocess as a base address.

Word 6, designated 'IOM, will be discussed below.

The single byte of word 7 is not important to this invention. Bits 8-15 of word 7 define the so-called YREDY field indicating why the associated microprocess changed its state.

After the microprocess is started, the YREDY field is stored in register R1 of dual register bank 210 in FIG.
(not shown). Bit 11, bit A of word 7, indicates that the subsequence state of the microprocess has been moved to the ready state by the microinstruction "Enable" issued in the AFP belonging to that MCB.

Bit 12, bit T of word 7, indicates that the RQTO microcommand has placed the microprocess in a standby state, given a time lapse for its passage to the ready state, and that time has now passed. Other bits of YREDY determine other events.

Accordingly, they indicate that the channel program was issued by the CPU on a special logical channel. AFP is notified of the event and it begins handling the first CCE of that channel program. The PCU is alerted to the event by signal CPW on gate PSI 223 of FIG. The sequence that starts the program is Bean Venue (B
ComputerInterfaceMe
French Patent Application No. 7,342,714 (U.S. Patent Application No. 5,277)
No. 58) It is clearly stated in the specification.

A reference to both of these applications will show the relationship. There is also another bit of YREDY, which is ABO
RT is detected by the MIOS and communicates that the AFP is asked to give up or abruptly stop the channel program in progress. All information contained in the N4CB will only be modified by the microinstruction managing the microprocess that addresses the MCB by its absolute address.

FIG. 7 represents the format of the words CPCW, TQHP and LCM, fields of memory M of FIG. 2 giving a fixed address in memory.

The word CPCW gives the status of microprocesses running on the PCU. Area NPC consists of three bits ranging from bit 0 to bit 2, which indicates the level of the microprocess being executed. Therefore, the size of 3 bits makes it possible to fix or set 6 levels of ordinary microprocesses (A) is not affected and 1 is related to EVl). If the area NPC does not contain n bits, then
It is clear that the NOD-2 level of ordinary microprocesses can be set. Bit M indicates that the sequence is masked, in other words the running microprocess is temporarily at level 2. Bit L indicates that the microprocess is level 2. Bit D indicates that the dispatcher is in service. Bit P indicates that the microprocess is running. Bit M, L
It must be noted that or D corresponds to a microprocess with priority.

Bit F, called ``Flag'', indicates that at least one microprocess has passed to the Ready Queue (RQ) after the last microprocess passed to the ``Desbatcher''.

The event causes a change in the priority of the microprocess. The word TQHP determines the head of the TIMER string.

“The content of the word TQHP is zero when the timer matrix is empty. The timer matrix makes it possible to organize or store microprocesses in the order of their calling times. Set maximum number.

FIG. 8 shows the format of the dispatcher table.

For each priority level, a table is allocated which is placed in the field of memory M in FIG. 2, and its address is calculated from the number of the corresponding level. The first field RQHP indicates the head of the ready matrix at that level. The second field RQTP indicates the tail of the ready matrix at that level. The microprocess at that level has been started but not finished, i.e. the microinstruction. and a third field containing bit B indicating that termination has not been performed. The fourth field and the following fields are for storing registers in the PCU when a microprocess is interrupted by a microprocess with a higher priority. Field DA
N stores the contents of register 208DNR in Figure 2,
The field SP stores the contents of the register SP2l2 of FIG. 2, in which the result of the operation is stored, and the fifth fynold is to be performed at the time of the interruption of the microprocess by the microprocess with a higher priority. Stores the address of the next instruction. The sixth field and the fields following it make it possible to store the contents of the general purpose registers of the registers of the lower bank of dual register bank 210 of FIG. bank). FIG. 9 shows the fixed table ALCT of memory M of FIG. 2, which serves as an interface between the MIOS and the peripherals and associated firmware.

For each logical channel LC, LC is connected to D. A
A table is associated containing the number of l and the address of the first MCB corresponding to that LC. 10A, b, c and FIG. 11 A, b, c respectively show RQ and TQ matrices, which are bidirectional matrices. That is, each MCB in the matrix contains instructions that can connect it to the previous MCB and connect the MCB to its next one. These two lines have the feature that they both use a pointer that represents the first MCB and that it can be moved out of the matrix. The pointers make it possible to indicate through their contents whether a matrix contains at least one MCB. When it is necessary to restore the N4CB to the column from which it was originally emptied, the contents of the pointer will point to the address of that MCB. If the MCB returns to a holding matrix that already contains several MCBs, the NLP and PLP pointers found in the first and second words of the MCB will find the address of the MCB that the NLP will come to next, and the PLP will find the address of the next MCB. M.C.
We must assume a value such that we can find the address of B. When a series of MCBs occurs, the value of the pointer must change according to the address of the MCB,
The addresses of the MCBs are the MCBs that occur in the order of exit.
Dependent on the CB, the value PLP of the subsequent MCB must be updated. Figure 10 shows the preparation matrix R at level N.
Figure 3 shows a series of modes used for Q.

The movement of the MCB follows the "first in" and first out rules. That is, for a given level N, the first activated M
CB is the first performed. These matrices have head pointer RQHPl trailing pointer RQ
These pointers occupy the memory fields defined by the first and second words of the level N table of the dispatcher as defined in FIG. RQHP represents the first MCB in the column and RQTP represents the last MCB. Each MCB is connected to the previous MCB and to the next MCB in the manner already described.
However, the value of the first MCB (7) PLP and the value of the last MCB indicate the address of the pointer RQlIP in the table of the dispatcher at level N, and the value RQTP is R
Indicates the QHP address. FIG. 10 shows a case where signal MCB is continuous on a line. Then RQHP is MCB
NLP indicates the address of RQHP. PLP then indicates the address of the MCB. FIG. 11a shows a series of modes of MCB in a timer ('IQ) matrix.

The timer matrix is circular, and it is the head MCB
If it does not have , it will not have a trailing MCB either. MCB is word 6
(See FIG. 6). Each MCB is connected to the preceding MCB by a representation PLP of MCB word 2, which is connected to the following MCB by a representation NLP of MCB word 1. Pointer TQHP points towards the MCB whose call time is closest. The MCB executes the command “When a special calling time comes or before the calling time comes
It can be removed from the timer matrix by 'activation'. The MCB then passes through the ready queue. The MCB exits the TQ holding matrix by the microinstruction "゜Stop". In all cases, ?■ The value PLP of the next MCB is M
The word PLP in CB will be updated to the value PLP. 1st
If there is only one MCB in the holding matrix TQ in Figure 1c,
The contents of '1QHP are reset to 0 and when MCB exits, the position by convention indicates that the TQ holding matrix is empty.
When any MCB leaves the holding matrix, the value of the previous MCB's NLP becomes the level of the delayed MCB (7) NLP, and the value PLP of successive MCBs becomes the level of the PLP of the delayed MCB.

When an MCB is placed in the timer holding queue, if there is no MCB in the waiting holding queue, the pointer TQHP is set to the first MCB.
Pointing towards the CB address.

Thereafter, NLP and PLP point to their own points as shown in FIG. 11b. Other M waiting in the timer queue
If CBs exist, the MCB is MCB word 6 (
It is placed after the MCB as a function of displaying the contents of the TOM, and its call time is immediately below it. The value of its NLP assumes the value of NLP of the previous MCB, and the value of its PLP assumes the value PLP of the following MCB. The value NLP of the previous MCB and the value PLP of the following MCB will be changed to the address of the MCB just entered in the holding matrix. The arrangement of microprocesses over time, as it is determined by the principles of MIOS and microprocess interaction and illustrated by the functional diagram of FIG. 4, will now be described in detail below of the invention. .
In such a description, the dynamic functionality of the system will be explained with the aid of the aforementioned hardware and firmware (microprograms and tables). FIG. 12 shows the sequence of operations to be performed at the time of a hardware interruption, in other words when the event EVl appears on the adapter or timer of the peripheral device.

If the flip-flop EE2l5 of FIG. 2 had not been placed at O by the microprogram, any signal E1 appearing on one of the DA ports or on the timer would be indicated to the MPU by the signal EVls from the OR gate 220. . The signal EV causes a hardware interruption of the operation being performed, and the hardware registers the dual register bank 210.
The second logic level 1 selects the upper register bank of the
The flip-flop UL2l7 shown in the figure is placed. From that moment on, all operations occur within the upper bank. The contents of register RQSAR2O4 in FIG. 2 are the registers Rl4 and Rl5 (
(not shown). Register DNR2O in Figure 2
The current contents of register 8 are register. Stored in ADNR2O9. The register DNR is then loaded with its new value containing the fixed address of the controller, which is the address of the start of the MIOS process taking into account hardware interruptions.
The MIOS then transfers the encoding device 221 to the register DNR.
In step 1202, the contents of the register NDR2O8 in FIG. 2 loaded by the data line CEV1 connected to the register are read. Register DNR then contains the boat number with the highest priority among all of these sending signal E1. MIOS in step 1203 starts from that number,
Then, the memory address MSAl in the control block of the adapter DACB of the peripheral device corresponding to the selected DA-1 boat is obtained. The memory address constitutes the starting address of the E1 microprocess that must be executed on the selected peripheral adapter.

In step 1204 of FIG. 12, the contents of register SP2l2 of FIG.
0 is stored in a special register R7 (not shown) in the upper bank of registers. Step 120 in Figure 12
5 takes a branch at address MSAl, and if E1 is not timer EVl, the AFP microprocess EVl corresponding to the selected device adapter of the peripheral is started (step 1207). This EVl microprocess ends with a microinstruction RAI that will cause flip-flop UL to be returned to O, register . Restore the contents of ADNR to register DNR. RAI also branches indirectly to upper registers RE and RF to obtain the return address of the suspended microprocess. In the case of the timer EV1, steps 1208 and 1209 consist in seeing whether the MCB of the "TIMER" file (see FIG. 2) exists, so that time is moved to the ready queue. Step 1208
At , the MIOS comes and reads the word 'IQHP (see FIG. 7) with a fixed address in memory. 'I
If the contents of the QHP are empty, the MIOS passes control to step 1216, which determines whether there are any microprocesses in the process that have priority. TQ]1
If the contents of P are not empty, MIOS comes and TQlI
The contents of word 6 or TOM (step 1209) (see FIG. 6) are read into the MCB indicated by P (see FIG. 11). If the content of TOM is O, MIOS is TOM
is reduced to 1 and passes control to step 1216. When the content of TOM is equal to O, this means that the ready matrix is "timed to pass the MCB from the timer matrix, the MCB is sent out from the TQ matrix, and the ready matrix corresponding to its priority level is Bit RQ, or bit 12, of word 0 of the MCB corresponding to FIG.
is set to 1 in step 1212. Word CPCW (7th
Bit F of the figure), that is, “゜flag” is set to 1,
The microprocess is indicated in step 1213 to become a ready matrix. Bit T is placed in the YREDY byte of the corresponding MCB in step 1214. The control of the timer matrix is 19 under the name of Labalme.
“Method and Apparatus for Requiring Early Handling of Randomly Distributed Calls and Response Delays for Arbitrary Deviations Sorted to Name Calls” filed on September 25, 2013
ethOdandAPParatlJSfOrPrOc
essingCallsDistrjbutedRan
dOmIyInTimeandRequiringRe
spOnseDelaysOfDeviatiOn,b
1 corresponding to U.S. Patent Application No. 400,578 entitled utSpecifiedfOrEAchcaI
French Patent Application No. 7234 filed on September 29, 9η
It is specified in the specification of No. 508. The relationship between these two applications can be seen by reference. In step 1216, MIOS looks for the microprocess in the process that has priority and reads the state of bits D, L, and M from word CPCW until its termination.

If D is equal to 1, the dispatcher is in progress.

If L is equal to 1, the suspended microprocess is at level 2. If M is equal to 1, the sequence is masked and the microprocess is temporarily at level 2.

Therefore, if D is equal to 1 and L is equal to 1 or M is equal to 1, then the suspended microprocess has the highest priority and is re-executed at step 1218.

Microphone interrupted. If no process has priority, step 217 is checking to see if EV2 is present. Returning to FIG. 2, the signal at the output of AND gate 233 when the timer boat is selected.

EV2s indicates whether there is at least one signal E2 appearing on one of the DAI or PSI ports.
Such global inspection benefits execution efficiency.
If bit F of word CPCW is 1, which is clearly the case when MIOS has performed the operation, the flag is equal to 1 in step 1213. But the flag is MI
It is necessarily not equal to 1 if the OS passes directly from step 1208 or step 1209 to step 1216. Testing bit F also results in an increase in execution efficiency (and therefore MIOS performance) since the ready matrix is scanned only when the priority of a running microprocess can be explored. If F is equal to 0, the interrupted microprocess is restarted at step 1218.

It is known that when the dispatcher is not running (D equals O), the microprocess in progress is interrupted.

The despatcher can only be interrupted at some well-defined point, called the "despatch window", passing through the various DA(7)EVl breaks. When F is equal to 1, step 1300 is performed. is being input into the system, and the various lines of readiness for each priority level are being analyzed. The thirteenth is a flowchart showing the functions of the despatcher.

When the dispatcher is input, bit D of word CPCW is set to one. Bit F of word CPCW is step 1
It is returned to 0 in step 302, and the MIOS
scans to determine if any EV2 is waiting. If EV2 is waiting, register DN
R is set back to 0 and MIOS checks whether any EV2 corresponding to DNR is equal to 0. Such E
Without V2, register DNR would be increased to 1 and therefore equal to 1. MIOS again checks if there are other EV2s corresponding to that DNR number, E
■If 2 does not exist, the contents of DNR are increased to 1 again and this is repeated until the value Q is reached. Q is PCU
corresponds to the number assigned to (Q is equal to tan+■,
Here -p- is PSI numbered from O to p-1
This is the boat number, and dan is the DAI boat number numbered from ■ to ■ 10-1). Value DNR p-
If there is an event waiting for 1, the event belongs to the PSI boat. Then the corresponding MIOS
The microprogram begins at step 1316 and ends with the instruction "End", the result of which is represented in the diagram of FIG. 17 with the start step numbered 1700.

If there is a waiting EV2 for the value p and DNR<-p+n-1, then that EV2 belongs to the DAI boat.
The corresponding microprogram is then started unless bit E of the device adapter control block DACB is equal to 1, ie the corresponding DA(7)E2 is not masked. If bit E is equal to 1, MIOS returns to step 1307, the contents of register DNR is raised to 1, and scanning for E2 begins again. If bit E is equal to O, MIOS passes to step 1400 of FIG. If E■2 does not exist, MI
The OS passes to step 1309 and checks whether the ready matrix at that level is empty. Until its end, it is checked in the despatches table corresponding to that level (
(See Figure 8). The content of word 1 of the distribution table at that level RQI (If P refers to itself, then the line is empty.
If the line is not empty, MIOS retrieves the MCB at the head of the ready-to-hold matrix at that level and it is used in step 1.
500 (see Figure 15). If the line is empty, MIOS is step 1
310 and looks for possible MCBs that appear in the ready queue at level 3. MIOS is level 3 to level 7
(i.e., addition-1) operates in the following manner for each level N. In step 1311, it
Examine bit B in word 3 of the dispatcher table at level N of the diagram. When B is equal to 1, it means that the level N microprocess has been started and has not yet finished, in which case MIOS passes to step 1600 (see FIG. 16) to return to the interrupted microprocess. When B equals O, the first word RQHP in the dispatcher table at that level is checked. If the ready-to-hold matrix (level N) is empty, MIOS passes to step 1313 at level N+1; if it is empty, the normal microprocess corresponding to the first MCB of the ready-to-hold matrix at that level passes to step 1500. will be started. The process continues until level N equals +-1. If MIOS does not find the MCB at any of its levels (step 1314), it
It returns to 0 and the dispatcher is started again. FIG. 14 is a flowchart showing the starting mechanism of microprocess E2.

The initiation of microprocess EV2 begins at step 1400. From the calculated value DNR (step 1307), MIOS searches for the starting address of microprocess EV2, address MSA2, in the control block (DACB word 2) of the corresponding peripheral adapter (step 140).
1). The MIOS then looks for the address of working field WZA2 of word 3 of the corresponding DACB and loads it into registers R4 and R5 (not shown) of the lower register bank pair of dual register bank 210 in FIG. (step 1402). In step 1403, bit L of word CPCW is set to 1 to indicate that the microprocess being started is a level 2 microprocess. In step 1404,
MIOS checks bit P of word CPCW. If P is equal to 0, there are no microprocesses executing before the interruption. MIOS passes to step 1406. Step 1
If P is equal to 1 at 405, the contents of the registers of the suspended microprocess with lower priority are stored in the table of the dispatcher corresponding to that level (see FIG. 8). In step 1406, bit D is set to 0, and in step 1407, bit P is set to 1, and step 1
The level of the microprocess to be performed at 408 is transferred to the word CPCW(7) NCP field. In step 1409, bit B is set to 1 in the dispatcher table corresponding to that level, indicating that a microprocess is being performed.

At step 1410, the flip-flop UL (FIG. 2)
is set to 0 and microprocess EV2 is started in step 1411. FIG. 15 is Flowchart 1, which begins at step 1500 and represents the steps necessary for the initiation of a level N conventional microprocess.

In step 1501, the microprocess is removed from the ready queue, and then the bit RQ of the microprocess control block MCB corresponding to the microprocess is reset to zero. In step 1502, the YREDY byte is returned to O of the MCB, after which the next state of the microprocess is unplanned. In step 1503, the MIOS
Check the status of bit S of ACB. If S is equal to 1, the peripheral adapter is stopped, the microprocess is disconnected, and the MIOS returns to step 1315 and the first
The process of FIG. 3 begins again at step 1312. If bit S is 0, the D found in byte 1 of the MCB
, the AI boat number is entered in the register DN in step 1504.
loaded on R. If this is a level 2 microprocess, the test at step 1505 returns MIOS to step 1411 and the process of FIG. 14 begins at step 1403. If this is not a level 2 microprocess, MIOS returns to step 1412 and the process of FIG. 14 begins at step 1404. FIG. 16 is a flowchart representing the steps necessary to return to an interrupted microprocess. The beginning of the process is indicated at step 1600. Step 16
At 01, MIOS checks bit P of word CPCW.
When P equals 1, the suspended microprocess is suspended by timer EVl and its registers are not destroyed;
The operation passes directly to step 1603. When P is equal to O, this means that the microprocess under consideration terminates with the instruction “End”. The contents of the registers of the suspended microprocess are restored from the reserved field of the dispatcher table corresponding to its level. and the return address is re-stored. In step 1603, bit D
is set to 0, bit P is set to 1, and the word CPCW(7) NCP byte is set to the corresponding value of the suspended microprocess, which is restarted.
Also, in step 1603, the flip-flop UL
is set to O. Return to the interrupted microprocess is accomplished in step 1604 (its current execution state is again ``running''). As shown in FIG. 3, the passage of a microprocess from one state to another takes place with the aid of microinstructions.

Figures 17-20 illustrate these effects that occur with these microinstructions. FIG. 17 is a flowchart illustrating the process governed by the microinstruction ``End'' in step 1700. Bits P, M and L of word CPCW are set to 0 in step 1701. Step 17
At 02, bit B is set to O in the dispatcher's table corresponding to the level N microprocess whose work was completed with instruction '4 exit 1'. In step 1703, the running microprocess is inhibited and the MIO
S is the first step 130 of dispatcher unconditional branching
Go towards 0. FIG. 18 is a flowchart illustrating the process controlled by the "activate" microinstruction at step 1800.

Step 1801 is checking bit RQ. If bit RQ is equal to 1, the MCB is already in the ready queue and then MIOS passes directly to step 1807. When RQ is equal to O, MIOS checks bit TQ. If bit TQ is equal to 1, MCB steps 1
At 803, the bit? is reset to O in step 1804. MCB is step 1
At 805, it moves to the preparation queue. Bit RQ and flag are returned to 1 in step 1806. Step 1807
In this case, bit 1 of YREDY is set to 1, indicating that the MCB is activated. In step 1802, if TQ is equal to 0, the MCB is not in the holding queue and the MIOS passes to step 1805 and the MCB is placed directly in the ready holding queue. Step 1808 depicts the termination of the process and return to the active microprocess that generated the microinstruction "〈〉Activate." Figure 19 shows the effects that occur with the microinstruction ``Stop'' in step 1900.

In step 1901, MIOS checks the state of bit TQ of the MCB. If (d) is equal to 1, it is taken out of the MCB timer holding matrix. If TQ is not equal to 1, M
IOS checks in step 1902 whether the MCB is in the ready queue. If so, the MCB is removed from the waiting queue at step 1904. Otherwise, it means the MCB is not flat and the process will stop. Figure 20 shows step 2000
The effect caused by the microinstruction RQTU is shown in FIG. Step 2001 is checking bit RQ of the MCB. If RQ is equal to 1, the MCB is already in the ready queue and the microinstruction has no effect, in which case the process stops at step 2002. If RQ is equal to O, pass to step 2003 where bit TQ is being checked.
If TQ is equal to 1, the MCB is in the timer matrix and the MCB is removed from the type matrix in step 2004 to update the TOM for word 6.
The instruction corresponding to the new value of M will put the MCB back into the "timer holding matrix". is marked in the TOM field of word 6. In step 2007, bit TQ is 1
is set, and its effect ends. Figures 21-24
The diagram represents the effects that occur at the time of execution of each masking and unmasking microinstruction.

FIG. 21 shows that everything is masked when there is no microprocess E1.

Bit M of word CPCW remains in step 2101 until its end.
1 (the microprocess is then temporarily considered to be at level 2, i.e. it cannot be interrupted by other ordinary microprocesses (see the microprocess with the highest priority in Figure 12). 2
Figure 2 shows the corresponding non-mask.

At its end, word CPCW is set to 0 in step 2201. Figure 23 shows the AFP that executes the microinstruction.
Indicates that EV2 of the peripheral device adapter corresponding to .

At its end, in step 2301, bit E of DACB corresponding to the contents of register DNR is set to 1. Second
Figure 4 shows the corresponding non-mask.

At its end, bit E is set to 0 in step 2401. FIG. 25 shows the effects caused by microinstruction STDA, which halts all operations in the peripheral adapter.

Bit S of word 6 of the DACB is set to 1 in step 2501 to indicate that the corresponding peripheral adapter is isolated and there is no other activity on the peripheral adapter. By reading the contents of the NPC field in step 2502, the MIOS reads the level of the executing microprocess in the word CPCW. Step 2503,2
504, 2505, and 2506 attempt to locate the suspended microprocess at level N+1 belonging to a peripheral adapter, and reset bit B of the level N+1 dispatcher table corresponding to that peripheral adapter to O.

Then the operation is level 7 for all other levels.
In other words, it continues until level 1. At step 2504,
If N is greater than 1, and the flip-flop UL is equal to 1 (that is, if it is the microprocess EVl that requested execution)
S passes to step 1219 on the input side of the dispatcher, and if it is not the microprocess E1 and the microprocess that requested execution is terminated, MIOS passes to step 1700 with the microinstruction ゜゜end゛. This device knows that all microprocesses that are running and have been suspended (those with bit B equal to 1 for that peripheral adapter) are immediately killed.

Other microprocesses (those in holding matrices RQ and TQ) will be cut off at the time of their start (see step 1503). The above-described frameware represents only one aspect of the form that can be implemented, and those skilled in the art of developing computer technology will be able to provide the following without departing from the scope of this invention:
Obviously, many other forms of performance are conceivable.

Glossary Firmware - A device and its associated circuitry consisting essentially of read-only or fixed memory, and used to store microprocesses for controlling repetitive functions, such as controlling peripheral devices. do.

Hardware - Includes all of the physical elements of a computer, including equipment, organs, or whatever elements are used.

Bit - Represents a binary number.

゛Byte Represents a binary number consisting of one or more bits.

DA-Term 6'Device Adapter
An abbreviation of tOr), which stands for an adapter for the device. D.A.
I-1 The term “Device Adapter Interface (Devj
ceAdaPt (1) RInterface) 25 abbreviation, represents the interface of the adapter for the device.

PSI terminology ゜゜Peripheral subsystem interface (PeripheralSLlbSyStemInte)
rface), which stands for the interface between the central unit of the peripheral device and the input/output controller of the central unit.

MPU-Term “゜Multi-processing peripheral unit”
prOcessingPeripheralUnit)
'5 or an abbreviation for microprogrammed unit for controlling peripheral devices.

ICU-Term “゜Interface control unit (I)
nterfaceCONtrOlUnit) 5', represents the interface between the 1 and various PSI and DAI interfaces.

Assembling A technique of rearranging parts of the same program or several different programs together that must be performed either simultaneously or in succession.

Dispatcher - Micro process distributor.

Logical Channels - The mode of access used to perform input/output operations between the central unit and peripheral devices is called a channel. The channels consist of physical channels containing the hardware sources for connecting the input/output controller of the central unit with the peripheral devices and logical channels containing all the complex means necessary to perform the input/output operations. Input/output operations are determined by channel programs. A logical channel can only have one active program at a time. The logical channel number is used by the channel to facilitate storage of requested parameters and to maintain several channel programs in progress at the same time. From a software perspective, the device has an input/output control number,
Confirmed by several physical and logical channels. Channel programs are assigned to devices. A logical channel number is assigned to a device during system configuration or when the device is added to the system. There may be more than one logical channel per device. A logical channel is considered to be effective from the time a channel program is initiated by a software instruction until the same is terminated. Cause of ABORT 1
An action to immediately stop an operation being performed by a peripheral device may be required by any element making up the system (CP
SW in U or FW or HW or CP in CPU
U or PW).

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a preferred form of the device according to the invention, including a central processing unit (CPU), a peripheral control unit (PCU) and various peripheral adapters DA;
The figure is a block diagram of the peripheral control unit PCU shown in Figure 1, Figure 3 is a diagram showing state transitions of various microprocesses, and Figure 4 is a block diagram of the peripheral control unit PCU shown in Figure 1. Flowchart for explaining the operations that occur; FIG. 5 shows the format of the peripheral adapter control block DACB; FIG. 6 shows the format of the microprocess control block MCB; FIG. 7 shows the word CPCW. TQHP and L
FIG. 8 is a diagram showing the format of the dispatcher table, and FIG. 9 is a diagram showing the format of the dispatcher table. Al. Figures showing the format of CT; Figures 10A, b, and c are diagrams representing the combination of MCBs in the preparation matrix; Figure 11;
12 is a flowchart showing the sequence of actions that must be taken when the event EVl appears on a peripheral adapter or timer; FIG. 13 shows the function of the distributor or microprocess despatcher. 14 is a flowchart showing the starting mechanism of microprocess EV2, FIG. 15 is a flowchart showing the start of a normal microprocess, and FIG. 16 is a flowchart showing the steps necessary to return to an interrupted microprocess. , FIG. 17 is a flowchart showing the actions that occur as a result of the microinstruction "End", FIG. 18 is a flowchart showing the actions that occur as a result of the microinstruction "Activate", and FIG. 19 is a flowchart showing the actions that occur as a result of the microinstruction "Stop". FIG. 20 is a flowchart showing the action that causes the microinstruction “゜RQT0” to occur, and FIG. 21 is a flowchart showing the action that occurs when the
22 is a flowchart showing the corresponding unmasked operation; FIG. 23 is a flowchart showing masking of the EV2 operation of a peripheral device adapter; FIG. 24 is a flowchart showing the unmasking of the corresponding E■2 operation, and FIG. 25 is a microinstruction S″M.
It is a flowchart which shows the effect|action which causes A successively. In the figure, 10 is a central processing unit CPUllOl is a peripheral control unit PCUllO2-105 is a peripheral device adapter DAllO6-109 is a peripheral device Pl2OO is a multi-processing peripheral unit MPUl202 is a memory Ml2O4 is a register ROSARl2O6 is an operator, 208 is a register DNR, 209 is a register ADNRl2lO is a dual register bank, 211 is an arithmetic and logic unit, 212
The register PRl2l5 is the flip-flop EEl2l
7 is a flip-flop ULl233 is a PSI boat, 2
34 is a DAI boat, and 236 is an interface control unit ICU.

Claims (1)

[Claims] 1 Central processing unit CPU through I/O channel PSI
to synchronize simultaneous control tasks in a plurality of different peripheral devices connected to a high-priority task that is initialized by interrupt signals EV_1 and EV_2 and is not addressable by other tasks. , C.P.
Control of a data processing unit that performs a task interrupt mechanism with lower priority tasks that have the normal job of transferring data between U peripherals and are addressable by other tasks. The device includes an independent processor MPU 200 and a memory 202, and the memory 2
02 is: 1. A memory block (CPCW, Fig. 7) for identifying the state of the task being executed; 2. A task control block MCB for controlling normal tasks; 3. Peripheral equipment for the highest priority task. block DACB for the control of 4 memory blocks accommodating tables of parameters for the working of the processor MPU, each peripheral device Pj is associated with its own control block DACB, and each control block D.A.
A control device for a data processing device, characterized in that the CB includes means for identifying the task control block MCB associated with the corresponding peripheral device Pj. 2. A timer state indicating that the microprocess can be executed only after the expiration of a predetermined period of time, a ready state indicating that the microprocess is always in a state of being executed, and a null state indicating that there is no plan for the microprocess. 2. A control device for a data processing system as claimed in claim 1, including means for assigning one of the three planning states to each common microprocess. 3. Each of the blocks MCB for the control of a normal task contains an indicator word TOM representing the calling time of the task so that it can be placed in a preparation queue. control unit for data processing equipment. 4. means for managing ready microprocesses having the same priority level in a queue of said microprocesses, storing a head word for identifying the microprocesses at the head of the queue; means for storing an identifying suffix, means for storing in the queue a next pointer in association with each microprocess that identifies the next microprocess in the queue, and before identifying a previous microprocess in the queue; 4. A control device for a data processing device according to claim 3, further comprising means for storing a pointer in a queue in association with each microprocess. 5 a first memory field containing a starting address for execution of a first microprocess having a first priority level associated with a first event signal received from a first device of said peripheral; a second memory field identifying a working memory field for execution of the microprocess, having a second priority level associated with a second event signal received from the first peripheral; a fourth memory field identifying a working memory field for execution for the second microprocess; a number of the logical channel associated with the first peripheral; a fifth memory field containing the highest number of logical channels connected to the first peripheral; a first bit indicating that the second event signal is masked; and all operations of the first peripheral are stopped; 5. A control device for a data processing device as claimed in claim 4, further comprising means for controlling a peripheral device by storing a sixth memory field containing a second bit indicating that the second bit is indicative of the sixth memory field. 6. said ordinary microprocess is represented by 2n-n levels, said means for identifying microprocess characteristics comprising means for storing an n-bit word NPC representing the priority level of the microprocess running the transfer data; means for storing M bits of a masked sequence that can temporarily place a microprocess in the process of transferring data with a priority level of means for storing bits, a P bit indicating that the microprocess is in the process of transferring data, and an F bit indicating that the microprocess has passed into the preparation queue of the microprocess to be executed; 6. A control device for a data processing device according to claim 5, further comprising storage means. 7. Means responsive to the first event signal for reading a register containing a number corresponding to the first peripheral device and representing a starting address stored in the first memory field. A control device for the data processing device described. 8 means for initiating execution of a first microprocess in response to said first event signal; means for generating a periodic timer signal; decided to be,
8. A data processing apparatus controller as claimed in claim 7, further comprising means for determining that a predetermined period of time associated with a predetermined microprocess has expired and placing the predetermined microprocess in a preparation queue. 9. A means is provided for returning the microprocess to the transfer data process having the first or second priority level without interrupting the second class microprocess or the first class microprocess having the second priority level. A control device for a data processing device according to claim 8.