JPS6047329U - timer circuit - Google Patents

timer circuit

Info

Publication number
JPS6047329U
JPS6047329U JP14078683U JP14078683U JPS6047329U JP S6047329 U JPS6047329 U JP S6047329U JP 14078683 U JP14078683 U JP 14078683U JP 14078683 U JP14078683 U JP 14078683U JP S6047329 U JPS6047329 U JP S6047329U
Authority
JP
Japan
Prior art keywords
circuit
switch circuit
timer
push
operates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14078683U
Other languages
Japanese (ja)
Other versions
JPH04587Y2 (en
Inventor
大石 靖雄
Original Assignee
カイセ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by カイセ株式会社 filed Critical カイセ株式会社
Priority to JP14078683U priority Critical patent/JPS6047329U/en
Publication of JPS6047329U publication Critical patent/JPS6047329U/en
Application granted granted Critical
Publication of JPH04587Y2 publication Critical patent/JPH04587Y2/ja
Granted legal-status Critical Current

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  • Relay Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係るタイマ回路のブロック図、第2図
はコンデンサの放電時間をタイマ時間とした回路図、第
3図はコンデンアの充電時間をタイマ時間とした回路図
である。 1・・・・・・入力端子、1a・・・・・・十入力端子
、1b・・・″・・・−入力端子、2・・・・・・電池
、2a・・・・・・接続点、3・・・・・・出力端子、
3a・・・・・・十出力端子、3b・・・・・・−出力
端子、4・・・・・・制御回路、4a・・・・・・トラ
ンジスタ、4b・・・・・・抵抗、5・・・・・・遅延
回路、5a・・・・・・コンデンサ、5b・・・・・・
抵抗、6・・・・・・セットスイッチ回路、6a・・・
・・・常時開接点、6b・・・・・・操作部、7・・・
・・・リセットスイッチ回路、7 a、 7 b・・・
・・・抵L ”t by 7 C? 7 e−−−−−
−トランジスタ 1111**@1111スイッチ回路
、8a・・・・・・抵抗、8a・・・・・・常時開接点
、8c・・・・・・操作部。
FIG. 1 is a block diagram of a timer circuit according to the present invention, FIG. 2 is a circuit diagram in which the capacitor discharging time is set as timer time, and FIG. 3 is a circuit diagram in which capacitor charging time is set as timer time. 1...Input terminal, 1a...10 input terminal, 1b...''-input terminal, 2...Battery, 2a...Connection Point, 3...Output terminal,
3a...10 output terminals, 3b...-output terminals, 4...control circuit, 4a...transistor, 4b...resistance, 5...Delay circuit, 5a...Capacitor, 5b...
Resistor, 6...Set switch circuit, 6a...
...Normally open contact, 6b...Operation unit, 7...
...Reset switch circuit, 7a, 7b...
・・・Resistance L ”t by 7 C? 7 e------
-Transistor 1111**@1111 switch circuit, 8a...Resistor, 8a...Normally open contact, 8c...Operation unit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] コンデンサと抵抗とから成り、セットスイッチ回路のO
Nによりタイマ動作が開始され、リセットスイッチ回路
のONによりタイマ動作が途中で中止される遅延回路と
、遅延回路によって駆動され、タイマ動作中は負荷に電
力を供給する制御回路と、遅延回路とは別に制御回路を
駆動して負荷に電力を供給するスイッチ回路と、前記セ
ットスイッチ回路を操作する押ボタン式の操作部と、前
記リセットスイッチ回路と前記スイッチ回路とを共に操
作する押ボタン式の操作部とから成るタイマ回路。
The set switch circuit consists of a capacitor and a resistor.
A delay circuit that starts timer operation by N and stops the timer operation midway by turning on the reset switch circuit, a control circuit that is driven by the delay circuit and supplies power to the load during timer operation, and a delay circuit. A switch circuit that separately drives a control circuit to supply power to a load, a push-button operation unit that operates the set switch circuit, and a push-button operation that operates both the reset switch circuit and the switch circuit. A timer circuit consisting of parts.
JP14078683U 1983-09-09 1983-09-09 timer circuit Granted JPS6047329U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14078683U JPS6047329U (en) 1983-09-09 1983-09-09 timer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14078683U JPS6047329U (en) 1983-09-09 1983-09-09 timer circuit

Publications (2)

Publication Number Publication Date
JPS6047329U true JPS6047329U (en) 1985-04-03
JPH04587Y2 JPH04587Y2 (en) 1992-01-09

Family

ID=30315088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14078683U Granted JPS6047329U (en) 1983-09-09 1983-09-09 timer circuit

Country Status (1)

Country Link
JP (1) JPS6047329U (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599830A (en) * 1979-01-25 1980-07-30 Matsushita Electric Ind Co Ltd Timer circuit
JPS55115135U (en) * 1979-02-09 1980-08-14
JPS55152727U (en) * 1979-04-19 1980-11-04
JPS55157343U (en) * 1979-04-26 1980-11-12

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599830A (en) * 1979-01-25 1980-07-30 Matsushita Electric Ind Co Ltd Timer circuit
JPS55115135U (en) * 1979-02-09 1980-08-14
JPS55152727U (en) * 1979-04-19 1980-11-04
JPS55157343U (en) * 1979-04-26 1980-11-12

Also Published As

Publication number Publication date
JPH04587Y2 (en) 1992-01-09

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