JPS6046066A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to readily form a high integration and large capacity memory in which no error occurs in the discrimination of information from a memory cell by differentiating the capacity values of the first and second capacitance elements by the number of fine holes without differentiating the size of the fine holes. CONSTITUTION:A memory cell has an MISFETQ14 for a switch and a capacitance element C14, the element C14 is composed of the entire inner surfaces of two fine holes (of a polycrystalline Si layer 6) and part of the surface of a semiconductor substrate 8, a dummy cell is composed of an MISFETQD12 for a switch, a capacitance element CD12, and the element CD12 is composed of the entire inner surface of one fine hole (of the layer 6) and part of the surface of the substrate 8. Since the holes 6 are all formed in the same shape, the all fine holes can have the same capacity. Accordingly, the capacity ratio of the memory cell to the dummy cell determined by the ratio of the number of the fine holes of the same shape can be very accurate as compared with the conventional one.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a highly integrated memory semiconductor device, and more particularly to a memory cell useful in application to a large capacity, highly integrated memory semiconductor device.

[Background technology]

In a dynamic memory semiconductor device (hereinafter referred to as D-RAMIC) in which information is held in an MIS type capacity, memory cells are formed small to achieve high integration. The difference in the amount of accumulated charge between the first and second charge accumulation states of the capacitor is minute. In order to detect this minute amount of charge, the D-RAMIC is provided with a dummy cell having an MI8 capacitor that stores an intermediate amount of charge between the amount of charge stored in the MI8 capacitors of the first and second memory cells. Information on a memory cell is recognized based on whether the amount of charge stored in the MIS capacitor of the memory cell is larger or smaller than the amount of charge stored in the MIS capacitor of the dummy cell. Since the difference between the first and second accumulated charges of the memory cell is extremely small, several tens of mV, the capacitance CD of the dummy cell
8 is exactly half of the memory cell capacity C8 (
CD8=CB/2) is desirable.

On the other hand, as one of the means to achieve high integration of D-RAMIC, a technology (hereinafter referred to as CCC (Corr.
UGated Capacitor Cell structure) is shown in Japanese Patent Application Laid-Open No. 130178/1983. This method involves creating pores in a semiconductor substrate, burying polycrystalline silicon in the pores with a thin insulating film in between, and
Forms IS capacity. This allows the surface of the inner wall of the pore to be used as a capacitor.

However, the present inventor has discovered that the D-RA of the CCC structure
I discovered that there are problems in the table below when implementing MIC.

That is, the present inventor has developed a D-RAMI using the CCC structure.
In C, the capacitance ratio between the MIS capacitance of the dummy cell and the MIf9 capacitance of the memory cell is determined by the above-mentioned CD8-〇s/2.
In order to satisfy this relationship, the size of the pores that act as capacitors was adjusted. (1) The total area inside each of the pores of the memory cell and the dummy cell, and the sum of the areas of the side and bottom surfaces of the pores were set to be 2:1. When forming pores in memory cells and dummy cells in such a method, the area of the opening must be changed depending on the total area of the pore.

However, according to the experiments of the present inventors, it is difficult to form the pores so that the total area inside the pores is 2:1 as described above using such a method. The reason for this is as follows, according to the studies of the present inventors. First, when a silicon semiconductor substrate is selectively removed by etching to form pores, the etching speed changes depending on the amount of silicon etched. That is, the etching rate of silicon, that is, the amount of etching depends on the amount of etching itself. Etching amount (volume inside pores)
When forming pores with different pores, it is difficult to control the amount of etching within each pore. Therefore, it is difficult to obtain the inner area of the pores of both the memory cell and the dummy cell as designed, and it is also difficult to change the designed value in advance in accordance with the amount of etching. In addition,
The etching rate in the pores of the memory cell is also smaller than that of the dummy cell. Further, due to mask misalignment, etc., the value of the area of the pore portion varies.

Therefore, the ratio of the capacitance of the memory cell and the dummy cell is exactly 2.
However, it is difficult to form a memory cell with a value of 1, and there is a problem in determining the information in the memory cell by comparing it with the amount of charge stored in the capacitance of the dummy cell.

[Purpose of the invention]

An object of the present invention is to provide a system for realizing a large capacity, highly integrated memory semiconductor device.

Another object of the present invention is to provide a large-capacity, highly integrated memory semiconductor device having a CCC structure having pores with no manufacturing variation in charge capacity.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by forming a different number of pores of the same shape in a capacitive element that stores information with different capacitances and a capacitive element that obtains a reference signal for discriminating the information of this capacitive element, the capacitance can be increased. The purpose of this invention is to determine the capacitance ratio of different capacitive elements.

〔Example〕

The present invention will be described below using an example.

FIG. 4 is an equivalent circuit diagram of a portion of a D-RAM semiconductor device to which the present invention is applied.

MIt t MI! ...indicates a memory cell. Each memory cell is MI8FETQ for switch,...
Q□... and the capacitive elements CII and CI! that are connected to this and are used to store information. It consists of... MI 8
FET Qo.

QI! The gate electrodes of . . . are connected to a word line WL for selecting a memory cell. One of the two electrodes consisting of semiconductor regions provided on both sides of the gate electrode is connected to the bit line BL, and the other is connected to the capacitive element CllIC12.
Connected to one electrode of... Capacitive element CII +
The other electrode of CII... is connected to a constant potential, for example, a power supply potential VCC (eg, 5V).

Dup D12... indicates a dummy cell. Each dummy cell is MISFETQD1□'QD for switch.
I□... and a capacitive element CD1l l C for charge storage
DI□... and CD1l l CDI of this capacitive element
□ MISFFi that reliably discharges the amount of charge of...
It consists of TCQ. MI S FBT QDII p C
The gate electrodes of D12... are connected to a word line WL for selecting a dummy cell.

One of two electrodes made of semiconductor regions provided on both sides of the gate electrode is connected to the bit line BL, and the other is connected to one electrode of the capacitive element CD1l l CD12 . . . . The other electrodes of the capacitive elements CD1l l CD□2... are connected to, for example, a power supply potential ■Cc. The capacitive element CD1□l CDI□ of the dummy cell has a capacitance that is 1/2 of the capacitive element CII r CIt . . . of the memory cell. The memory cells and dummy cells are arranged in rows and columns to form a memory cell array and a dummy cell array.

SA, SA2... are a pair of corresponding memory cells.
This is a sense amplifier for detecting and amplifying the difference in the amount of charge accumulated in the capacitive element of the dummy cell and the capacitive element of the dummy cell. B L+t connected to sense amplifier SA, SA2
, B L 1t , B L□, and BL22 are bit lines, and transmit the amount of charge to the sense amplifier as a corresponding bit line potential. WL 1. WL t, WL
s.

WL4 is a word line; in particular, WL, . . . WL2 contribute to dummy cell selection, and WL, ., WL, contribute to memory cell selection.

Information of memory cell M H1 is transmitted to sense amplifier SA by bit line BL, . This memory cell M
1. The difference between the maximum and minimum amount of charge stored in the capacitor C11, that is, the difference between one value and the other value of the binary level for storing one bit of information, is small. When 5■ or ]■ is applied to one electrode of capacitive element C1, the 0 difference is ・1
"line BL... 0t position 1 differs by 0.15 to 0.2■. When memory cell M, 1 is selected, it is connected to BL, which is the complementary bit line of bit line BL, . Dummy cell D.

is selected. Dummy cell D connected to bit line BL
, 2 transmit the amount of charge accumulated in the capacitor CD□2 to the sense amplifier SA as the potential of the bit line BL+t as a reference signal for determining the information of the memory cell M11. In the sense amplifier SA, the bit line B Lo
, B L st and compares the information of the memory cell and the dummy cell, and amplifies the minute signal.

FIG. 2 is a schematic plan view of part of the memory cells and dummy cells, showing the state in which they are regularly arranged. Region X represents a memory cell portion, and region X2 represents a dummy cell portion. In the figure, portions corresponding to those in FIG. 1 are also shown with their reference numerals.

In the memory cell portion, a bit line 2 made of aluminum and a word line 3 made of a second layer of polycrystalline silicon extend horizontally and vertically in the figure, respectively. The bit line 2 has an ohmic contact (connection) 4 with the memory cell MI8FETQ. In order to make the entire IC smaller, the memory cells are compressed and arranged in the bit line direction. Therefore, the word line extends so as to bypass the contact portion 4. MI8FETQII, Q1
The gate electrodes of 0... are connected to the word lines W L s , W L
4... is integrally formed. Capacitive element CII
As will be described in detail later, two pores constituting r CII... are provided in each memory cell with the same shape. In the figure, it is shown only by dotted lines. In order to make the resistance of the word line WL the same as that of other word lines, the portion 14 not used as a memory cell is also provided with the same shape as the memory cell, and the step difference in the lower layer is made the same as the other portions. Reference numeral 91 denotes an N+ type semiconductor region and a guard ring surrounding a plurality of memories. This region is connected to the power supply voltage VCC, for example,
Absorbs minority carriers and helps prevent soft errors caused by alpha rays. In addition, the shape of the memory cell is such that the rectangular pores are arranged in the closest density, so that the memory cells for 2 bits, which share the connection part 4 with the bit line, have both ends located in the center, as shown in the figure. It has a wide so-called tonk bone type.

In the dummy cell section, the first
A wiring 61 made of polycrystalline silicon in the second layer and wirings 31 and 32 made of polycrystalline silicon in the second layer extend.

The wiring 31 is word line WL, WL2, M I 8
It is formed integrally with the gate electrode of the FET QD process 11QD12. The wiring 32 is formed integrally with the gate electrode of MI8FBTCQ, and has a capacitance CD□1. CD machine 2 discharge signal φ. is applied. One pore constituting the capacitive element CD1l''DI□ is provided in each dummy cell, as will be explained in detail later.The shape is similar to that of the two pores constituting the capacitive element C11°Cat... of the memory cell. It has the same shape as one of the holes.It is shown only by a dotted line in the figure.92 is an N+ type semiconductor region, and MI8
It is formed integrally with the source/drain region of FHTCQ. This region is connected to the ground potential V88 and is used as a wiring.

FIG. 3 shows a plan view and a cross-sectional view of one memory cell M, 4, which is an embodiment of the present invention shown in FIG. Third
The figure (→ is a plan view of the memory cell, and FIG. 3(b) and FIG. 3(C) are cross-sectional views taken along the BB line and DD line of FIG. 3(a), respectively. In (a), the interlayer insulating film is omitted to simplify the drawing.

1 memory cell M, 4 is MISFETQI for switch
4 and a capacitive element CI4.

M I S F E T Q +4 is the gate electrode 3 and the N+ type semiconductor region 93.94 which is the source/drain region.
and a gate insulating film (8i0. film) 15. The gate electrode 3 is made of a second polycrystalline silicon layer and forms part of the word line. N+ type semiconductor regions 93 and 94 are formed on both sides of the gate electrode 3 in a self-aligned manner with the gate electrode 3 by implanting arsenic ions, and serve as source or drain regions.

Region 93 is connected to bit line 2 made of aluminum through connection hole 4 . This area is the memory cell MI
! In the area shared with the 4th insulating layer 12 is a phosphor silicate glass (P2O) film or the like, and is used to insulate the word line and bit line.

Region 94 connects MISFETQ,4 and capacitive element CI4.

The capacitive element CI4 includes a P-type silicon semiconductor substrate 8 as one electrode, an insulating film 10 as a dielectric, and a first polycrystalline silicon layer 6 as the other electrode. As shown in FIG. 3 (→ and FIG. 3(C)), two pores of the same shape are provided in the semiconductor substrate 8. These pores are ccz, +o.

Reactive ion etching using gas
It is preferable to form it by e-on etching. According to this method, pores can be formed with good control. Since it is anisotropic etching, it is possible to form deep holes with small opening areas and side walls substantially perpendicular to the surface. A capacitive element C14 is provided in a portion that is wider in the direction of the ward line than MISFETQ, 4. This portion is covered with the 14th polycrystalline silicon 6.

Parts 6a and 6b of the polycrystalline silicon 6 fill the inside of the pore and at the same time flatten the surface of the portion where the pore is provided, so that the word lN13 ( WLs) and bit line 2 (BLu
) to prevent wire breakage and increase in resistance. Capacitive element CI4
That is, an insulating film 10 is provided in a region surrounded by a thick field insulating film (Sin, film) 7 and covered with the first layer of polycrystalline silicon. This insulating film 1O is made of SiO formed by thermal oxidation of the surface of the semiconductor substrate 8 provided with pores,
A membrane is used. Note that a silicon nitride film or the like may be used instead of this. As described above, the capacitive element CI4 is constituted by the entire inner surfaces of the two pores and a part of the surface of the semiconductor substrate 8.

In the capacitive element C14, an inversion layer or a deep depletion layer (not shown) is formed on the surface of the semiconductor substrate 8 by the voltage Vcc applied to the first polycrystalline silicone layer, which is one electrode. For this purpose, the first polycrystalline silicon layer 6 is integrally provided throughout the memory cell array as a common electrode for a plurality of memory cells. Then, at the end of the memory array, the power supply voltage VCC (for example, 5
V) and remains functional as wiring. The inversion layer or deep depletion layer connects to the N+ type region 94. MISFE
An inversion layer is formed when charges are supplied from the N+ type region 94 to the capacitive element CI4 through TQ+4.

An insulating film 11 is provided to insulate between the first polycrystalline silicon layer 6 and the word line made of the second polycrystalline silicon layer 3. This insulating film 11 is an SiO film obtained by thermally oxidizing the surface of the polycrystalline silicon layer 6.

Simultaneously with the formation of this Sin film 11, the surface of the substrate 80 is also thermally oxidized to obtain a gate insulation M (8i0. film) 15.

Memory cell M1. There is an aluminum wiring 2 which is a bit line above, and a word line 3 made of a second layer of polycrystalline silicon extends in a direction perpendicular to the bit line. The bit line 2 forms an ohmic contact 4 with an N++ semiconductor region 93 which is the source or drain region of the MISFET Q+4.

FIG. 4 shows a plan view and a sectional view of one dummy cell D12, which is an embodiment of the present invention shown in FIG. Fourth
Figure (a) is a plan view of the dummy cell, and Figure 4 (b) is a plan view of the dummy cell.
FIG. 3 is a cross-sectional view taken along line BB in FIG.

In FIG. 4(a), the interlayer insulating film is omitted to simplify the drawing.

One dummy cell D1. is MISFETQD for switch
1□, a capacitive element CD12, and a MISFBTCQ.

The MISFET QD device 2 consists of a gate electrode 3, N++ semiconductor regions 95 and 96 which are source/drain regions, and a gate insulating film (SiO2 film) 15. Gate electrode 3 is 2
The second polycrystalline silicon layer 3 forms a part of the word line WL2 for dummy cell selection.

The N++ semiconductor regions 95 and 96 are formed on both sides of the gate electrode 3 by implanting arsenic ions.
It is formed in a self-aligned manner and acts as a source or drain region. Region 95 is connected through connection hole 4 to bit line 2 (BL+2) made of aluminum. Insulating film 1
Reference numeral 2 is a phosphor silicate glass (PSG) film or the like for insulating the word line and bit line. Region 96 connects MI 8 FET QD1□ and capacitive element CD1□.

The capacitor CD device 2 consists of a P-type silicon semiconductor substrate 8 as one electrode, an insulating film 10 as a dielectric, and a first polycrystalline silicon layer 6 as the other electrode.

As shown in FIGS. 2, 4(a) and 4(b), the semiconductor substrate 8 is provided with pores having the same shape as the two pores of the memory cell. These pores are CCt as already mentioned.

Reactive ion etching (Re-a) using +02 gas
It is preferable to form it by active ion etching). In this way, by making the shapes of the pores, which are the main parts of the capacitive elements of the memory cell and the dummy cell, the same, the capacitance ratio between them can be controlled to approximately 2:1. The volume of one pore, or the amount of silicon etched, is the same for all pores. In reactive ion etching of silicon using CC44+02 gas, the amount of silicon etched, that is, the etching rate, depends on the etching amount itself.

Therefore, if an attempt is made to achieve a 2:1 capacity ratio with pores of different volumes, it will be very difficult to control the amount of etching. If the volume of each pore is the same as in the present invention,
The etching rate will be the same within all pores. Therefore, all the surface shapes of the semiconductor substrate exposed inside the volumetric volume of the pores can be controlled to be approximately the same. Capacitive element CD12
The portion where is provided is covered with the first layer of polycrystalline silicon 6. A portion of this polycrystalline silicon 6 fills the inside of the pore and at the same time flattens the surface of the portion where the pore is provided, thereby preventing disconnection of the bit line 2 (BL12) and increase in resistance. An insulating film 10 is provided in a region surrounded by the capacitive element CD1□, that is, a thick field insulating film (Sin, film) 7 and covered with the first layer of polycrystalline silicon. This insulating film 10 is made of 8i0. A membrane is used. Alternatively, a silicon nitride film or the like may be used instead. As described above, the capacitive element CD□2 is constituted by the entire inner surface of the pore and a part of the surface of the semiconductor substrate 8.

In the capacitive element CD12, the voltage ■ is applied to the first polycrystalline silicon layer, which is one electrode. .

As a result, an inversion layer (not shown) is formed on the surface of the semiconductor substrate 80. For this purpose, the first polycrystalline silicon layer 6 is provided as a common electrode for a plurality of dummy cells.

The end portion of the dummy array is connected to the power supply voltage VCc (for example, 5 V), and remains functional as a wiring. The inversion layer connects to the furnace region 94 . MI8FBTQD1
Charge is supplied from the N+ type region 94 to the capacitive element cD1□ through the capacitor 2, and an inversion layer is formed. At this time, the capacitive element cD
1□ stores 1/2 the amount of charge of the capacitive element CI4.

MISFBT for discharging the charge of capacitive element CD□2
CQ is a gate electrode 13 made of polycrystalline silicon and an N++ semiconductor region 92.97 which is a source or drain region.
and a gate insulating film 15.

Dummy cell D8. There is an aluminum wiring 2 (BL+t) which is a bit line above, and a word lJ made of a second layer of polycrystalline silicon is placed in a direction perpendicular to the bit line.
3 (WLz) is extended. Bit line 2 is MIS
N++ which is the source or drain region of FET QD, □
An ohmic contact 4 is formed with the semiconductor region 95.

According to this method, all the pores in the c c c g structure are formed in the same shape, so there is no difference in the amount of etching caused by the difference in pore size, and all pores have the same capacity. I can have it. Therefore, the capacitance ratio of the capacitive elements of the memory cell and the dummy cell, which is determined by the ratio of the numbers of pores having the same shape, becomes much more accurate than in the past. In the present invention, it is desirable that the area of the region other than the pore portion, which is defined by the field insulating film and in which polycrystalline silicon exists, be reduced to one-half of that of the memory cell.

Note that the charge stored in the area other than the pores is minute and does not override the capacitance ratio of each capacitive element.

If dummy cells and memory cells are formed as described above, -
When comparing the amount of charge accumulated in the pixel elements, it is possible to perform a striking force without causing any deviation.

〔effect〕

(i) The capacitance ratio of the capacitive elements of the memory cell and the dummy cell can be accurately determined only by the number of pores in the CCC structure, and the read level of the memory element can be easily set. Therefore, errors are less likely to occur in determining information from memory cells.

(2) A highly integrated large capacity memory device can be easily formed from (1).

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in this embodiment, an N-channel type semiconductor element is used, but it goes without saying that similar effects can be obtained by using a P-channel type semiconductor element. In this case, the substrate is an N- conductivity type semiconductor substrate, and the source/drain layers are P+
Becomes a conductive layer. Furthermore, although a CCC structure in which only one polycrystalline silicon layer is formed in the pores is used, any CCC structure that utilizes the pores to obtain capacity can be applied. Further, although a 7-osilicate glass film is used as the first passivation film, it may be made of silicon oxide or the like.

Furthermore, the material of the gate electrode 3 is not polycrystalline silicon, but may be a high melting point metal material or its silicide.

Furthermore, a thin 8i0□ film may be formed on the surface of the gate electrode made of polycrystalline silicon by thermal oxidation.

[Application field]

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the memory cell and dummy cell of D-RAMIC having a CCC structure, which is the field of application which is the background of the invention, but it is not limited thereto. The present invention can be applied to a semiconductor device in which MIS type capacitors having different capacitance values are formed and the capacitance ratio is always required to be constant.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing a memory cell portion of a D-RAM semiconductor device to which the present invention is applied, and FIG. 2 is a plan view of a memory cell and dummy cell portion of a D-RAM semiconductor device to which the present invention is applied. FIG. 3(a) shows the D-
3(b) is a sectional view taken along line BB in FIG. 3(a), and FIG. 3(C) is a plan view of a memory cell portion having a CCC structure of a RAM semiconductor device. 4(a) is a plan view of a dummy cell portion having a CCC structure of a D-RAM semiconductor device to which the present invention is applied; FIG. 4(b) is a sectional view taken along the DD line of FIG. FIG. 3 is a cross-sectional view taken along line BB in FIG. 2... Data line made of aluminum, 3... Word line made of polycrystalline silicon, 4... Contact hole, 5... CCC structure formation region, 6... Polycrystal of CCC structure pore Silicon layer, 6a... Pore in 1 mesori cell, 6b... Pore in 1 memory cell, 7... Field insulating film made of silicon oxide, 8... P-conductivity type semiconductor substrate , 92.93, 94, 95.96...
N+ conductivity type semiconductor region, 10, 11, 15... silicon oxide film, 12... Phos7 ossilicate glass film,
13...Gate electrode.

Claims (1)

[Claims] 1. A plurality of memory cells having a first capacitive element having a first capacitance value, a plurality of dummy cells having a second capacitive element having a second capacitance value, and a memory cell and a dummy cell. means for comparing the amount of charge accumulated in each of the capacitive elements, the first and second capacitive elements each having a semiconductor substrate and an insulator that covers at least an inner surface of a pore provided in the substrate. and a conductive layer provided on the insulating film to at least fill the pores, and the first and second capacitance values are determined by the number of pores without making the size of the pores different. A semiconductor device characterized by having different characteristics. 2. The semiconductor device according to claim 1, wherein the first capacitance value is approximately twice the second capacitance value. 3. The first capacitive element has two pores, and the second capacitive element has two pores.
2. The semiconductor device according to claim 1, wherein the capacitive element has one pore.