JPS6045781A - Knocking controller for internal-combustion engine - Google Patents

Abstract

PURPOSE:To prevent each cylinder from knocking even when there is a defference in the occurrance of knocking among cylinders, by storing and holding a finding result of knocking against each of cylinders according to a specified timing signal at every cylinder, while making it reflect on the control of ignition timing in corresponding cylinders. CONSTITUTION:A knocking vibration in each of cylinders in a multicylinder internal-combustion engine VI is detected by a knocking detctor I . Knocking output of the knocking detector is compared with a reference value by a knocking discrimination device II and a fact of whether there is knocking or not is discriminated. This discrimination result is stored in a memory III according to a signal out of a specified timing signal generating device IV at every cylinder. An ignition control device V controls each ignition timing at every cylinder according to the knocking result of each cylinder being stored and held in the memory device III. With this constitution, ignition timing is properly controlled in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a knocking control device for an internal combustion engine that detects the presence or absence of knocking in each cylinder and controls ignition timing for each cylinder.

[Prior art]

Conventionally, devices that detect vibration noise in order to detect the presence or absence of knocking in an internal combustion engine and control the ignition timing (for example,
1=No. 46606) or one that detects vibration acceleration (for example, Japanese Patent Application Laid-open No. 1987-87537), but in both cases knocking is detected by targeting a specific cylinder. In response to knocking, the ignition timing is uniformly delayed even in cylinders where knocking has not occurred, which resulted in a decrease in output and fuel efficiency, which was not appropriate.

[Purpose of the invention]

Therefore, the present invention detects the presence or absence of non-king for each cylinder, and in order to control the ignition timing of the cylinder in which knocking occurs, the determination result of the presence or absence of non-king is transmitted to each cylinder by a timing signal corresponding to the rotational angular position of the engine. The purpose is to accurately understand the state of knocking in each cylinder by storing it in memory and reflecting it in the ignition timing control of the corresponding cylinder, and to appropriately prevent knocking in each cylinder. There is.

[Structure of the invention]

FIG. 1 is an overall configuration diagram for clearly showing the configuration of the present invention, in which ■ is a knocking detector that detects non-king vibration of each cylinder of a multi-cylinder internal combustion engine ■ and generates a non-king output in accordance with this vibration; ■ is a non-king determination means that determines the presence or absence of knocking by determining the magnitude relationship between the average value of the knocking output from this non-king detector and the non-king output; storage means for storing information for each cylinder in accordance with a predetermined timing signal; The ignition control means (2) controls the ignition timing of the engine for each cylinder in accordance with the non-king determination result for each cylinder stored in the storage means (2).

〔Example〕

The present invention will be described below with reference to embodiments shown in the drawings.

FIG. 2 shows an embodiment for detecting internal pressure vibrations of an internal combustion engine, and is applicable to an in-line four-cylinder internal combustion engine. In FIG. 2, 1a to 1d are acupressure detectors made of piezoelectric elements as knocking detectors, and are in the shape of spark plug washers. Detector 1a is a spark plug for the first cylinder, and detector 1b is The detector 1c is attached to the engine together with the spark plug for the second cylinder, the detector 1c is attached to the engine together with the spark plug for the third cylinder, and the detector 1d is attached to the engine together with the spark plug for the fourth cylinder. Note that the non-king detector may be one that detects mechanical vibrations of the engine.

The two people used a crank angle detection sensor, and the configuration diagram is shown in Fig. 3. In Fig. 3, 2a is attached to the crankshaft, and the protrusion position a1 is 10° after the top dead center of the first and fourth cylinders.
a2 is the position 30 degrees after the top dead center of the first and fourth cylinders, a3 is the position 10 degrees after the top dead center of the third and second cylinders, a4 is the third position,
The position is 30 degrees after the top dead center of the second cylinder. Also,
Position a5 at 110° after the top dead center of the first and fourth cylinders and the third,
A protrusion is provided at position a6 at 5110 degrees of top dead center of the second cylinder. 2b is an electromagnetic pickup and is a sensor that outputs a signal at a position facing each protrusion of the disk 2a.

Reference numeral 3 denotes a cylinder discrimination sensor, the configuration of which is shown in FIG. 4, and is built into the distributor. In Fig. 4, 3a is an iron disk with a protrusion in one place, and 3b is an electromagnetic pink-up 2b shown in Fig. 3.
It is the same as , and outputs a signal at a position facing the protrusion of the disc 3a. The position of this protrusion is approximately 20 minutes before the top dead center of the first cylinder.
It is. Amplifiers 4a to 4d have the same circuit configuration, which is composed of a buffer and an amplifier, but since this is well known, the details will be omitted. 5 is a first waveform shaping circuit whose internal circuit is as shown in FIG.
waveform-shapes the output signal.

In FIG. 6, (A) is the crank angle detection sensor 2A.
(B) output signal of the cylinder discrimination sensor 3;
(C) is the output signal of the first waveform shaping circuit 5.

The internal circuit of this first waveform shaping circuit 5 is shown in FIG.

In FIG. 5, 51 is an input terminal, one end of a resistor 52 is connected to the input terminal 51, and the other end is commonly connected to the resistor 53, the positive electrode of a diode 54, and the negative electrode of a diode 55. The other end of the resistor 53 is connected to the inverting input terminal of a comparator 59 made of an IC product number 3302 manufactured by Molola, and the positive terminal of the diode 55 is grounded. One end of the resistor 56 is connected to the other end of the resistor 53, and the other end is connected to the diode 5.
It is connected to the negative electrode of No. 4. One end of the resistor 57 is connected to the negative electrode of the diode 54, and the other end is connected to one end of the resistor 58.
The other end of the resistor 58 is grounded. The resistor 57 and the resistor 58
The connection point is the non-inverting input fff! of the comparator 59. It is connected to a child. Since the output of the comparator 59 is an open collector, a resistor 60 is connected between the output and the power supply Vc. Then, the respective resistance values are determined so that the impedance on the resistor side viewed from the non-inverting input terminal of the comparator 59 and the impedance viewed from the inverting input terminal on the resistor side are the same. Also, the non-inverting input terminal of the comparator 59 is approximately 1/3
It is the voltage of VC. Therefore, when the electromagnetic pink-up 2b is connected to the input terminal 51, approximately 1/3 Vc is applied to the inverting input terminal of the comparator 59. The diode 55 is designed to prevent a negative voltage of 10.5 V or less from being applied to the inverting input terminal, and the diode 54
This is to prevent a positive voltage higher than →−(V c +0.5 V) from being applied to the inverting input terminal.

The second waveform shaping circuit 6 has the same circuit configuration as the first waveform shaping circuit 5, so its configuration will be omitted. When the waveform shown in FIG. 6(B) is output, the shaped pulse shown in FIG. 6CD) is output from the second waveform shaping circuit 6.

Reference numeral 7a denotes a timing pulse generation circuit which, based on the signals from the cylinder discrimination sensor 3 and the crank angle detection sensor 2A, sends signals to the control inputs of the analog switches 132 to 13d and signals to the control input of the peak bold circuit 8a. , is a circuit that generates a trigger signal for the A-D conversion circuit 9 to start A-D conversion. The internal circuit is shown in FIG. In FIG. 7, an input terminal 131 is connected to the output of the first waveform shaping circuit 5, an input terminal 132 is connected to the output of the second waveform shaping circuit 6, and the input terminal 1
33 is the clock C, + (
200KHz). Input terminal 132 is connected to one terminal of OR gate 135 via inverter 134. The other terminal of the OR gate 135 is connected to the "3" output terminal of the counter with divider 136.
The output of the R gate 135 is connected to the reset terminal R of the counter 136 with a divider. The clock input CL of the divide-by-die counter 136 is connected to the input terminal 131. Further, the "0" output terminal is connected to the clock input of the divider counter 137, and the "1" output terminal is connected to the reset terminal R of the divider-equipped counter 142. The counters with dividers 136, 137, and 142 all use IC and CD4017 manufactured by RCA. The “0” output terminal of the counter 137 with a divider is connected to the input of the buffer 138, and the 61″ output terminal is connected to the buffer 139.
to the input of the buffer 140, and the “2” output terminal to the input of the buffer 140,
The "3" output terminals are respectively connected to the inputs of buffers 141.Buffers 138, 139, 140, and 141 all use RCA ICCD4050.

Note that the clock enable terminals CE of the divider die 1 counters 136 and 137 are grounded. The clock input terminal CL of the counter 142 with a divider is connected to the input terminal 133, and the clock enable terminal is connected to the 9'' output terminal of the counter 142 with a divider. The “1” output terminal is connected to the input of the inverter 143.Buffer 138.13
9, 140, and 141 are connected in this order to the output terminals 145, 146, 147, and 148 of the timing pulse generation circuit 7a, respectively. “1” of counter 136 with divider
The output is connected to an output terminal 149 via a buffer 144, and the converter 143 is connected to an output terminal 150.

To explain the operation of the timing pulse generating circuit 7a with the above configuration, the pulse shown in FIG. 6(D) is input to the input terminal 132. Therefore, the counter with divider 136 has (
D) The inverted pulse enters (D) The pulse becomes “
0'', the counter with divider 136 is reset.

Then, the pulse shown in FIG. 6(C) enters the clock input of the divider-equipped counter 136. Then, at the rising edge of the third pulse, the OR gate 135 outputs “
1'' is entered, and the divide die 1 counter 136 is reset, so that the output terminal "0" has the waveform shown in FIG. 6(E).

Next, the counter 137 with a divider is similarly reset when the waveform (D) is 0'', and the waveform (E) enters the input clock, so the output terminal ``0'' becomes ``1'' in Figure 6 (S+).
The output & Ml terminal is shown in Figure 6 (S3), and the "2" output terminal is shown in (S3).
4) The "3" output terminal outputs the same waveform as (S2). Therefore, Hasofub 138.139.140.141
The outputs of are shown in Figure 6 (Sl), (S3), and (S4), respectively.
, (S2).

In addition, the waveform (F) in FIG. 6 is output to the "1' output &lW terminal of the counter 136 with a divider. Therefore, the counter 142 with a divider detects when the pulse of the (F) waveform is "1". 200K when it goes from 1 to 0
Count the Hz clock C]. However, if the pulse of the 91st plane is counted, "1" is input to the clock enable terminal, so it is held unless it is reset.

Therefore, "the 1' output terminal has a <F) waveform pulse"
6. When it goes from 1” to 0”. A 10 μs pulse is generated. The pulse is inverted by the inverter 143, and the waveform shown in FIG.
It is output to the output terminal 150 of. Further, the output of the hashoff 144 has a waveform as shown in FIG. 6(F).

138 to 13d are analog switches, which are conductive when the control input is "1" and cut off when the control input is "O".The control inputs include output signals (Sl) and (S2) from the timing pulse generation circuit 1raku 7a. , (S3), (S4)
is applied to each of the analog switches 133 to 13d.

The analog switches 132 to 13d have a common output.

In addition, when the (S+) signal in FIG.
) When the signal is '1', the analog switch 13C is conductive, and when the signal is '0', it is cut off. (S4) When the signal is '1', the analog switch 13C is conductive, and when the signal is '0', it is cut off. (S
2) Since the analog switch 13b is conductive when the signal is "1" and is cut off when the signal is "0", the output of each analog switch 13a to 13d is the T of the second cylinder in the acupressure waveform.
Shiatsu waveform of the 1st cylinder from 110° after DC to 110° TDCi of the 1st cylinder and 110° after TDC of the 1st cylinder
Shiatsu waveform of the 3rd cylinder from 110° after the TDC of the 3rd cylinder to TD of the 4th cylinder from 110° after the TDC of the 3rd cylinder
The acupressure waveform of the fourth cylinder up to 110° and the acupressure waveform of the second cylinder from 110° after TDC of the fourth cylinder to 110° after TDC of the second cylinder are output. Here, the switching point of each analog switch 13a to 13d is set at TDCf & 11o° of each cylinder because high frequency noise is generated by switching at this switching point and is output to the next bypass filter 14. However, the waveform that is actually required is the section from TDCl & 10° to 30° for each cylinder, and the switching point may be anywhere other than this section, but it was set as far apart as possible and at 110° after TDC of each cylinder.

The bypass filter 14 is a bypass active filter with a frequency of 5 KHz or higher, and is manufactured by NF Circuit Block Design Co., Ltd., product number DV4BH, and is connected to the input and output by capacitors, respectively.

Reference numeral 15 is an AC amplifier with an amplification factor of approximately 100 times, but since this is well known, the details will be omitted.

The output waveform of the AC amplifier 19 is shown in FIG. 6(1). In this FIG. 6 (1), 1. The waveform is the waveform caused by the explosion stroke of the first cylinder, and t2 is the waveform of the analog switch 13a.
t4 is the ignition noise of the third cylinder, t5 is the waveform caused by the explosion stroke of the third cylinder, L6 is the switching noise of the analog switches 13c and 13d, and t7 is the ignition noise of the fourth cylinder. It is noise, t8 is the waveform caused by the explosion stroke of the 4th cylinder, and t9 is the same J Gusui 7
13d and 13b, too is the ignition noise of the second cylinder, ill is the waveform caused by the explosion stroke of the second cylinder, and t12 is the analog switch 13b and 13.
a(7;) is the noise during switching, t2, t6, t9,
The noise at t12 also includes waveforms generated by the opening of the intake valve and exhaust valve of each cylinder.

16 is an absolute value circuit, and this circuit uses the circuit described on page 163 of the 't-NW Amplifier Handbook published by Electronics Digest in 1976, only the circuit constants are different. Explanation will be omitted. The operation is to convert a negative waveform into a positive waveform, and the waveform shown in FIG. 6 (, J) is output.

8a is a peak hold circuit, and FIG. 8 shows its internal circuit. The input terminal 210 is connected to the (F) signal of the timing pulse generation circuit 7a, and the input terminal 21
0 is indicated by the code 212 Texas Instruments mono step multi-vibration IC product number SN741
It is connected to the input IB of 23. The input IA is grounded. Between the terminal IC and I R/C of the IC212 &r near 7 capacitor 213, the terminal IR/C and the power supply Vc (=5V
), a signal with a pulse width of about 100 μs determined by the capacitor 213 and the resistor 214 is generated as shown in FIG. 6 (K) after the (F) signal of the timing pulse generation circuit 7a rises. This occurs at output Q as shown. The output Q is connected to the control terminal of analog switch 215. The input terminal 211 is connected to the absolute value circuit 1.
6 (there is 7c, the input terminal 211 is connected to diode 2
It is connected to the positive electrode of No. 16. The negative terminal of the diode 216 is connected through a resistor 217 to the non-inverting input of a buffer amplifier 220. Further, the analog switch 215's power supply is connected to the non-inverting input of the buffer amplifier 220 via a resistor 2-19, and its output is grounded. A capacitor 218 is connected between the non-inverting input of the buffer amplifier 220 and ground. The inverting input of buffer amplifier 220 is connected to the output of the sofa amplifier. The output of the buffer amplifier is connected to the output terminal 221 of the peak bold circuit 21.

To explain the operation of the peak hold circuit 8a with the above configuration, when the signal shown in FIG. ) pulse is generated. The pulse width of this (K) causes the analog switch 2 to
15 is closed to discharge the charge on capacitor 218 through resistor 219 and reset the voltage on capacitor 218 to QV. Thereafter, the output (1) of the absolute value circuit 16 is charged into a capacitor 218 through a diode 216. Therefore, the voltage of the capacitor 218 is the peak value from the time it is applied until the next time it is reset. The capacitor 2
18 is outputted to the output of the next high input impedance buffer amplifier 220. This output is shown in Figure 6 (L)
The waveform becomes Alternatively, the peak value rectifier circuit described on page 135 of "Latest Operational Amplifier Utilization Technology" published by Seibundo Shinkosha in February 1975 may be used for the circuit 8a.

9 is an A-D converter, manufactured by Micro Network Company M8.
The P1-A-D converter IC product number MN5210 is used. (G) of the timing pulse generation circuit 7a
When the output signal enters the start conversion terminal of the A/D converter 9, conversion is started, and when the conversion is completed, the pulse shown in FIG. 6(H) is generated at the EOC terminal. This conversion time is approximately 1
It is 0 μsec. Here, the signal in FIG. 6(G) is a waveform at 30° after TDC) of each cylinder, and therefore the voltage of the bold circuit 8a at the peak up to 10 μsec from this waveform is
-D conversion, so 8 bits 2 of A-D converter 9
The decimal code value approximately represents the peak value of the signal waveform from TDci of 10° to 30° for each cylinder. The EOC output of the A/D converter 9 is connected to the interrupt terminal of the frequency rate calculation circuit 10a, and the 8 pinot/binary code output is connected to the I10 terminal.

The frequency rate calculation circuit 10a will be explained. FIG. 9 shows the internal circuit of this frequency rate calculation circuit 10a.

The input terminal 230 is connected to the output EOC terminal of the A/D converter 9. Further, the input terminal 231 is connected to the output (S+) of the timing pulse generation circuit 7a, and the input terminal 232.233.234.235.236.23
7.238.239 is 8 bit 2 of the A-D converter 9
There are "ζ" connected to the decimal code output in order from the smallest number of digits.

240 is a microcomputer, Toshiba TLC
3-12 is used. The microcomputer-2
The circuit and operation of 40 are well known and will be omitted here, but it uses an internal clock frequency (2MHz), and when power is applied, it initializes and starts operating.
It starts from the address of M. One of the eight interrupt signal lines of the microcomputer 240 is connected to the input terminal 230. Also, terminal 2
41.242.243 is one of the input/output control units (hereinafter referred to as DCU) inside the microcomputer 240.
3 of the 6 device address select signal lines S
It is connected to Eo, SE+, and SE2, respectively, and connects the device and the BUS line. This terminal 241 is NA
The terminal 242 is connected to the NAND gate 246.
7, the terminals 243 are connected to one terminal of an AND gate 249, respectively.

When the terminal 244 is the same < 1 on the input/output command line of the DCU, the device is connected to the microcomputer 24.
When the bit is "0", data is transferred from the CPU to the device (hereinafter referred to as CPU). terminal 2
44 is NAND gate 1-246 and NAND gate 247
It is connected to the other terminal of the AND gate I-249 via the inverter 248.

245 has 12 lines coming out of the 12-pin BUS line. BLISII is the lowest digit and BUSO is the highest digit. 250 is a buffer circuit consisting of 6 3-state non-inverting buffer circuits, product number TC501 manufactured by Toshiba.
I am using 2P.

Input ■! is connected to the input terminal 231 of the frequency rate calculation circuit 10a, and DISA! 3LE terminals D4 and D2 are both N
It is connected to the output of AND game 1-246. Output 01
is connected to the BUS line BUSO. 251 is the same as the buffer circuit 250, and inputs ■1, I2, I
3, I4, Is, +6 is the input 0 of the frequency rate calculation circuit tOa
114 children 232.233.234.235.236.2
37 in this order. I) I SΔ
L E 5i: Both D4 and D2 are NAND gate 2
It is connected to the output of 47. Also, output 01.02.0
3.04.05.06 is the Bus line BUSII,
BUSlo, BUS9, BUS8, BUS7, +3US
6 in this order.

252 uses the same TC5012P as the buffer 250. Inputs 1 and I2 are respectively connected in this order to input terminals 238 and 239 of the frequency rate calculation circuit 10a.

The remaining inputs (3), I4, +5, and +6 are commonly grounded. DISABLE terminals D4 and D2 are commonly connected to the output side of the NAND gate 247. Also, the outputs 01% 02, o3, o4.05, o6 are the BUS lines BUS5, BUS4, BLIS3, B
Connect to US2, BUSI, and BUSO in this order. 253 is a memory device made by RCA company IC1 product number C
D4035 is used, and the clock input CL is the above A.
At the output of the ND gate 249, each human power D + = D 2
, D3, and D4 correspond to the BUS lines 0, 2, 2, and 2, respectively.
3, and the reset terminal is grounded. The output of the memory 253 is output terminal 254.255.256.257 of the frequency rate calculation circuit 10a.

With the above arrangement, the operation of the frequency rate calculation circuit 10a will be explained with reference to the flowchart of FIG. When a key switch (not shown) is turned on, the power is turned on and operation starts. Then, in step 1, the ROM of the microcomputer-240
Clear all memory except and step 2
Now clear UO of RAM memory area U,
In step 3, clear Ul and set the number of data for the first cylinder to 0. In step 4, clear U2 and set the number of cylinders i to 0. In step 5, clear U3 and set the number of data for cylinders other than the first j. Set to 0.

In step 6, the mask is set and the step command is executed to input an interrupt signal.

Then, when the engine starts and rotates, the A-D
The converter 9 starts the conversion, and when this conversion is finished, the sixth
Frequency rate calculation circuit 1 that generates the EOC pulse in Figure (I])
An interrupt is applied to the microcomputer 240 from the input αj111 child 230 of 0a to start calculation. That is step 7.

If there is no EOC pulse, it waits until it arrives, and if a +7.0C pulse comes, it jumps to step 8. In step 8, after the input/output command signal to the dehysteresis control unit (DCU) in the microcomputer 240 becomes 1, the dehysser I/reselect signal SEo is outputted to the terminal 241.

When both the input/output command signal and the device address select signal are "1", the NAND gate 246 becomes "O", and the input/output of the buffer 250 is combined and the data output to the BUS line is sent to the register of the processor in the microcomputer 240. Load into. Then, in step 9, it is determined whether only the highest digit of the 12-bit data stored in the register of the processor is "l" or "0", and the first
It is determined whether or not the data is for the cylinder (#1). If yes, the process proceeds to step 10; if no, the process proceeds to step 11.

In step 10, UO in the memory X area is set to 1, and the process proceeds to step 11. Step 11: Memory U
Determine whether the content of o is 1 or not, and if yes, step 1
Proceed to step 2, and if no, return to step 7. Once the memory UO is filled with 1, the process will proceed to step 12 unconditionally until it is filled with 1.

The above steps 8, 9, 10 and 11 are steps for storing data in memory in order starting from the data for the first cylinder.

Step 12 is a process that includes steps 8 and 9, but it is determined whether the data that has just entered is data for the first cylinder or not in the same process as steps 8 and 9.
If , proceed to step 13, and if no, proceed to step 14.

Step 13 adds 1 to the contents of memory U and stores the result in memory Ll+. Then, clear the memory of U2 and set i to 0. Therefore, initially 0+1 and h=1
is stored. Similarly, step 14 adds 1 to the content i of the memory U2 and stores it in the memory U2 again. Therefore, since the initial value is i-0, i=1 is stored at O+1. In step 15, the content i of memory U2 is
OM is multiplied by the programmed number of data NR (=100) to be collected per cylinder and stored in the memory U3.

Step 16 adds the contents of memory U1 and the contents j of memory U3 and stores the added value I in memory U4.Then, in step 17, the contents of memory U4 are added to address XkO in area X of memory specified by the contents of memory U4. Frequency rate calculation circuit 10a
data coming in from inputs 232-239 of. In step 18, the content k (total data number) of memory U4 is 4.
Determine whether or not X N R has been exceeded, and if no, step
Return to step 7, and if yes, proceed to step 19.

That is, if the set number of times NR is now 100 in the process from step 7 to step 18, the data for the first cylinder among the A-P converted data is stored in memories x1 to X+oo, and the data for the third cylinder is stored in memories x1 to x+oo. The data is Xl0I
Data for the 4th cylinder is stored in the memory of X300 from X20+, and data for the 4th cylinder is stored in the memory of X300 from
Data for the cylinders are stored in the memories X301 to X400 in order.

Step 19 resets the mask and disables interrupts every time a step command is executed. Step 2
If 0, clear the memory U5 and specify the cylinder number. Set the content to O ('O is the 1st cylinder, 1 is the 3rd cylinder, 2 is the 4th cylinder, 3 is the 2nd cylinder), and step 21 is the memory US. The content capacity is multiplied by the setting circuit NR programmed into the ROM and stored in the memory U6. Step 22: Memory U
The contents n (addresses from 1 to Np) of 7 are set to 1. Step 23 clears YO in the memory Y area and sets the content S to O. Step 24 adds the content n of the memory U7 to the content l of the memory U6 and stores the result in the memory U8. Therefore, initially m-0 and n=1, so P=
]. Step 25 adds the content lap of Xp of the memory X designated by the content P of the memory U8 to the content S of the memory YO in the memory Y area and stores the result in the memory YO. Then, step 26 is the content n of memory U7.
1 is added to and stored in memory U7.

In step 27, it is determined whether the content n of the memory U7 is larger than the setting circuit NR. If yes, the process moves to step 28; if no, the process returns to step 24.

Therefore, according to the process from step 22 to step 27, if m=0 and NR=100, the content S of the memory Yo contains data for the first cylinder D1+D2+...
...+DI 00 is included.

Step 28 transfers the contents S of the memory Yo to the setting circuit NR.
and stores the divided value D″m in memory Y1.D
m represents the average value of the cylinders determined by the value of m. Step 29 sets the contents of memory U9 to 1.

Step 3o clears the memory UIO and sets the content r to 0. Step 31 divides the data Dq of the memory Xq indicated by the content q of the memory U9 by the content τm of the memory Y1, and stores the division value Eq (ratio when the average value is 1) in the memory Y2.

In step 32, it is determined whether the content Eq of the memory Y2 is smaller than a set value ER (certain magnification) programmed in advance in the ROM. If yes, the process proceeds to step 34; if no, the process proceeds to step 33. Step 33 adds 1 to the content r of the memory LJIO and stores it in the memory UIO. Therefore, initially r=Q. Ste, Pu 3
4 adds 1 to the content q of the memory U9 and stores it in the memory U9. Therefore, at first q=1, then 2, and then 3. Step 35 is memory U9
It is determined whether the content q is larger than the setting circuit NR, and if YES, the process proceeds to step 36, and if no, the process returns to step 31.

Therefore, through the process from step 29 to step 35, the data D1, D2...Dnlq stored in the memories X lXX2...XnR are reduced to an average value τm
Divide each by and obtain the divided values El, R2...EN
The number of R that is equal to or greater than the set value ER is the content r of memory U+O
becomes.

Step 36 transfers the contents r of the memory UIO to the processor 8
The set number of times NR is read out from the ROM and divided.

The division value F (frequency) remains in registers R2 and R3. Step 37 ROMs 100 to the contents of registers R2 and R3.
Read out and multiply. The multiplied value H represents the frequency rate and remains in registers R2 and R3. The upper digit is R2 and the lower digit is R3.
It is.

In step 38, it is determined whether the contents of the registers R2 and R3 are greater than or equal to a set value (certain relationship rate) HR. If yes, proceed to step 39; if no, proceed to step 40. Step 3! J reads the content of the memory U5 and sets the mth digit of the memory Ull to 1". Step 4o sets the mth digit of the memory Ull to °'0". Since the first m is O, the highest digit of the memory U11 will be cented. Step 41 adds 1 to the contents of memory U5 and stores the result in memory U5.

The step knob 42 determines whether the content capacity of the memory US is 4 or more, and if no, the process returns to step 21, and if yes, the process proceeds to step 43.

As described above, the set number of times NR is set to 100 through the process of step 42 from step 2o, and the data DI for the first cylinder is set to 100.
, D2... Take Dloo, calculate the ratio, and calculate the number of data occupied by the set value ER or more of the nuclearization (if it exceeds R%, the number of data occupied by ER is set to 0). Set the digit to 1, and set it to 0 if Hρ is not drawn.Similarly, next is the data for the third cylinder DI01.DIO'2...D
200, calculate this average value D1, divide each data by the average value D1, calculate the ratio, and if the number of data occupied by ER or more after nucleation becomes HR% or more, the first digit of memory Ull is calculated. Set it to 1, and set it to 0 if it is less than H8. Similarly, data for the fourth cylinder D201, D202...D3
oo, calculate this average value D2, divide each data by the average value D2, calculate the ratio, and if the number of data occupied by ER or more of nuclearization becomes HR% or more, the second Set the digit to 1, and set it to 0 if it is less than H8. Similarly, data for the second cylinder D 301, D302, ..., I) 4o
o, calculate this average value D3, divide each data by the average value D3 and take the ratio.
Set the digit number 1 to 1, and set it to 0 if it is less than H8.

Step 43 outputs the contents of memory U11 to the I10 pass line. In this case, the input/output command signal comes out from the terminal 244 and becomes "O", and at the same time, the device address select signal SE2 comes out from the terminal 243 and becomes "1".
”. At the same time, the contents of the memory Ul+ are output to the I10 hash line. When the input/output command signal and the device address select signal satisfy the above conditions, the inverter 248 and the AND gate 249 output a signal from 0 to 1. With this signal, the memory 253 records the necessary upper four digits of the data output to the I10 high line 1a.

The microcomputer 240 then returns to the second step in the flowchart of FIG.

In addition, in the flowchart of FIG. 10, when making a determination such as step 7, there may be an additional step,
There may be detailed steps when returning to the previous step, but since these are generally known, their explanation will be omitted.

As a result of the above, the output of the memory 253, that is, the output terminal 254 of the frequency rate calculation circuit 10a outputs the calculation processing result for the first cylinder, and the output terminal 255 outputs the calculation result for the third cylinder.
6 outputs the arithmetic processing result for the fourth cylinder, and output terminal 257 outputs the arithmetic processing result for the second cylinder.

Then, during non-king, the ignition timing is controlled by the non-king signal for each cylinder obtained from the output terminals 254 to 257 from this frequency rate calculation circuit 10a (the ignition timing is delayed during non-king), thereby minimizing the occurrence of non-king. can be kept to a low value. As a method of controlling the ignition timing, the ignition timing can be delayed by using a delay circuit, for example, when knocking occurs.In addition, in the case of electronic ignition timing control devices that are being adopted in recent years, electronic ignition timing can be delayed when knocking occurs. Just configure the circuit.

12 is a display circuit whose circuit configuration is shown in FIG. 1st
In Figure 1, 260 is the display circuit for the first cylinder, and resistor 2
One end of 61 is the output terminal 25 of the frequency rate calculation circuit 10a.
4, and the other end is connected to the base of transistor 263. The emitter of transistor 263 is grounded. A resistor 262 is inserted between the base and emitter of the transistor 263, and its collector is connected to the negative electrode of the light emitting diode 264. The light emitting diode 26
The positive terminal of No. 4 is connected to the power supply voltage VC across the resistor 265.

To explain the operation of the display circuit 12 with the above configuration, the terminal 25
When a voltage is applied to the transistor 4, a base current flows to the transistor 263 through the resistor 261, and the transistor 263 becomes conductive. Therefore, the light emitting diode 264 lights up.

When no voltage is applied to terminal 254, transistor 263
is cut off and the light emitting diode 264 is turned off. Similarly, 270 is a display circuit for the third cylinder, and 280 is a display circuit for the fourth cylinder.
290 is a display circuit for the cylinder, and 290 is a display circuit for the second cylinder, each of which operates in the same way as the display circuit 260.

Note that the clock circuit 11 is composed of an oscillation circuit using a crystal resonator and a counter that divides the oscillation frequency.

As described above, by checking whether the light emitting diodes of the display circuit 12 are turned on or off, it is possible to determine whether or not the engine is knocking for each cylinder.

In addition, in the above-mentioned embodiment, 10° to 3° after top dead center
Peak hold circuit 8a, ! for the purpose of taking the peak value of the waveform in the 0° section! =A-D converter 9 was used, but in order to calculate the value of integrating the waveform in the interval from top dead center 10° to 30°, an integrating circuit 8a as shown in FIG. 12 was used instead of the peak bold circuit 8a. ′ can also be used to detect knocking. In FIG. 12, 211' is a diode that passes the positive waveform among the waveforms. and a resistor 212', an amplifier 2
13', capacitor 214', analog switch 215
', and resistor 216' constitute an integrator. 212.
Reference numerals 113 and 214 denote an IC, a capacitor, and a resistor that constitute a monostepple multi-by-break similar to the one shown in FIG. The output shown in figure (K) is generated. Analog switch 215' is closed by the pulse of FIG. 6(K) applied to the control input, discharging the charge on capacitor 214' and starting integration. In this case, the input of the integrator is a positive voltage, so
The output is a negative voltage.

Therefore, it is inverted by the inverting amplifier 217' with a gain of 1 and outputs a positive voltage. The start of this integration is approximately TDC (10°), and since the integration is performed at 30° after TDC at a speed of about 10 μsec, the converted value is converted at 10° to 30° after TDC. This is the integral value of the waveform in the interval of °.If non-king occurs, the integral value increases accordingly, so this value is processed in the same manner as above by the frequency rate calculation circuit 10a and the result is displayed in the display circuit 12. When displayed, almost the same effect as in the above case was obtained.

In addition, in the above embodiment, the sampling period is TDC
The section was set from 10° to 30° after TDC, but this was changed to 10° before TDC.
There was no significant difference even when the angle was changed from 30° to 30° after TDC.

〔Effect of the invention〕

As described above, in the present invention, the knocking determination result for each cylinder is stored in memory for each cylinder in accordance with a predetermined timing signal, and is reflected in the control of the ignition timing of the corresponding cylinder. Therefore, even if there is a difference in the occurrence of knocking between the cylinders, non-knocking in each cylinder can be appropriately prevented, and output and fuel efficiency can be improved.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram for clearly showing the configuration of the present invention, FIG. 2 is a block diagram showing an embodiment of the device of the present invention, and FIG. 3 is a front view showing a crank angle detection sensor in the device shown in FIG. 4 is a front view of the device shown in FIG. 2 without showing the cylinder discrimination sensor, FIG. 5 is an electric circuit diagram showing the first waveform shaping circuit in the device shown in FIG. FIGS. 7 to 9 are waveform diagrams of various parts used to explain the operation of the device shown in FIG. 10 is a flowchart of the microcomputer in the circuit shown in FIG. 9, FIG. 11 is an electric field circuit diagram showing an example of the display circuit in the device shown in FIG. 2, and FIG. 12 is a diagram of the peak bold circuit in the device shown in FIG. FIG. 3 is an electrical circuit diagram showing an example of an integrating circuit used instead. ■a-1d...Shiatsu detector as a non-king detector, 7a...Timing pulse generation circuit, 3a...Peak bold circuit, 8a'...Integrator circuit, 9...A
-D converter, 10a... Frequency rate calculation circuit, 13a-1
3d...Analog switch, 240...Microcomputer-0 Representative patent attorney Takashi Okabe 5

Claims (1)

[Scope of Claims] A non-king detector that detects knocking vibrations in each cylinder of a multi-cylinder internal combustion engine and generates a non-king output according to the vibrations, and an average ground that averages the knocking outputs from this knocking detector. knocking determination means for determining the presence or absence of non-king by determining a magnitude relationship with the non-king output; and a recording means for storing and holding the knocking determination result corresponding to each cylinder for each cylinder in accordance with a predetermined timing signal. and a timing signal generating means for generating the predetermined timing signal in response to a signal detected at a predetermined rotational angle position of the engine, the storage means having the information as described in 1. 1. A non-king control device for an internal combustion engine, characterized in that the ignition timing of the engine is controlled for each cylinder in accordance with the non-king determination result of each cylinder in which the ignition timing is maintained.