JPS6045386B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and more particularly to an improved electronic timepiece circuit that issues a count adjustment signal necessary for adjusting the time, for example, in an electronic timepiece.

In general, an electronic watch with a liquid crystal display passes the output of a crystal oscillator, for example, a frequency of 128H2, through a first frequency dividing circuit to obtain 1H2 as a 1-second signal, and this 1-second signal is counted by an impression counter to give 1 second signal. At the same time, digital display is performed by constantly driving the liquid crystal display element using 32H2, which is obtained by dividing the frequency of 128H2 by 114, to AC drive the liquid crystal display element.

To adjust the time of such an electronic clock, for example, two switch elements are used, and the first switch resets the first frequency dividing circuit and the advance counter, and generates a count adjustment signal for time adjustment. The output of a second frequency dividing circuit provided separately is gated by a second switch to obtain, for example, a 1H2 count adjustment signal.

The liquid crystal display element is driven by this 1H2 signal, and the second switch is turned on until the hour and/or minute of a predetermined time is reached. When the liquid crystal displays this predetermined time, the second switch Turn off the switch, close the gate, and turn off the 1H2 count adjustment signal. In this state, at the same time as the regular time signal (the predetermined actual time at which the time should be set), the first frequency dividing circuit and advance counter are reset and canceled again using the first switch to perform regular counting. The time setting is completed from the beginning. To explain the counting circuit of the above-mentioned electronic clock using FIG. 1, the 128H2 output signal of the crystal oscillator is converted into a
2H2) input to the 1/2 frequency divider circuit 2 which obtains the signal /.

The output of this 114 frequency divider circuit 2 is also input to the first frequency divider circuit 4 for obtaining the 1 second signal 3.
is input to the frequency dividing circuit 5 to obtain 1H2. The 1-second signal from the first frequency dividing circuit 4 is input to the print counter 6, which outputs the 1-minute signal 7 to operate the liquid crystal. 5 The five 112 frequency divider circuits constituting the first frequency divider circuit 4 and the advance counter 6 are each reset by a signal 8 from the first switch.

A second frequency divider circuit 5 is connected to one input of the two-input gate circuit 9.
A 1 Hz output signal from the second switch is connected to the other input, and a signal 10 from the second switch is connected to the other input via an inverter 11.

The output 12 of this 2-input gate circuit 9 has a 1 for counting adjustment.
A Hz signal is gated out. With this circuit configuration, it is only necessary to perform the first and second switch operations as described above to complete the time adjustment, and the counting error in this case is at most 3.
The frequency is 1.25rrLS (1132Hz), which is sufficiently practical.

However, since such a conventional circuit configuration requires two sets of frequency dividing circuits, the number of circuit components increases when the circuit is integrated, which is not a good idea. In the current situation where it is desired to reduce the number of circuit components, the circuit shown in FIG. 1 is not suitable for integration. An object of the present invention is to provide an electronic timepiece suitable for integration by reducing the number of circuit components.

The electronic timepiece of the present invention includes a frequency dividing circuit configured with a plurality of frequency division stages that obtains a timekeeping signal from a predetermined oscillation frequency, a display section that displays time using the timekeeping signal, and a switch.
The present invention is characterized in that it includes a gate circuit that outputs a signal obtained from a predetermined frequency division stage by operating this switch, and means for changing the time display via the display section using the signal obtained from this gate circuit. . According to the electronic timepiece of the present invention, there is no need to separately provide a second frequency dividing circuit for generating a count adjustment signal, which is required in conventional electronic watches, and only one frequency dividing circuit can be used. Since the circuit can be used both for time counting and counting adjustment, the number of circuit elements is reduced accordingly, making the circuit suitable for integrated circuits.

Note that the error after time adjustment is the same as that of the conventional method. Therefore, the electronic timepiece of the present invention maintains the characteristics of the conventional electronic timepiece in terms of characteristics, and can greatly reduce the number of j elements. In order to better understand the present invention, the present invention will be explained in detail below using FIGS. 2 and 3.

FIG. 2 is a circuit block diagram showing one embodiment of the present invention, and FIG. 3 shows timing waveforms of various parts in the circuit block of FIG. 2. In the figure, 128H of the crystal oscillator
The output signal of z is input to a 114 frequency divider circuit 22 which obtains a 32Hz1 signal 21 for constantly AC driving the liquid crystal display element.

This 114 frequency divider circuit 22 includes 1 to 2 frequency dividers 23 and 24.
It is composed of This 32 Hz signal 21 is also input to the frequency dividing circuit 25 and frequency-divided to 1 Hz to become a 1 second signal 26 for counting, and this 1 second signal 26 is further converted into a 1 minute signal 28 by a (1) base counter 27. These 1 second signal 26 and 1 minute signal 28 are sent to the liquid crystal display element together with the 32 Hz liquid crystal drive signal 21 to digitally display the time. The frequency dividing circuit 25 is composed of five 112 frequency dividers 29 to 33, and divides the input signal of 32 Hz into a 1 Hz signal. The first switch 34 for time adjustment is normally connected to the negative side of the power supply 35, and this negative potential (low level) is inverted by the inverter 36 and applied to the D-type flip-flop (D-FF) 37. Clock 7 input.

The output of the D-FF 37 is the output of the two-person AND gate 38, and the output of the AND gate 38 is the output of the frequency dividing circuit 25.
It serves as a reset input for the 112 frequency dividers 29 to 33 that constitute the . Also, the output of D-FF37 remains unchanged) Impression counter 27
It serves as the reset input for the The second switch 39 for time adjustment is normally connected to the negative side of the power supply 40, and this low level becomes the other input of the AND gate 38 via the inverter 41, and at the same time, the 2-input 0R gate 4
2 has become a single-handed force.

On the other hand, the 1 Hz signal 26 becomes the other input of the 0R gate 42, and the output of the gate 42 becomes the count adjustment signal output terminal 43. Note that the switch 34 normally outputs a low level as described above, but when the switch is turned on,
It is assumed that the D-FF 37 is instantaneously connected to the positive side of the power supply 35 and generates a high-level single pulse, which will be described later, regardless of its input time), and the output state of the D-FF 37 is reversed every time it receives this single pulse. It shall be.

That is, the state of the output of the D-FF 37 is reversed each time the switch 34 is turned on.Also, the switch 39 normally outputs a low level as described above, but when the switch is turned on, the power supply 40 is turned on during the turn-on period. It shall be connected to the positive side to maintain its output at a high level, and when the input is released, it will return to the initial state and output a low level.
It is assumed that the 2 frequency dividers 29 to 33 and the sexagesimal counter 27 are reset by inputting a high level reset pulse.

A time adjustment method using the circuit configuration will be explained with reference to FIG.

In the steady state, the 128Hz output signal of the crystal oscillator is divided into a 32Hz signal 21 by the 114 frequency divider circuit 22,
This signal is a constant alternating current drive signal for the liquid crystal display element.

At this time, the output 34'' of the switch 34 is at a low level, so the output of the inverter 36 is maintained at a high level. Also, the output 39'' of the switch 39 is also at a low level, so the output of the inverter 41 is maintained at a high level. Therefore, the output of the AND gate 38 is at a low level, and therefore the frequency dividing circuit 25 and the advance counter 27 are in an operating state. Therefore, one second and one minute signals are obtained at the terminals 26 and 28, respectively, and together with the liquid crystal drive signal 21, the liquid crystal is operated to display the regular time. Next, when adjusting the time, first turn on the switch 34 at the time, then a single pulse 34'' is obtained at the output, and this pulse 34'' causes the D-FF
The output 37'' of 37 is inverted and becomes high level.

Therefore, the (4) base counter 27 is reset. At this time, the other inputs of the AND gate 38 are at a high level, so the gate 38 is opened and its output becomes a high level, so that the frequency dividing circuit 25 is also reset. In this state, the 1 second and 1 minute signals for driving the liquid crystal are not output, so the liquid crystal display element continues to display the time when the switch 34 is turned on. Next, the switch 39 is turned on for a desired period Tx from time T2. During this period Tx, switch 3
9's output 39'' will be at a high level, therefore inverter 4
The output of 1 is low level. Therefore, the gate 38 is closed, its output becomes low level, the frequency divider circuit 2-5 is released from reset, and a 1 second signal is input to one input of the 0R gate 42. At this time, the other input of the 0R gate 42 is switch 3.
9. Since the level is low due to the inverter 41, the gate 4
2, a 1 second signal for counting adjustment is outputted to its output terminal 43. Therefore, during the period Tx, (1) the base counter 27
remains reset), so its output 28 does not output a one-minute signal. However, the count adjustment signal 43 determines when and/or when the liquid crystal should be driven to set a predetermined time.
or set to minutes. This time adjustment period is the Tx above.
It is. By releasing the switch 39 when the liquid crystal displays the predetermined time, the 0R gate 42 is closed, and at the same time, the AND gate 38 is opened and the frequency dividing circuit 25 is reset again. In this state, the time T when the above predetermined time held and displayed on the liquid crystal coincides with the regular time signal.
When the switch 34 is turned on again at 3, a single pulse 34''
is outputted by the switch 34, thus inverting the state of the D-FF 37, that is, setting it to a low level, and closing the gate 38.

As a result, both the frequency dividing circuit 25 and the sexagesimal counter 27 are reset, and the normal time is counted and the normal time is displayed digitally. As is clear from FIG. 3, even with the method of the present invention, the error of the clock after time adjustment is within 31.25 mS, and accuracy equivalent to that of the conventional method can be obtained.

In the above embodiment, 1 is used as the time count adjustment signal.
Although Hz is used, it is of course possible to use this as a 2Hz signal. In this case, the signal is taken out from the connection point of the 112 frequency dividers 32 and 33 of the frequency dividing circuit 25 and sent to one of the 0R gates 42. It can be done manually. It is also conceivable to shorten the adjustment period Tx by using the same counting adjustment signal of 2 Hz or more, that is, 4 Hz, but this is not practical because the display speed of the liquid crystal display element becomes faster. Further, although the liquid crystal constant driving signal is set to 32 Hz, it is of course possible to set it to 64 Hz, and in this case, the 112 frequency divider 24 can also be reset.

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[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional circuit block, FIG. 2 is a circuit block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing timing waveforms of each part of the block in FIG. 2. In the figure, 25... frequency dividing circuit, 26... 1
Second signal, 27...6 Pheasant counter, 28...
1 minute signal, 34... 1st switch, 37...
...D type flip-flop, 38...AN
D gate, 39...Second switch, 42...
0R gate, 43... is a count adjustment signal output terminal.

Claims (1)

[Claims] 1. An electronic timepiece comprising a clock circuit having a second signal generation circuit and a minute signal generation circuit in its upstream stage, and a display unit coupled to the clock circuit, comprising: a reset means for resetting the minute signal generation circuit; and a minute signal generation circuit. means for extracting a time adjustment signal from a second signal generating circuit to change the display while the second signal generating circuit is reset; and means for resetting the second signal generating circuit after the change, and changing the reset state of the signal generating circuit after changing the display contents. An electronic timepiece characterized in that the reset state of the second signal generation circuit is released at the same time as the reset state of the second signal generation circuit is released.