JPS604339A - Stereo demodulating circuit - Google Patents

Abstract

PURPOSE:To eliminate a beat noise with a simple constitution by using a specially generated signal to cancel beat signals having phases opposite to each other which are included in the output signal of a subsignal decoder. CONSTITUTION:In the first output terminal of a subsignal decoder 7, a beat B between beat 114KHz included in a composite signal and higher harmonic 114KHz in a square wave signal of 38KHz is generated together with a demodulated stereo subsignal. A beat-B having a phase opposite to that of the beat B obtained in the first output terminal is generated in the third output terminal of the decoder 7. Consequently, the switch of a compensating circuit 21 is turned on to eliminate the heat surely with resistances 19 and 20 whose values are determined in accordance with a beat frequency whose elimination is required. In this case, control in ''on'' and ''off'' of the switch 23 of the compensating circuit 21 is executed by using a control signal which is generated by processing a signal equal to the 38KHz square wave switching signal used in the decoder.

Description

Detailed description of the invention (a) Industrial application field In an FM stereo receiver, when there is a radio wave from an adjacent station close to the frequency of the receiving station, a beat occurs between the signals of both stations, and the Beats having a frequency that falls within the IF (intermediate frequency) band of the station pass through each stage of the FM receiver, are detected by the FM detection stage, and then applied to the stereo demodulation stage. Therefore, in the stereo demodulation stage, 38KH2
When demodulating is performed using the square wave switching signal of 38K llz, a beat is generated between the beat and the high frequency (especially 114I (H7 signal)) of the 38K llz square wave switching signal, and a harsh beat noise is generated. It had the following drawback.

As a method for preventing the generation of beat noise, an LC resonant circuit whose resonant frequency is the frequency of the beat contained in the detected output signal is connected to the input end of the stereo restoration circuit, and the beat noise contained in the detected output signal is There is something to remove.

However, such a method has the disadvantage that the phase of the stereo sub-signal is shifted by the LC resonant circuit, resulting in extremely poor separation, and is unsuitable for integration into an IC (integrated circuit), and requires adjustment. This method was not very desirable because it had the following drawbacks.

In addition, as shown in Fig. 1, when demodulating the left and right stereo signals in the stereo demodulation circuit (1), in order to prevent beat noise, a switching signal carrier of 38Kt (Z square wave switching signal with harmonics removed in advance) is used. A method has also been proposed in which the switching signal is generated and demodulated by applying the switching signal from the switching signal generation circuit (2) to the stereo demodulation circuit (1). Since the signal has been removed in advance, there is no chance of beats occurring, and beat noise can be sufficiently removed.

However, this method requires a complicated circuit in order to create a switching signal (a) from which high frequencies are removed, and also requires a special stereo demodulation circuit of three-way operation type as a stereo demodulation circuit. Not very common.

Furthermore, as shown in FIG. 2, in the stereo demodulation circuit (1), the left and right stereo signals are demodulated using a switching signal generation circuit (3) that generates an ordinary 38I (Hz square wave switching signal), and an auxiliary demodulation circuit is also used. (4), and in the auxiliary demodulation circuit (4), the 38I(H
A switching signal generation circuit (5
) has been proposed to perform beat demodulation using the demodulation circuits (1) and (4), and add the output signals of both demodulation circuits (1) and (4) to remove the beats. However, this method also requires a special auxiliary demodulation circuit (4) and has the disadvantage of complicating the circuit.

(c) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and aims to remove beat noise using a stereo demodulation circuit that can be easily converted into C and has a simple configuration.

B) Structure of the Invention The stereo demodulation circuit according to the present invention includes: a demodulation section that separates and generates left and right stereo signals from a detected stereo composite signal; a means for generating a 38I (Hz) rectangular wave switching signal; means for generating a rectangular wave signal having a frequency that is an odd multiple of the rectangular wave switching signal; means for generating another rectangular wave signal from the rectangular wave switching signal and the rectangular wave signal; and means for partially reducing the degree of separation between left and right stereo signals.

匝) Embodiment FIG. 3 is a circuit block diagram showing an embodiment of the present invention.
(6) is the I''M detection circuit, and (7) is the FM detection circuit (6).
) in the output composite signal (T,
-'R), and (8) is the stereo sum signal (L-I-R) in the composite signal.
(2) is a phase comparator θ0),
A low-pass filter (11), a VCO (voltage controlled oscillator) 02 that oscillates at an oscillation frequency of 228 KHz, a frequency divider 03), and a second divider that divides the output signal of the first frequency divider (131 to 1). A PLL circuit (15) is composed of a frequency divider (+41) and generates a signal in phase with the stereo pilot signal (P) in the composite signal. The sub-signal decoder (stereo sub-signal (L-R) demodulated by power) and the sum signal circuit (
0'71 is a first addition circuit that adds the stereo sum signal (L+R) obtained from 8) to generate a stereo left signal (L) at the first output terminal (+6); R-L) and stereo sum signal (L+11)
A second adder circuit that adds the stereo right signal (group) to the second output terminal 0 barrel, <1'J is the sub-signal decoder (the 1V' power end of the power and the first adder circuit 05). A first output resistor (20) inserted between the second output terminal of the sub-signal decoder (7) and the second adder circuit (17)
) is inserted between the level adjustment resistor (22) and the switch (23+) inserted between the input terminals of the first and second adder circuits (+5) and (+7). The compensation circuit C.0 consists of the output of the VCO (]2
The third frequency divider divides the frequency into 114I (Hz) and generates a square wave signal.
a frequency divider, and (2ω is the first and third frequency divider (13)
Using the output signal of (24), the compensation circuit (b)
This is a control signal generation circuit that generates a control signal for controlling the switch (23).

Next, the operation will be explained. 19I (Hz stereo pilot signal in the composite signal obtained at the output end of the FM detection circuit (6) is a 19KHz square wave signal obtained at the output end of the second frequency divider θX) and a signal corresponding to the phase difference is sent to the phase comparator (10
) at the output end of the barrel. Then, the signal corresponding to the phase difference is passed through the low-pass filter 01) to the VCO (+21
, the VCOQ2 is controlled and its output oscillation frequency (228KHz) is synchronized with the -19KHz stereo pilot signal in the composite signal. The output signal of the VCOH is passed through a first frequency divider (I3
) to become a 38KHz square wave signal, which is applied to the sub-signal decoder (power) to demodulate the stereo sub-signal. is the demodulated stereo sub signal (
L-R) as well as the beat (B) between the beat (+14 Kl (near z)) included in the composite signal and the harmonic (114 Kl (z)) in the 38 KHz square wave signal.
occurs. Further, the second sub-signal decoder (7)
At the output terminal, a stereo sub-signal (R-L) having a phase opposite to that of the stereo sub-signal (L-R) and a beat (-B) having a phase opposite to the beat obtained at the first output terminal are generated.

The present invention provides beats (B) and (-B) of mutually opposite phase contained in the output signal of the above-mentioned sub signal decoder (7),
It is characterized by using a specially created signal for cancellation.

114 Kl (to cancel the beat near z,
The first and second output resistors 00 and (20+) and the compensation circuit (
goods) will be placed. The switch of the compensation circuit (b) (
23) is blocked, the sub signal decoder (7
The output signals of ) are transmitted through the first and second output resistors (1 and (2α), respectively, to the first and second adder circuits (15) and (
171, and is added to the sum signal (L+R) from the sum signal circuit (8), similar to the through-submerged stereo demodulation circuit, and the stereo left signal (L+ is applied to the second output terminal (16)). A stereo right signal (respectively) can be obtained from the output terminal (1→). When the switch (23) of the compensation circuit is made conductive,
The output signal obtained at the first output terminal of the sub-signal decoder (7) is applied to the second adder circuit a7) via the first output resistor (1!l) and the level adjustment resistor (22), and the second
Output resistance (A) and level adjustment resistance (via 2)
The output signal obtained at the second output terminal of the coder (7) is applied to the first adder circuit 05). The level of the cancellation signal applied from one output end of the sub-signal decoder (force) to the other output end is determined by the values of the first and second output resistors α9 and (20) and the level adjustment resistor (two). Generally, the level of the third harmonic is 1 of the fundamental wave, and the level of the 5th harmonic is 1 of the fundamental wave.In other words, the level of the 3rd harmonic is 1 of the fundamental wave. Since the harmonic level is equal to 1 of the fundamental wave, reliable beat removal can be achieved by determining the values of each of the resistors and setting their ratio according to the frequency of the beat that needs to be removed. Third
In the embodiment shown in the figure, the side pressure for removing the beat of 114 KH2 is explained, so in that case, the value of each resistor may be set in four ways such that the level of the cancel signal becomes 1.

The control of shutoff and conduction of the switch (23) of the compensation circuit is performed using a control signal created by processing a signal equivalent to the 38 KHz square wave switching signal used in the sub-signal decoder. FIG. 4 shows an example of the control signal generation circuit (c) in FIG.
The input terminal (27) is the second input terminal to which the 4KH2 negative-phase signal is applied, the third input terminal to which the 2-channel 138KIIZ positive-phase signal is applied, (29) is the 38Ktlz negative-phase signal to which it is applied. The fourth input terminal (30) is the 114KH
The first multiplier circuit C31) that multiplies the Z positive phase signal and the 38 KIIZ positive phase signal multiplies the 114 KHz positive phase signal and the 38 KIIZ positive phase signal.
The second multiplier circuit multiplies the Hz reverse phase signal, and the θ force is the same as the above 1.
a third multiplier circuit that multiplies the 14KHz negative phase signal and the 38K1z negative phase signal; (331 is the 114K11z negative phase signal;
A fourth step that multiplies the negative phase signal and the 38Kl (Z positive phase signal)
A multiplication circuit, Ga is a first output terminal from which an addition output of the output signal of the first and third multiplication circuits C1) and 0 power is obtained, and C35+ is the second and fourth multiplication circuits C31) and C3.
This is the second output terminal from which the summed output of the output signals of 3) is obtained.

Next, the operation shown in FIG. 4 will be explained with reference to FIG. On the first multiplier circuit side, the 8g5 114KH2 positive phase signal in Figure (A) applied to the first input terminal (26) and the 38Kll signal in Figure 5 (C) applied to the third input terminal (28)
z positive phase signal is multiplied, and an output signal shown in FIG. 5(e)K is generated. In addition, in the third multiplier circuit (in the case of three multiplication circuits, 114 in FIG. 5 (b) applied to the second input terminal (5)
The KHz negative phase signal is multiplied by the 38 Kt (z negative phase signal in FIG. 5) applied to the fourth input terminal t29), and the fifth
The output signal shown in figure (f) is generated. And the first
By adding the output signals of the and third multiplier circuits 00) and (13z), the first output terminal (34) receives data that becomes 1.1-high level 0 period or S as shown in FIG. -76K with tee
[A square wave signal of Jz is obtained. On the other hand, the second multiplication circuit 4
31), the 114 KHz positive phase signal of FIG. 5 (A) applied to the first input terminal (26) is multiplied by the 38 KHz negative phase signal of FIG. 5 (A) applied to the fourth input terminal (26). The output signal shown in FIG. 5(a) is generated, and in the fourth multiplier circuit 133), the 114 KHz positive phase signal of FIG. 5(b) applied to the second input terminal (5) and the third The signal is multiplied by the 38 KHz positive-phase signal shown in FIG. 5 (c) applied to the input terminal (28), and the output signal shown in FIG. By adding the output signals of the multiplier circuits 01) and 0(8), the second output terminal c39 receives a 76KHz rectangle with a duty such that the Irepel I period is winter, as shown in FIG. wave signal is obtained.

Therefore, if one of the signals obtained at the first or second output terminal 0 or 0 is used to control the compensation circuit switch (23), interference caused by beats around 114 kHz can be removed. I can do it.

In that case, if the switch is of a type that conducts when the switch is set to low level, the first output terminal (34
) is used for control, and the signal obtained at switch 0
If 31 is of the type that conducts at high level σ-D, the signal obtained at the second output terminal 05) in FIG. 4 is used for control.

FIG. 6 shows a specific circuit example of the block diagram in FIG.
It is constructed of a double-balanced differential amplifier circuit consisting of sixth to sixth transistors (3G) to (41). The 38KITZ positive phase signal is applied to the base of the first transistor (3t3), and the 38KITZ positive phase signal is applied to the base of the second transistor (37).
Hz reverse phase signals are respectively applied. In addition, the common base of the third and sixth transistors (41)
A 14KHz positive phase signal is applied to the common base of the fourth and fifth transistors (40), and a 114K1 (114K1) negative phase signal is applied to the common base of the fourth and fifth transistors (40, respectively. The output signal shown in (g) is output from the second output terminal (4
The output signals shown in FIG. 5 (N) are obtained on each floor.

7(a) and 7(b) respectively show the stereo sum signal obtained at the output end of the sub-signal decoder (7) and the 7th
Figures (c) and 2) respectively show the first and second adder circuits (
15) and (17) at the input end. As shown in Figure 7 (a) and (b),
Sub signal decoder (the stereo sum signal at the power output end is 3
It can be expressed as an envelope of an 8KHz switching signal. Therefore, as the switch of the compensation circuit (23), a type that conducts at level 2 is used, and as the control signal for the switch (23), the signal shown in Figure 5 (2) is used. Then, the first addition circuit (I
As shown in Figure 7 (C), the signal obtained at the input terminal of 5) is partially mixed when the switch (C) is turned on, reducing the degree of separation and containing the third harmonic of 38 KHz. The result is a step-like waveform with no shoulders. Similarly, the signal obtained at the input terminal of the second adder circuit 07) also has a stepped waveform, as shown in FIG. Note that the envelopes of the signals in FIGS.
) is also not affected by the control of the switch t23).

As is clear from the above description, the demodulated stereo sub-signals (T, -R) and (R-
Since no beats are included in T, ), the stereo sub-signals (L-1'() and (R-L) and the stereo sum signal (T, +R) are sent to the first and second adder circuits 05 ) and (1η), the left and right stereo signals obtained at the first and second output terminals (16) and (+81) are
Beats are not included in L+ and (8) either.

In the embodiment shown in FIG. 3, the case where beats are removed from the demodulated stereo sub-signal has been explained.
A compensation circuit 1) may be inserted between the first and second output terminals α6) and (R) to remove beats from the left and right stereo signals ff, ) and (R). In addition, in the example, 3
8I (1 1 which is the third harmonic of the Hz switching signal)
11 in the input signal using a square wave signal of 4 K+lZ
4 K) The case of removing beats caused by beats in the vicinity of lz has been described, but using a square wave signal of the nth harmonic frequency of a 38 KHz switching signal, the nth harmonic in the input signal can be removed. Beats caused by beats near the wave frequency can be removed in exactly the same way, and if they are combined to create a compensation circuit, the beat removal effect will be further improved.

(f) Effects of the Invention As described above, according to the present invention, it is possible to provide a stereo demodulation circuit that can be easily integrated into an IC, has a simple circuit configuration, and eliminates beat interference.

[Brief explanation of the drawing]

1 and 2 are circuit block diagrams showing a conventional stereo demodulation circuit having a beat interference removal function, and FIG.
FIG. 4 is a circuit block diagram showing one embodiment of the present invention, and FIG. 5 is a circuit block diagram showing an example of the control signal generation circuit.
Figures (A) to (J) are waveform diagrams for explaining the operation of Figure 4, Figure 6 is a circuit diagram showing a specific example of Figure 4, and Figures 7 (A) to (6) are waveform diagrams for explaining the operation of Figure 4. , is a waveform diagram for explaining the operation of FIG. 3. Explanation of main drawing numbers (7)...Sub signal decoder (''...P T,
L circuit (goods)...Compensation circuit (23)...Swift (25)...Control signal generation circuit Fig. 1 fJ2 Fig. 4 n Fig. 5 Fig. 7

Claims (1)

[Claims] (]) In a stereo demodulation circuit that demodulates left and right stereo signals from a stereo composite signal including a stereo sum signal, a stereo difference signal, and a stereo pilot signal,
A third rectangular wave signal is created from a first rectangular wave signal of 38 KHz synchronized with the pilot signal and a second rectangular wave signal having a frequency equal to an odd harmonic of the first rectangular wave signal, and the third rectangular wave signal is The present invention is characterized in that the degree of separation between the left and right stereo signals is partially reduced using a wave signal, and a beat occurring between an odd harmonic of the first rectangular wave signal and a beat between adjacent stations is removed. Stereo demodulation circuit.