JPS6041883A - Decoding system of coded data - Google Patents

Abstract

PURPOSE:To realize speed up and miaturizing of a decoding and processing system by using the output data of a memory means at a point of time when decoded data are read out from a combined address of input coded data and succeeding reading address as decoded data corresponding to input coded data. CONSTITUTION:When a start command is inputted to an FF51 and a latch circuit 50, a clock signal is supplied to a first-in and first-out register 10 and the latch circuit 50 through an AND gate. Consequently, the data of 1 bit of output step in the register 10 and the output of the latch circuit 50 in which all values reset by a starting signal is in ''0'' state are supplied to a table 20. Accordingly, if the output value of the register 10 is ''0'', stored data of address ''0'' are read out from the tble 20. If the output value of the register 10 is ''1'', the address of the table 20 obtained by adding the value ''1'' to next reading address latched by the latch circuit 50 is accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field The present invention relates to an encoded data decoding method for decoding encoded data such as an encoded facsimile IJ image.

(b) Prior art In the field of technology for transmitting large amounts of data such as facsimile images and storage technology for large amounts of data, it is common practice to encode original information and compress the amount of data to increase transmission efficiency and storage efficiency. .

A method shown in FIG. 1 has been proposed as a method for decoding such codes.

FIG. 1 is a diagram illustrating a conventional decoding method.

In the figure, 1 is a shift register, 2 is a code table memory, 3 is a comparison section, 4 is a decoding data triple memory, and a 5-digit control section.

Explain the operation.

The input code to be decoded is introduced bit by bit into the shift register 1. Every time a 1-bit code is input to the shift register 1, the control section 5 supplies the read address "0" to the code table memory 2. The code read from the table memory 2 and the data in the shift register 1 are compared in the comparing section 3. When the comparison unit 3 issues a non-coincidence output, the control unit 5 increments the read address for the table memory 2, and repeats the same process. Even if the control unit 5 supplies all the read addresses allocated to the table memory 2, if a comparison match output is not obtained from the comparison unit 3, the control unit 5 further instructs the shift register 1 to perform bit shift and Supplies the shift clock for input,
The comparison test operation described above is repeated. When the comparator 3 issues a comparison match output, the controller 5 converts the address data currently being supplied to the table memory 2 into the table memory 4.
I will give it to you. Decoded data is stored in the table memory 4, and the table memory 4 outputs the decoded data stored at the address given by the control unit 5 as decoded data corresponding to the input code. Thereafter, the control unit 5 issues a shift clock to input the next bit into the shift register 1 after setting all the data stored in the shift register to logical zero or invalid data.

The decoding method described above has been conventionally employed as an effective method when the input code is not a fixed code length but has a variable length.

However, in the conventional encoding system described above, each time one bit or a predetermined bit code is input, the table memory 2
C has the drawback of requiring a large amount of processing time, as it is necessary to search multiple times if there are many addresses.
1. Furthermore, since a code table memory is required in addition to the decoded data table memory, the apparatus also has the disadvantage of increasing in size.

(C) Object of the Invention The object of the present invention is to provide a coding system for input coded data that can be processed at high speed and miniaturized in order to eliminate the above-mentioned conventional drawbacks.

(d) Structure of the Invention In order to achieve the above object, the present invention provides data at a next read address linked to the address of decoded data corresponding to input encoded data or decoded data corresponding to input encoded data. is stored in an address that is a combination of the next read address data and the input encoded data, and the storage means stores the encoded data at the time when the encoded data is read from the combined address of the input encoded data and the next read address. The output data is the decoded data corresponding to the input encoded data.

(e) Example Figures 2 and 3 are code diagrams and code (=b genealogy) for explaining the -94 to 1j example of the present invention.
FIG. 5 is a block diagram and an explanatory view of essential parts of one example of the present invention.

FIG. 2 is a code diagram used in the run-length encoding method. In the figure, the right column indicates the run length, that is, the continuous length of one image (for example, the continuous FC number of black pixels) [in the tree table] - original information], and the right column 1d Corresponding to each length, disease 1” applied coat (
input encoded data).

In the run-length encoding method, the number of bits of the code is variable depending on the frequency of appearance of the original information.

In other words, the figure shows Rin, which has the highest frequency of consecutive black pixels or [2] bits.

Note that the original information, that is, the decrypted data, is shown in [ ], and in this example, the text in [ ] is -It! An elementary series ht; a number indicating a number.

Expand the chord diagram in Figure 2 into a tree, /<- is the third
As shown in the figure.

In the figure, the numbers in [ ] indicate the original information shown in FIG. 2.

Mfc, "C error]'" d1 shows a very good code as the code in FIG.

In the figure, “■” (°0) is the branch number.
Each bit of the code in 1r is shown, and the next bit of each code is allocated from the beginning of each code to the genus ↓ number, and the next bit of each code is assigned to the end of each code, and expanded in a tree shape. Original 4 in the diagram? Source + B [6) J, code 0010'
“The position in the tree in Figure 3 is incorrect.

At dawn, we move on to the next tower.

The first bit of the code '0010', the value '0', is the branch ■
It originates from and is located at the position of the branch ■.

The second bit, g, value 1'0'' of the code '0010'' originates from the branch ■ and is located at the position of the branch ■. Code ゛OO] The third bit of 0P, G, value "1" originates from the position of branch ■ and is located at the position of branch ■. 4th bit, value of code 0010'
0'' originates from the position of the branch ■ and is located at the position of the branch [phase].

Using such a tree, a method for reproducing restored data when a code is input in units of units (one bit in this example) will be explained.

As an example 7, code ° “011” (original information [4])
) Explanation of the reprinting method when the 114th input is made. When the first bit O1'' of the code "011" is input, the decoding means (details will be described later) starts from the branch ■ and finds the branch ■ where the corresponding value "0pa" exists.

When the second bit of the code "011", "Do1'" is input, the encoding means selects the branch ■ having the corresponding value "1" from among the branches ■ and ■ related to the branch ■. Ru.

Furthermore, when the third pit "1" is input, the decoding means
Among the branches ■ and ■ related to branch ■, select the branch ■ that has the corresponding value "1". As a result, the original (i'i report "[4]") is reproduced. Each school is a branch ■ ,■.

■,■,■,■, [phase] or the terminal branch■,■,■
.

(2), [Phase], 0.0.0 can be determined by making it occur simultaneously when each school is accessed as the identification data (decoding end instruction data) of the branch type in each school.

In addition, each school can be identified by associating the numerical values of mold entry and exit with already identified branch branches.

As described above, by determining the encoded data input through each school, the reprinting means can generate decoded data by processing the encoded data as many times as the number of focuses matches.

That is, high-speed decoding becomes possible.

FIG. 4 shows a block diagram of an embodiment of the present invention that embodies the embodiment explained using FIGS. 2 and 3, and FIG. 5 shows the main parts of FIG. FIG.

10 in the figure is a first-in first-out register;
20 is a table circuit, 50 is a child circuit, 51 is a flip-flop circuit, and 52 is an AND gate. The table 20 stores data in the format shown in FIG.

The addresses in the table 20 correspond to the branch numbers explained in each FIG. In each address, the above-mentioned identification data indicating whether the branch branch 75 is the terminal branch is stored.

Also, if the address corresponds to the terminal branch,
The original information for that branch is stored.

Further, in this embodiment, the next read address corresponding to one branch branching from the branch branch is stored at the address of the branch branch in FIG. 3, which is already known in the notebook 20. If the next hit of the input code is the value ``0'' depending on whether it is the value 1 or the value 0, the address of the branch branch is used as it is, and the next read address is written down. The other branch is
Add the value ``1'' to the address already specified above, that is, the address to which the input focus value ``1'' is added, stores the next (7) read address or original information. .

The operation shown in FIG. 4 will be explained with reference to FIG.

First, a start command is input to the reset off terminal of the flip-flop circuit 51 and launch circuit 50.

Flip-flop 51 raises its output and opens AND gate 52. A clock signal is input to the second gate 52, and when the second gate 52 becomes open, the clock signal is input to the second gate 52.
The signal is supplied to the iFO register 10 and the latch circuit 50.

As a result, in the table 20, the 1-bit data of the output stage in the 1riFo register and all the candy reset by the start input are ``0'' + the missing latch circuit 5.
The output of 0 is used as an address signal and is supplied with -C.

From table 20 to Fi11i'o and register 10 (1
) If the value of JAO is 0'', the data stored at address ■ in FIG. 5 is read out. This INj, WRf
According to FIG. 5, the value of the data is ``0'',
This shows the branch mentioned above.

On the other hand, the data stored in the data area, ie, the next read address (2) as described above, is read out and set in the digital memory 50 together with the identification data.

The next clock signal is applied to FiFo register 0. Supplied to latch 50.

The next value of the FiFo register 0, for example "°°1", is read out. At this time, the next read address ■ latched in the latch circuit 5o and the value "'1" of the FiFo register O are read out.
” is supplied to the table 20 as the address of the table 20. That is, this att/s is the next read address
This corresponds to address ■ which is obtained by adding the value ``lt'' to .

From address ■ in table 20, identification data II Q
I+ and the next 1 output address ■ are read out and the latch circuit 50
Now, I get hit.

Further, the next clock signal passes through the AND gate 52 and is input to Fi
Fo register 0 is supplied to child circuit 1o.

, when the output value of the FiFo register 10 is the value "1", the next output 1 latched by the latch circuit 50 is
The address ■, which is the value "1" added to the output address ■, and the address ■ of the table 20 are accessed.

Identification data "1", that is, identification data indicating that decoding has been completed, and original information [4] are stored at address (2) of the table, and the image information is read out and latched by the latch circuit 50.

The latch circuit 50 thereby performs I1i′, 111M
The identification data is supplied to the reset terminal R of the flip-flop 5J to reset the flip-flop circuit 51. Furthermore, since this identification data becomes the value "1", the circuit (not shown) that uses the original information is notified of the restoration completion, and as described above, the original information of the child circuit 50 is transferred. According to the above embodiment, the table (storage means) stores the decoded data mixed in the next acquisition address, and only stores one J-bit identification information, which makes the device small. Of course, the purpose of the present invention, which is to speed up processing, is also possible because it is sufficient to access the memory the same number of times as the number of pits in the encoded data.

In the above embodiment, seven types of codes were explained for the sake of simplicity, but the present invention is not limited to these. The relationship between each school and the address is not limited to the above example, but the address can be created by combining the already known address and the unit amount data to be input next. Also good.

(0) Effects of the Invention As described in detail above, according to the present invention, decoded data can be obtained quickly by accessing the storage means the same number of times as the number of bits of encoded data.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional decoding device, Figures 2 and 3
The figure is a code diagram and a code system diagram for explaining the principle of an embodiment of the present invention, and Fig. 5 is a block diagram and a diagram illustrating main parts of an embodiment of the present invention. In the figure, 20 is a table, ]0 is a FIFo register, and 50 is a latch circuit. Agent: Hiroshi Matsuoka, patent attorney.

Claims (1)

[Claims] a first storage means for storing decoded data corresponding to the input encoded data and read address data to be read next at mutually different addresses; a second storage means for storing decoding end instruction data at an address; a predetermined number of input codes and the read address data stored in the first storage means; and memory access means that accesses the second storage means every time the predetermined number of codes are input, and when the decoding end instruction data is read by access by the memory access means, the corresponding first memory A method for decoding encoded data, characterized in that the output of the means is decoded data corresponding to input encoded data.