JPS6041342A - Clock selection control system - Google Patents

Abstract

PURPOSE:To discriminate automatically the connection mode of a terminal equipment by discriminating whether the distance from a network terminating equipment to the nearest terminal equipment is shorter than a prescribed value or not, and outputting a clock signal of a fixed phase output or a digital phase synchronizing circuit output in accordance with this discriminated result. CONSTITUTION:The shortest terminal distance identifying circuit LID detects violation of a frame synchronizing signal to identify the distance from the network terminating equipment to the nearest terminal equipment on a basis of a frame phase pulse indicating the phase of the transmission frame synchronizing signal. If this distance is shorter than the prescribed value, a clock signal of a fixed phase is selected from a transmission control circuit SC by a selector SEL and is sent to a retiming circuit RTM. If said distance is identified that it is not shorter than the prescribed value, the output clock signal of a digital phase synchronizing circuit DPLL is selected by the selector SEL and is sent to the circuit RTM.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention provides
Relating to a clock selection control method that automatically switches between a digital phase-locked loop (DPLL) clock signal and a fixed-phase clock signal as a retiming clock signal, depending on the connection type with a 75-unit terminal. It is something.

Prior Art and Problems In the integrated service digital network (ISDN), the connection form between the subscriber's home network termination equipment and the subscriber terminal is connected to point 1 or multipoint as shown in Figure 1. Format and as shown in Figure 2;] Point to Point 1
~ There is a format. In connection form 1 shown in FIG. 1, a network termination device NT and a plurality of terminal devices TEa-TEn are connected by T and R lines in the form of a bus. According to the CCITT proposal, the maximum distance β1 from E”' a ” T E n is 100 to 15
It is less than 0m. In addition, in the connection form shown in FIG. 2, the network termination device N1' and the terminal device TE are connected one-to-one by the T line and the R line, and the maximum distance β2 between them is as shown in FIG. According to the CCITT proposal, it is less than IKm.

The frame structure on the T line and the R line is, for example, a 64 K b/s channel Bl, as shown in FIG.

B2 and channel D of 16 Kb/s are multiplexed in a time division multiplex format and a frame synchronization signal F is added. Also, as a transmission code, 100%
It is being considered to use an AMI code (“bi is o”, “o” uses positive and negative pulses alternately) and use a violation as the frame synchronization signal. For example, as shown in FIG. The frame synchronization signal F is “0”, 0”,
If the pulse before that (D"0" is a positive polarity pulse, it will be considered a positive polarity pulse and a negative polarity pulse, and if the previous "0°'" is a negative polarity, it will be considered a negative polarity pulse and a positive polarity pulse. , (V) indicates a violation.

In the connection configuration shown in FIG. 1, a frame synchronization signal F is sent from the network termination device NT to the R line, each terminal detects the frame phase, creates its own frame, and connects the network via the T line. It is sent to the terminal device NT. Also, in the connection configuration shown in Fig. 2, the network termination device NT
The terminal equipment detects the frame synchronization signal F sent from the network to the R line, creates a frame at the terminal equipment, and sends it to the network terminal equipment NT via the 'r line. In the case of the point-to-point format shown in Fig. 2, 11i11
In the terminal device NT and the terminal device TE, by a digital phase synchronization circuit (DPLL) which is energized.

Although it is possible to extract the clock component from the received data, in the case of the point-to-multipoint format shown in FIG. 1, the extraction of the clock component at the network termination device NT poses a problem.

In other words, since the distances from the network termination device NT to each terminal device are different and they are multiplexed on the T line, the data phase from each terminal device at the reception point of the network termination device NT is different, and the clock is not output in the energized DPLL format. It is technically extremely difficult to extract the components, and it is better to use a fixed-phase clock signal created based on the transmission clock signal phase as the retiming clock signal in the I2I termination device NT.

For example, in FIG. 5, 611 is connected from the network terminal device NT to
signal sent to the line, (bl is v1 near the network termination device NT)
! The received signal of the terminal device TEa, (C) is the received signal of the terminal device TEa.
transmission signal, (di is the reception signal of the terminal device TEn far from the network termination device NT, (8) is the transmission signal of the terminal device TEn, channels B, , B2 each have 3 bits, 1- bit, channel D has 2 bits, The frame synchronization signal F is composed of 1 bit 1-, and if the width of 1 bit is T, then from the terminal device TEa (as shown in C1), by channel B2 synchronized with the frame synchronization signal F, b2L, b22. The data is sent and received by the network termination device NT with almost no delay, but at the distant terminal device TEn, the frame synchronization signal F from the network termination device NT is received with a delay corresponding to the distance ( As shown in el, bll is generated by receiving frame J and channel B synchronized with synchronization signal F.

bl2. The data b21.bl3 is sent out, and the network terminal device NT receives the data b21. b2
2. b23 and data b sent from the terminal device TEn
ll, b12. b13 and (as shown in 0, -g1
% overlap.

Therefore, in the network terminal device NT, it is difficult to extract the clock component from such received data using the DPLL. Therefore, as shown in ([1], retiming is performed using a fixed-phase clock signal that is synchronized with the transmission frame synchronization signal F and started from the phase of (3/4)T. In the point-to-multipoint system, since a timing clock signal is used, a limit is placed on the distance 81 between the network termination device NT and the terminal device TEn.

If it is necessary to increase the distance between the terminal devices and the network termination device NT, connect the terminal devices in the point-to-point format shown in Figure 2 to shorten the distance between the terminal devices,
In addition, if it is necessary to connect multiple terminal devices, the first
Terminal devices will be connected in the point-to-multipoint format shown in the figure. In cases where the connection configurations are different in this way, it is necessary for the network termination device NT to select whether to use the DPLL output clock signal or a fixed phase clock signal as the retiming clock signal. In order to make such a selection, a configuration shown in FIG. 6 can be considered. In the figure, RCV is a receiver that receives signals from the T line, DPLL is a digital phase synchronization circuit, RTM is a retiming circuit, SEL is a selector,
SC is a transmission control circuit, and SW is a changeover switch.

A fixed phase clock signal is applied from the transmission control circuit SC to the selector SEL, and the digital phase synchronization circuit DP
LL extracts a clock signal from the received data, and this clock signal is applied to selector SEL. The clock signal selected by the selector SEL is applied to the timing circuit RTM to perform timing of data received by the receiver RCV. Also changeover switch SW
can be switched manually; for example, when switched to the ground side, the selector SEL is switched to the digital phase synchronization circuit D.
When the clock signal from the PLL is selected and switched to the +V side, the selector SEL selects a fixed phase clock signal, and in the case of the point-to-multipoint format shown in Figure 1, the selector SEL selects the clock signal with a fixed phase. The switch will be switched to the +V side, and the point to point shown in Figure 2 will be changed.
In the case of the point type, the changeover switch SW is switched to the ground side.

As mentioned above, in the conventional system, it is necessary to switch and select the clock signal for retiming using the changeover switch SW depending on the connection type, which has the drawback of requiring only one operation.

OBJECTS OF THE INVENTION It is an object of the present invention to enable a network termination device to automatically identify the connection form of a terminal device and select a retiming clock signal.

Structure of the Invention The present invention provides a means for transmitting a frame synchronization signal, a digital phase synchronization circuit for extracting a clock signal from received data, a means for timing the reception data, and a fixed phase synchronization circuit synchronized with the phase of the frame synchronization signal. In a system in which a terminal device is connected in a point-to-point format or a point-to-multipoint format to a network termination device equipped with a clock signal generating means, a frame indicating the phase of the frame synchronization signal. A shortest terminal distance identification circuit that identifies the distance to the terminal device based on the time relationship between the phase pulse and the detected pulse that detects violation of the received frame synchronization signal, and extraction using the fixed phase clock signal and the digital phase synchronization circuit. and a selector for selecting the fixed phase clock signal, and when the shortest terminal distance identification circuit identifies that the terminal device is less than a predetermined distance, the selector selects the fixed phase clock signal and selects the fixed phase clock signal. When it is determined that the distance is greater than or equal to the distance, the selector selects the clock signal of the output of the digital phase synchronization circuit, and the reception data transfer timing is performed using the clock signal selected by the selector. Explain in detail.

Embodiment of the Invention FIG. 7 is a block diagram of main parts of an embodiment of the present invention, and the same reference numerals as in FIG. 6 indicate the same parts.
is the shortest terminal distance identification circuit.

This shortest terminal distance identification circuit LID detects a violation of the arene synchronization signal and determines the distance Mf from the network termination device NT to the nearest terminal device based on the frame phase pulse indicating the phase of the transmitted frame synchronization signal.
Identify whether t is less than or equal to a predetermined distance, and set the predetermined distance 1
In the case of i111 or below, it is determined that the point-to-multipoint format shown in the first till is selected, the fixed phase clock signal from the transmission control circuit SC is selected by the selector SEL, and the clock signal is sent to the retiming circuit RTM. is supplied to perform retiming.

If it is determined that the distance is not less than the predetermined distance, it is determined that the point-to-point format shown in FIG.
Select the clock signal of the output of L and retiming circuit R
The clock signal is supplied to the TM to perform retiming.

FIG. 8 shows the shortest terminal distance identification circuit L according to the embodiment of the present invention.
This is a block diagram of the main parts of ID, where VDT is a violation detection circuit, MMV is a mono-multi high break, and G1 is a violation detection circuit.
BAND circuit, FF1. FF2 is a flip-flop. FIG. 9 is an explanatory diagram of the operation, and the frame phase pulse a indicating the phase of the transmission frame synchronization signal F is shown in FIG.
This frame phase pulse a is sent out at a constant cycle as shown in FIG. As shown in FIG. 9(b), the output signal of the mono-multi-by-break MMV is triggered by the frame phase pulse a and outputs a signal with a predetermined time width. In addition, the high violation detection circuit V D 'r'' detects a violation of the received frame synchronization signal F and outputs a detection pulse C. is, the output of AND circuit G1 is 1
'', and the output signal of the AN1 circuit G1 is applied to the set terminal S of the flip-flop FFI, so the flip-flop FFI is set and the Q terminal output d becomes 1''. In other words, it is as shown in (d+) in FIG. 9. Since this Q terminal output d is applied to the data terminal of the flip-flop FF2, the merit flip-flop FF2 is set to 1- for the next frame phase pulse a. The Q terminal output e is the 9th
The result is shown in (e) of the figure. This Qα11,1 child output e becomes a switching signal for the selector SEL.

In this way, when the switching signal becomes "1", it indicates that the shortest terminal distance is less than the predetermined distance, so the connection form is the point-to-point type shown in FIG.
The fixed phase clock signal from the transmission system ta11 circuit SC is selected by the selector SEL, and the retiming circuit R
Add to TM.

Also, the violation detection circuit VDT detects a violation in the received frame synchronization signal, and the detection pulse C
As shown in (fl) in FIG.
1. Since FF2 is not set (-), the Q terminal output of flip-flop FF2 is "'" as shown in (g+) in FIG.
Since it remains at 0' and the switching signal applied to the selector SEL is 0', the clock signal of the output of the digital phase locked circuit DPLL is selected and the retiming circuit RTM
will be added to.

That is, since the shortest distance between terminal devices is longer in the point-to-point format than in the point-to-point format, the violation detection pulse of the received frame synchronization signal is mono-multi-high break. M
Since the MV output signal will not be output within the time, in such a case, the switching signal of the Q terminal output e of the flip-flop FF2 will be "0", and the selector SEL will change the output signal of the digital phase locked circuit pPLL. The I cock signal, ie, the clock signal extracted from the received data, is applied to the retiming circuit RTM.

FIG. 10 is a block diagram of the violation detection circuit VDT according to the embodiment of the present invention, in which CMP1 and CMP2 are comparators of the receiver RCV, FF3 to FFG are flip-flops, SRI, 5R2t co-shift register, G2-G
5. GIO is Nando times! ? 8.06 to G9 are OR circuits. Also, clk is a high-speed clock signal, THI and TH2 are dark value voltages of comparators CMP I and CMP2, (1) to (1
4) shows the reliability of each part, and examples of signals (1) to (14) of each part are shown with the same symbols in the operation explanatory diagram of FIG. ) indicates a violation.

When the received data (1) shown in (1, 1 in FIG. 11) is input to the receiver RCV via the T line, the comparators CMP1.
CMP2 compares the threshold voltages THL and TH2, and the positive pulse is output from the comparator CMP1 to (2) in Fig. 11.
The negative polarity pulse is output as shown in the comparator c+v
pz is output as shown in (3) in FIG. Also, the high-speed clock signal clk is applied to the flip-flops FF3 to
Clock terminal C of FF6 and shift register SRI, S
It is added to the clock terminal of R2, and the comparator CMP
The output signal (2) of No. 1 is applied to the data terminal of flip-flop FF3, and the output signal (3) of No. 2 is applied to the data terminal of comparator CMI) and flip-flop FF5, respectively.

Output signal (2) or (
3) is "1", the ζ terminal output of flip-flop FF3 or FF, 5 becomes "1", and the next high-speed clock signal clk causes the ζ terminal output of flip-flop FF4 or FF6 in the next stage to become "1". '1 Pa. NAND circuit G
The Qy (1 child output) of flip-flops FF3 and FF4 is added to 2, and the ζ terminal output of flip-flops FF5 and FF6 is added to NAND circuit G3. G2 or G
3 output signal (4) or (7) becomes O''. (4) and (7) in FIG.
).

These output signals (4), +71 are the comparator CMPI
, CMP2 output signal +21. (This corresponds to the differential signal of the rising edge of 31.

Shift registers SR1 and SR2 are NAND circuits G2. G
3 output signal (4+, (71 to high speed clock
k, and outputs after a time of 1 bit width, and the output signal (fi+,
The output signal (5) of R1 and the ζ terminal output of flip-flop FF3 are applied to the OR circuit G6.
The output signal (6) is as shown in (6) in FIG. That is, since the ζ terminal output of the flip-flop FF3 and the outputs F, 9 (51) of the shift register SRI do not become 0'' at the same time, the output signal (6) of the OR circuit G6 continues to be 1''.

Also, the output signal (8) of the shift register SR2 and the ζ terminal output of the flip-flop FF5 are applied to the OR circuit G9, and the output signal (9) of this OR circuit G9 is output as (9) in FIG.
). Ikuji flip-flop FF5 ζ
At the timing when the terminal output and the output signal (8) of the shift register SR2 simultaneously become "0", the output signal (9) of the OR circuit G9 becomes 0.

Also, from shift registers SRI and SR2, NAND circuit G4.
The signal input to G5 can be, for example, the output signal of the first stage flip-flop of the shift registers SRI and SR2, and the high-speed clock signal c
Since it is shifted by G2.lk, the NAND circuit G2. G3 output signal (4).

The time delay for (7) is negligible. Therefore, NAND circuit G4. G5 output signal 00).

(11) is 001. in FIG. (11). This output signal 00) and the output signal (7) of the NAND circuit G3 are input to the OR circuit G8, and the output signal (13) of the OR circuit G8 becomes "1" as shown in (13) in FIG. It becomes a series of Further, the output signal (II) of the NAND circuit G5 and the output signal (4) of the NAND circuit G4 are input to the OR circuit G7, and the output signal (12) is the output signal as shown in (12) in FIG. (11) is "'0"
“0” when the output signal (4) becomes °’0”
becomes.

Each output signal of OR circuit 66 to G9 +61. (12)
.

(13), +91 becomes °0'', the output signal (14) of the NAND circuit GIO becomes (14) in FIG.
) becomes “1” as shown. This output signal (I4) becomes a violation detection signal. That is, the first
The first high oleasis condenser (V) in (1) of Figure 1 is the case where a positive pulse is input next to a positive pulse, and the output of the flip-flop consisting of NAND circuits G4 and G5. When the signal (11) is "0", the NAND circuit G is the 11th order pulse of the rising edge of the positive polarity pulse.
Since the output signal (4) of 2 becomes "0", the OR circuit G7
The output signal (I2) becomes 0'', thereby the violation detection signal (14) becomes 1''.

Moreover, when a negative polarity pulse is input successively after a negative polarity pulse, the output signal of shift register SR2 (
8) becomes "0", and therefore the output signal of OR circuit G9 (
9) becomes "'0", while the violation detection signal (14) becomes "°1".

As mentioned above, violations of consecutive pulses of the same polarity are caused by flip-flops FF3. The ζ terminal output of FF5 and the output signals of shift registers SRI and SR2 (51,'
(By 81, the output signal of OR circuit G6.G9 (61,
(Violations in which pulses of the same polarity are spaced apart can be detected when 91 becomes "0°',"
NAND circuit G4 constituting a flip-flop. G5 output signals (10), (11) and NAND circuit G3. Due to the output signal of G2 (7+, (41), the OR circuit G8.G
This can be detected when the output signals (13) and '(12) of 7 become "0".

FIG. 12 is a block diagram of an example of a mono-multi high break MMV, and shows a case where it is configured by a counter CTR. FIG. 13 is an explanatory diagram of the operation. When the frame phase pulse a is input to the low F terminal of the counter CTR as shown in FIG. 13 (al), the initial value A is set in the counter CTR. As a result, counter C
The output terminal CA of TR becomes 0''. Therefore, in-hark I
The output signal S of NV becomes "1" and is applied to the count enable terminal EN of the counter CTR, starting the run 1- of the high speed clock signal clk. Since the output terminals C and A become "1" due to the predetermined count contents, the output signal of the inverter INV becomes "0",
Since "'0" is also input to the count enable terminal EN, counting of the high speed clock signal elk is stopped. Therefore, the output signal shown in (bl) in FIG. 13 is obtained.

The time width of this output signal can be arbitrarily set by selecting the initial value A. That is, network terminal equipment NT
The shortest terminal distance can be identified by setting the time width to the propagation time corresponding to the shortest distance from the terminal.

Note that as the configuration of the multi-by-break MMV, it is of course possible to adopt a configuration using a well-known OCR time constant, etc., in addition to the above-described embodiments.

As described in detail, the present invention provides the connection form of the terminal device to the shortest terminal function Ii! II identification circuit LID is used for identification, and this identification is performed based on the time relationship between the frame phase pulse and the violation detection pulse of the received frame synchronization signal. For example, it is determined that it is a point-to-multipoint format and a fixed phase clock signal is selected, and if the distance is greater than a predetermined distance, it is determined that it is a point-to-point format and extracted by the digital phase synchronization circuit DPLL. The system selects a clock signal that has been selected and performs the timing of receiving data using the selected clock signal.
The clock signal can be selected depending on the connection type.

Therefore, there is an advantage that operability is improved.

[Brief explanation of the drawing]

Figures 1 and 2 are explanatory diagrams of the connection form of the terminal device;
4 is an explanatory diagram of frame synchronization signal violation, FIG. 5 is an explanatory diagram of operation in the connection configuration of FIG. 1, and FIG. 6 is a block diagram of main parts of the conventional example.
FIG. 7 is a block diagram of the main part of the embodiment of the present invention, FIG. 8 is a block diagram of the shortest terminal distance identification circuit of the embodiment of the present invention, FIG. 9 is an explanatory diagram of its operation, and FIG. FIG. 11 is a block diagram of the violation detection circuit of the embodiment, FIG. 11 is an explanatory diagram of its operation, FIG. 12 is a block diagram of an example of a mono-multi-high flake, and FIG. 13 is an explanatory diagram of its operation. NT is the network terminal equipment, TB and TEa-TEn are the terminals. Not equipped, RC is receiver, RTM is retiming circuit,
DPLL is a digital phase synchronization circuit, SC is a transmission control circuit, SEL is a selector, LID is a shortest terminal distance identification circuit, VDT is a violation detection circuit, and MMV is a mono-multi-by-break. Patent Applicant Fujitsu Limited Patent Applicant Nippon Telegraph and Telephone Public Corporation Patent Attorney Shoji Aitani Attorney Patent Attorney Hiroshi Watanabe - Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 (9) −−−−−−−−−−−−−−−−−−
'Fig. 10lk Fig. 11 (5)'"1"' (6) "I... (n) 1 (14)...d. Fig. 12 Fig. 13 (a) (b)

Claims (1)

[Claims] A means for transmitting a frame synchronization signal, a digital phase synchronization circuit for extracting a clock signal from received data, a means for timing the received data, and a means for generating a fixed phase clock signal synchronized with the phase of the frame synchronization signal. In a system in which a y6H, H floor device is connected in a point-to-point format or a point-to-multipoint format to a network termination device equipped with a a shortest terminal distance identification circuit that identifies the distance to the terminal device based on the time relationship between the frame phase pulse indicated by the signal and the detection pulse that detects the high orientation of the received frame synchronization signal; and the fixed phase clock signal and the digital phase synchronization circuit. a selector for selecting the extracted clock signal, and the shortest MjAt
When the end distance identification circuit identifies the 0(;) floor device as being less than or equal to a predetermined distance, the selector selects the fixed phase clock signal; A clock j Bessawa control system characterized in that a clock signal output from the digital phase synchronization IEjl Wfs is selected by a selector, and reception data timing is performed by the clock signal selected by the selector G.