JPS6037758A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6037758A JPS6037758A JP58145930A JP14593083A JPS6037758A JP S6037758 A JPS6037758 A JP S6037758A JP 58145930 A JP58145930 A JP 58145930A JP 14593083 A JP14593083 A JP 14593083A JP S6037758 A JPS6037758 A JP S6037758A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- fixed
- chip
- semiconductor element
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、１つのパッケージに２つ以上の半導体素子チ
ップを含むマルチチップ型半導体装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-chip semiconductor device including two or more semiconductor element chips in one package.
近年、電子機器は装置の小型化、軽介化が進み。In recent years, electronic equipment has become smaller and easier to use.
これに伴い部品の小型化と部品点数の低減が進められて
いる。Along with this, progress is being made in miniaturizing parts and reducing the number of parts.
半導体装置においても、集積回路の集積素子数の増大パ
ッケージの小型化が進められている。しかし、小型化の
為に集積回路１個のチップにすべて心壁な回路機部を盛
り込むことは技術的にも経済的にも不可能な場合も多い
。この場合はやむを得ず１つのパッケージに２つ以上の
半導体素子チップを使用することになる。例えばバラン
スドミキサー例用いられる特性のそろった２ケの電界効
果トランジスタ（以下、ＦＥＴという）チップを１つの
パッケージに入れたマツヂドデュアルＦＥ’Ｉ’と云わ
れる半導体装置が考えられる。In the field of semiconductor devices as well, progress is being made in increasing the number of integrated elements in integrated circuits and downsizing packages. However, in many cases, it is technically and economically impossible to incorporate all the essential circuit parts into a single integrated circuit chip for miniaturization. In this case, it is unavoidable to use two or more semiconductor element chips in one package. For example, a semiconductor device called a mated dual FE'I' can be considered, in which two field effect transistor (hereinafter referred to as FET) chips having the same characteristics used in a balanced mixer are housed in one package.
ｍ１図は、この様な従来例を示すもので、所定のリード
フレームにチップを固着し、ボンディングワイヤーで結
線した状態である。Figure m1 shows such a conventional example, in which a chip is fixed to a predetermined lead frame and connected with a bonding wire.
第１の半導体素子チップ１．！ｌ：第２の半導体素子チ
ップ２とはそれぞれ特性のそろった接合型ＦＥＴのチッ
プである。リードフレームは各リードが対向して配信さ
れておシ、半導体累子チップｌと２とをそれぞれ固着す
るゲート電極用リード４と８は互いにつながっている。First semiconductor element chip 1. ! 1: The second semiconductor element chips 2 are junction FET chips with uniform characteristics. The leads of the lead frame are distributed so as to face each other, and the gate electrode leads 4 and 8, which respectively fix the semiconductor chips 1 and 2, are connected to each other.
各半導体素子チップｌと２のソース電極はソース電極用
リード３と７にそれぞれ金属配線で接続されておシ、同
様に各ドレイン電極もドレイン電極用リード６と１０に
それぞれ金属配線で接続されている。ゲート電極用リー
ド４．８とドレイン電極用リード６．１０間は入出力間
を遮蔽するためにシールド端子用り−ド５と９が設けら
れており、これらクールド端子５と９も互いにつながっ
ている。全体は点線で示すように、プラスチック樹脂１
１で封止されている。The source electrodes of each semiconductor element chip l and 2 are connected to source electrode leads 3 and 7 with metal wiring, respectively, and similarly, each drain electrode is connected to drain electrode leads 6 and 10 with metal wiring, respectively. There is. Between the gate electrode lead 4.8 and the drain electrode lead 6.10, shield terminal leads 5 and 9 are provided to shield the input and output, and these cooled terminals 5 and 9 are also connected to each other. There is. As shown by the dotted line, the whole is plastic resin 1
1 is sealed.
この例では、半導体素子チップ１．２の基板がゲートで
あり、素子が取シ付けられたゲート電極用リード４と８
より電気的接続がとられている。In this example, the substrate of the semiconductor element chip 1.2 is the gate, and the gate electrode leads 4 and 8 to which the element is attached.
More electrical connections are made.
従って２つのＦＥＴのゲートは共通となっている。Therefore, the gates of the two FETs are common.
ところで、パッケージの小型化を進めていくと２個の半
導体素子チップを平面的に並べていたのではパッケージ
の外形の小型化に制約を及ぼすことになる。従って、よ
フ小型化への方策が望まれるところである。By the way, as the size of packages progresses, arranging two semiconductor element chips in a two-dimensional manner will impose restrictions on the size reduction of the package. Therefore, measures for further miniaturization are desired.
本発明はこの様なマルチテップ型半導体装置の小型化へ
の手段を提供するものである。The present invention provides a means for downsizing such multi-step semiconductor devices.
すなわち、半導体素子チップを固着すべき、リードフレ
ームの両面をこれにあてるもので、リードフ１／−ムの
表面に第１の半導体素子チップを固着し、同じリードフ
レームの裏面に第２の半導体素子チップを固着すること
を特徴とした半導体装置を提供するものである。That is, both sides of the lead frame to which the semiconductor element chip is to be fixed are applied to this, and the first semiconductor element chip is fixed to the front surface of the lead frame 1/-, and the second semiconductor element chip is attached to the back surface of the same lead frame. The present invention provides a semiconductor device characterized by fixing a chip.
次に本発明を図面を用いてより詳細に説明する。Next, the present invention will be explained in more detail using the drawings.
第２図は本発明の一実施例を示すものでリードフ１／−
ムの表面よシ見た上面図で、リードフ１／−ムに第１の
半導体素子テップ【を固着しボンディングワイヤーで結
線した状態である。リードフレームは、従来同様リード
が互いに対向するように配置されており、そのうち第１
の半導体素子チップ【を固着するゲート電極用リード４
と８はつながっている。またゲート電極用リード４，８
とドレイン電極用リード６．１０間に配置されこれらの
開音遮蔽する／−ルド端子用リード５，９も互いにつな
がっている。第１の半導体素子ブーラグｌのソースおよ
びド１／イン１ｔｌ極はそれぞｉＬンソー電極用リード
３およびト１／イン電極用リード６に金桝配線により接
続されている。FIG. 2 shows an embodiment of the present invention.
This is a top view seen from the surface of the film, showing a state in which the first semiconductor element tip is fixed to the lead frame 1/- and connected with a bonding wire. The lead frame is arranged so that the leads face each other as in the conventional case, and the first
Gate electrode lead 4 for fixing the semiconductor element chip
and 8 are connected. Also, gate electrode leads 4 and 8
The /- lead terminal leads 5 and 9 which are arranged between the and the drain electrode leads 6 and 10 and which shield these open noises are also connected to each other. The source and do1/in1tl poles of the first semiconductor element Boolag l are connected to the iL source electrode lead 3 and the to1/in electrode lead 6 by metal wires, respectively.
第３図は第２図の実施例の下面図であり、リードフレー
ムの裏面より見た図である。第２の半導体素子テップ２
はゲート電極用リード４．８の第１の半導体素子チップ
ｌが固着された部分の裏面に固着されている。この第２
の半導体素子テップ２のソースおよびドレイン電極はそ
れぞれソース電極用リード７およびドレイン電極用リー
ド１０に金属配線により接続されている。各半導体素子
テップｌと２と各金属配線とは点線で示すごとく。FIG. 3 is a bottom view of the embodiment of FIG. 2, viewed from the back side of the lead frame. Second semiconductor element step 2
is fixed to the back surface of the portion of the gate electrode lead 4.8 to which the first semiconductor element chip l is fixed. This second
The source and drain electrodes of the semiconductor element TEP 2 are connected to a source electrode lead 7 and a drain electrode lead 10, respectively, by metal wiring. Each semiconductor element step 1 and 2 and each metal wiring are shown by dotted lines.
モールド樹脂ｉｔで封止されている。It is sealed with mold resin IT.
第４図は第２図および第３図に示した実施例の断面図を
示す。すなわち、リードフレームの１つのリードの表面
に第１の半導体素子テップ１が固着されており、その反
対側裏面に第２の半導体素子テップ２が固着されている
。FIG. 4 shows a cross-sectional view of the embodiment shown in FIGS. 2 and 3. That is, a first semiconductor element tip 1 is fixed to the front surface of one lead of the lead frame, and a second semiconductor element tip 2 is fixed to the opposite back surface.
本実施例では、マツチドデュアルＦＥＴと云われるバラ
ンスドミキザーに用いられるように特性のそろった２ケ
のＦＥＴチップを第１および第２の半導体素子チップ１
，２°として用い、これらを１つのパッケージに入れた
例について説明した。In this embodiment, two FET chips called mated dual FETs, which have the same characteristics and are used in a balanced mixer, are placed in the first and second semiconductor element chips 1.
, 2°, and an example in which these are packaged in one package has been described.
この様に、本発明によれは、リードフレーム上の半導体
素子テップを固着すべき領域はその面積が１つの半導体
素子テップを固着するのに必要な面積だけで良く、その
分パッケージの小型化が可能となる。As described above, according to the present invention, the area on the lead frame to which the semiconductor element tip is to be fixed is only required to have an area necessary for fixing one semiconductor element tip, and the package can be made smaller accordingly. It becomes possible.
又、複数の半導体素子テップ１と２とがリードフレーム
の表面及び裏面に固着されている為、ワイヤボンディン
グは結果的に立体接続されることになり、平面配置では
不可能であったワイヤの交差も表面、裏面を使い分ける
ことにより可能となる。In addition, since the plurality of semiconductor elements 1 and 2 are fixed to the front and back surfaces of the lead frame, wire bonding results in three-dimensional connection, which allows wires to cross, which is impossible with a planar arrangement. This is also possible by using the front and back sides separately.
又、リードフレームの表面の第１の半導体素子チップｌ
と裏面の第２の半導体素子テップ２とはリードフレーム
材一枚を介して接しているので熱的環境ははは同等と考
えられる。すなわち、２つの半導体素子テップ間で熱バ
ランスが問題となる様な装置では非常に有効な手段であ
る。Also, the first semiconductor element chip l on the surface of the lead frame
Since they are in contact with the second semiconductor element TEP 2 on the back side through a single lead frame material, their thermal environments are considered to be the same. In other words, this is a very effective means for devices where heat balance is a problem between two semiconductor chips.
以上説明した様に、本発明によれはマルチテップ型半導
体装置の小型化の方法として有力な手段を提供するもの
である。As explained above, the present invention provides an effective method for downsizing a multi-step semiconductor device.
第１図は従来のマルチチップ型半導体装僧を示す平面図
である。
第２図は本発明による一実施例を示す上面図、第３図は
その下面図、第４図はその断面図である。
ｌ・・・・・・第１の半導体素子チップ、２・・・・・
・第２の半導体素子チップ、３．７・・・・・・ソース
■、極用り−ド％ ４．８・・・・・・ゲート電極用リ
ード、 ５．９・・・・・・シールド端子用リード％
６，１０・・・・・・ド１ツイン電極月ｐノード、 １
１・・・・・・モールド位刊旨。
代理人 弁理士 内 原 迎 ・ ・。
日：、ｊFIG. 1 is a plan view showing a conventional multi-chip semiconductor device. FIG. 2 is a top view showing an embodiment of the present invention, FIG. 3 is a bottom view thereof, and FIG. 4 is a sectional view thereof. l...First semiconductor element chip, 2...
・Second semiconductor element chip, 3.7... Source ■, pole lead % 4.8... Lead for gate electrode, 5.9... Shield Terminal lead%
6, 10... de 1 twin electrode month p node, 1
1...Mold publication status. Agent: Patent attorney Masayuki Uchihara.日：、j
Claims (1)
半導体装置において、リードフレームの表面に第１の半
導体素子チップを固着し、該リードフレームの裏面に第
２の半導体素子チップを固着したことを４？徴とする半
導体装置。In a semiconductor device including two or more semiconductor element chips in one package, a first semiconductor element chip is fixed to the front surface of a lead frame, and a second semiconductor element chip is fixed to the back surface of the lead frame. ? Semiconductor device with special characteristics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58145930A JPS6037758A (en) | 1983-08-10 | 1983-08-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58145930A JPS6037758A (en) | 1983-08-10 | 1983-08-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6037758A true JPS6037758A (en) | 1985-02-27 |
Family
ID=15396362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58145930A Pending JPS6037758A (en) | 1983-08-10 | 1983-08-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6037758A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62109333A (en) * | 1985-11-04 | 1987-05-20 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Semiconductor package |
| US4862322A (en) * | 1988-05-02 | 1989-08-29 | Bickford Harry R | Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween |
-
1983
- 1983-08-10 JP JP58145930A patent/JPS6037758A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62109333A (en) * | 1985-11-04 | 1987-05-20 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Semiconductor package |
| US4862322A (en) * | 1988-05-02 | 1989-08-29 | Bickford Harry R | Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween |
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