JPS6037637Y2 - signal processing circuit - Google Patents

Description

[Detailed description of the invention] The present invention proposes a signal processing circuit that determines whether multiple signals input simultaneously are necessary or not by using their level change status, and enables only the necessary signals. It is something.

Data input systems that use holograms for data recording are known.

This involves passing a hologram between the emitter and receiver to obtain a reproduced image of the hologram pattern, converting the optical information from this reproduced image into an electrical signal at the receiver, and reproducing and reading the recorded data from this electrical signal. This is how it was done.

Problems with the electrical signal processing system in this conventional data input system will be explained below.

One digit of data recorded as a hologram pattern has, for example, a 5-bit structure, and in order to correspond to this, as shown in FIG. 3, a photoelectric sensor S is used as the light receiver.

, S□? S2. sat s7 are arranged so that their centers are aligned with 5 adjacent positions of m equally spaced positions on a predetermined circumference, that is, 5 positions on a semicircle, and the reproduced image is
The data is recorded in such a manner that two out of the five sensors are in the light receiving state.

That is, when the data content is r4J, as shown by solid hatching in FIG. 3, the sensor S enters the light receiving state to represent this, and the sensor S also receives a signal as a parity pit.

is in a light receiving state.

By the way, when such a reconstructed image is obtained, five sensors S are used.

~The center O of the circumference where the center of S7 is located, and the sensor S.

(or the image formed on it) and the center of the sensor S, (or the image formed on it). A sensor S corresponding to

? A noise image (indicated by dashed hatching) having the same diameter as the image of Sa is formed.

Since this noise image is focused at a position close to the sensor S1 or S2 as shown in the figure, the sensor S or S2 outputs electrical noise according to the distance from the noise image and other optical conditions.

And sensor S. The -87 output signal is input to a comparator with a predetermined threshold level set, and is binarized by comparing it with this threshold level, so the level of the sensor output due to the noise image, In other words, if the level of the noise signal is low and you do not want it to be detected as an unnecessary signal, there will be no problem, but if the level of the noise signal becomes high due to poor optical system accuracy, aging of the hologram card, etc. , this level exceeds the threshold level, causing troubles such as data misreading and unreadability.

Figure 4 shows sensor S.

It is a schematic diagram of an electronic circuit connected to ~S7.

Sensor S. , S□, s2. s4. The outputs of s7 are applied to the negative input terminals of comparators 40, 41, 42, 44, and 47, respectively, and the outputs of these comparators are applied to the BCD converter 5 and parity check circuit 6. It is.

4-bit output H of BCD converter 5, H2, H4, H
8 is taken in as read data to a circuit section not shown, and the output HC of the parity check circuit 6 is input to the number of digits check circuit 7.

Now, in the state shown in FIG. 3, when the output level due to the noise image of the sensor S1 is relatively high, the output may exceed the threshold level as shown at the beginning of FIG.

That is, FIG. 5A to 5Y are timing charts showing each signal at this time, and FIG.

. s,, s2. The output signals of s, , s7 are shown, and the desired value levels set in the comparators 40, 41, 42, 44, and 47 are also shown by broken lines.

Since the hologram can be moved between the emitter and receiver,
Each signal has a shape like a half-wave of a sine wave, but in this case, the signal that originally needs to be detected, that is, the sensor S.

, S, is naturally much higher than the threshold level.

And sensor S. The output signal level of sensor S is higher than that of sensor S, and the level of the output signal of sensor S is slightly higher than the threshold level, and the level of the output signal of sensor S2 is lower than the threshold level. shall be taken as a thing.

Note that the output of the sensor S7 remains at the atmospheric level.

Now, in such a case, the comparators 40, 41, 42,
44, 47 output H3o, H3□.

H32, H51, and H57 are shown in Figure 5, respectively.

The state shown in Figure 2 is reached.

That is, H32 and H37 remain at low level, and H3o
, H51, and H54 are all sensors S.

, S□, and S4 are pulse signals that become high level only while the levels of the output signals exceed the threshold level.

The BCD converter 5 receives H3, which is a bit input representing m□J.
While only o is at high level, its 4-bit output H1
, H2, H4? Both H8 are at low level, but H3, which is the bit input representing H3o and 4J,
When 4 becomes high level, the output H1 of the bit divided by r4 from the rising timing of H3 becomes high level.

Then, while H3□, which is the bit input representing 1L, also became high level, 11. The output H□ of the bit divided into is also set to high level, and in short, data representing 15 yo is output.

And after H3 engineering falls to low level, H4 again
After returning to the state where only H3 is set to high level, and H3 falls to low level, H3 is also set to low level.

H3o to H37 are also input to the parity check circuit 6, but this parity check circuit 6 outputs a check signal HC that becomes high level only when two of the input 5-bit data are at high level. This is input into the digit number check circuit 7.

The number of digits check circuit 7 checks the number of digits of data consisting of 5 bits per digit based on the number of pulses of the check signal HC, that is, the check signal H.
The number of times C becomes high level is counted, and it is checked whether or not this matches a predetermined number, for example, the number of digits of data recorded on one hologram card, to determine whether there is an erroneous reading.

When pulse signals H3o-H37 as shown in Figures 5 to 5 are input, H8o and H3, as shown in Figure 5 Y, are input.
The check signal HC is at high level while both are at high level and the others are at low level, but while the pulse appears in H3, the number of pulse signals at high level is 3. Therefore, the check signal temporarily falls to low level.

Therefore, the digit number check circuit 7 counts the originally one digit data as two digits, and treats it as a data error.

Therefore, in order to avoid such a situation, it is necessary to take measures such as using a system with a higher precision optical system or periodically replacing the hologram card with a new one.

The present invention has been made in view of the above circumstances, and the signal input from the sensor has a peak of the necessary signal that is larger than that of the unnecessary signal, as shown in Fig. 5 A to 2. The rising point of the signal is earlier than that of the unnecessary signal, and each signal has a half-sine wave shape. Therefore, the point at which the level of the necessary signal exceeds the threshold level is the unnecessary signal that appears at the same time as the necessary signal. By focusing on the fact that it is faster than that of the comparator output and validating only the required number of comparator outputs that appear earlier and disabling unnecessary signals, data reading accuracy is improved and noise resistance is improved. DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to provide an improved signal processing circuit, the present invention will be described in detail below with reference to the drawings showing embodiments thereof.

FIG. 1 is a block diagram schematically showing the main circuitry of the data input system using a hologram according to the present invention.

Sensor S. , Sl, S2. S. S7 is arranged in the same manner as before, and the respective outputs are connected to comparators 40, 41, 42, 4.
4 and 47 - input terminals,
The other input terminals of the comparators 40 to 47 are also provided with a potential for setting a common threshold level, as in the prior art.

Then, the sensors S are connected to the comparators 40, 41, 42, 44, and 47, respectively.

, S□, S2. S4. The input signal from S7 is binarized by comparing the threshold levels and becomes pulse signals H3o and H3o, respectively.
H8□, H32, H3°H37, these pulse signals are sent to D flip-flops 10, 11, 12, 14, respectively.
, 17, and as the five inputs of the five-power NOR gate 2, and as in the conventional case, if two of the five bits of input are at bi-level, that is, the check result is normal. The parity check circuit 6 generates a check signal HC which becomes bi-level only when the signal is input.

The above check signal HC is for all D flip-flops 10 to 1.
The output X of the NOR gate 2 is applied to each trigger terminal T of all D flip-flops 10 to 17 and the set terminal S of the R-S flip-flop 3, and the output It is designed so that it is applied to the reset terminal R of No. 3.

Each Q output signal HQo, HQ1 . HQ2. HQ4 and HQ7 are input to the conventional five-man BCD converter 5, where they are converted to BCD and output as 4 bits.

H2, H4, and H8 are obtained and taken into a circuit portion (not shown) as read data.

Further, the Q output HC' of the RS flip-flop 3 is inputted to a conventional digit number check circuit 7.

Next, the operation of the circuit of the present invention constructed as described above will be explained as shown in FIG.

, S, and a case where an image corresponding to recording data is formed on one corner of the parallelogram and a noise image is formed on one corner of the parallelogram will be explained based on the timing chart of FIG.

Figure 2 A9, C, 2, and H are sensors S, respectively.

, Sl. S2. S4. The output signal of S7, i.e. the comparator 40
, 41° 42, 44, 47 as input stages of the signal processing circuit of the present invention, in this case sensor S.

, S, is the required signal, and the output signal of sensor S1. The output signal of S2 is an unnecessary signal.

These output signals are sent to comparators 40, 41, 42, 44.4
7, the level is compared with the threshold levels of the comparators 40 to 47 shown by broken lines in FIG.
Pulse signals H3o and H shown in the figure
3□, H32, H34, H37.

Since the output of sensor S7 remains at the atmospheric level, and the peak of the output of sensor S2 is lower than the threshold level,
H37 and H32 remain at low level, while H37 and H32 remain at low level.
Pulses appear at 5o, H31, H3, and these pulses include the H3o pulse rising first, then the H84 pulse rising, finally the pulse H31 rising, and then H3□, H34, and H3o in that order. Each pulse appears to fall.

That is, I to I in FIG. 2 are exactly the same as I to I in FIG. 5, respectively.

Now, after the pulse signal H3o becomes the bi level, the pulse signal H34 becomes the bi level, but when both become the bi level, a parity check is performed with a slight delay from the rise of the pulse of H34, as shown in Figure 2. Check signal HC of circuit 6 becomes bi-level.

The D flip-flops 10 to 17 are set in synchronization with the rising edge of the input to the trigger terminal T when its input terminal is at the bi level and the input to the trigger terminal T becomes the bi level. Since H3o and H34 are already at by-level at the rising edge of the check signal HC input to the D flip-flop 10.14, the D flip-flop 10.14 is set.

On the other hand, in synchronization with the rise of the check signal HC, the R-S flip-flop 3 is also set, and its Q
Output HC' becomes bilevel.

At the time when the flip-flop R-3 flip-flop is set, any of the pulse signals H3o to H37 is at the bi-level, so the output X of the NOR gate 2 is at the low level as shown in FIG. , these flip-flops are prohibited from being set and cannot be immediately reset.

By setting the D flip-flop 10.14, its Q output signal HQO-HQ becomes bi-level as shown in the second figure.

Therefore, the bi-level Q output signal HQO=HQ4 and the low-level Q output signal HQ□=HQ2. As shown in Figure 2, the BCD converter 5 to which HQ7 is input has only the output ratio bi-level, and the other outputs H1, H2, H.
Outputs a 4-bit signal in which bit 8 is low level.

Now, a pulse corresponding to the noise signal output by the sensor S1 will eventually appear in the pulse signal H3□.

Then, with a slight delay from the rise of this pulse, the check signal HC of the parity check circuit 6 changes to low level, but this causes the flip-flops 10 to 17.
3 Furthermore, the BCDCD outputs -1 to H8HC' do not change at all.

Next, when the pulse of H81 disappears, the check signal HC returns to the by level with a slight delay from its falling edge.

At this time, the rise time of the check signal HC is slightly delayed from the fall time of the pulse signal H3, so the rise of the check signal HC causes the D flip-flop 1 to
It is never set to 1.

Therefore, the Q outputs HC' of the BCDCD outputs -1 to H8 flip-flop 3 are not affected by the pulse signal H31.

Then, the check signal HC goes to low level in synchronization with the falling of pulse signal H3, but there is no change due to this. Then, when the pulse signal H3o also goes to low level, all five inputs of NOR date 2 go to low level. Therefore, the output signal X becomes bi-level and the flip-flop 1
Reset 0-17 and 3, HQoy HQ,.

HC' is set to low level.

Along with this, the BCD output also falls to a low level, and the digit number check circuit 7 detects the end of one-digit data.

That is, even though the sensor S□ detected a noise image and output a relatively high level noise signal, the circuit of the present invention was able to correctly read the one-digit data representing 4yo.

Since the proposed circuit is constructed as described above, it can be used even when the noise output, that is, the level of unnecessary signals, is relatively large due to aging of the hologram card or poor precision of the optical system of the data input system. This invention makes it possible to perform highly accurate data reading and signal processing without being affected by this, and the present invention greatly contributes to improving the reliability of this type of system.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, in which Fig. 1 is a block diagram of the proposed circuit, Fig. 2 is a timing chart for explaining its operation, and Fig. 3 is a diagram showing the arrangement position of the sensor and playback. FIG. 4 is a block diagram of a conventional circuit, and FIG. 5 is a timing chart for explaining its operation. SOt S19 S2? S49 S7""" sensor,
2------NOR gate, 3...R-S flip-flop, 5...BCD converter, 6...
...Parity check circuit, 7...Digit number check circuit, 10, 11, 12, 14.17...
・D flip-flop, 40,41°42.44,47
...Comparator.

Claims (1)

[Scope of utility model registration request] When a specific number (multiple) of high-level necessary signals are input, low-level unnecessary signals may be input at the same time, and the input signal is determined by comparing the level of this input signal with a predetermined threshold level. Parity check in a signal processing circuit equipped with means for binarizing a signal and converting it into a pulse signal, in which all three or more signals obtained from the means corresponding to each simultaneously input signal are input. It is equipped with a circuit, a NOR gate, and a D flip-flop which receives each of the three or more signals as data input, outputs an output indicating a normal check result of the parity check circuit, and uses the NOR gate output as a reset input. , A signal processing circuit characterized in that it is configured to obtain the specific number of pulse signals.