JPS6037034A - Multiplying circuit for pipeline formation with mode - Google Patents

Abstract

PURPOSE:To secure the application of a multiplying circuit to the data processing which requires high accuracy by switching in mode the multiplication having high performance and a high accuracy mode, and therefore making use of a fact that the hardware quantity is small together with high performance. CONSTITUTION:When an operation (AXB) is carried out (where A: multiplicand and B: multiplier), A and B are stored to a multiplicand register 10 and a multiplier register 11 respectively. Both the final sum and the final carry are supplied to a result production means 16 via signal lines 1500 and 1501 in a high performance mode and after a prescribed operation. Then the final sum and the final carry are supplied to registers 16-2 and 16-3 in high accuracy mode. The outputs of these registers are supplied to a carry foresighted adder 16-7 via selection circuits 16-5 and 16-6 and added together with the output of a transmission carry producing circuit 16-4. Then 56 bits less than a decimal point are stored to a result register 17 through a signal line 1600. In this mode the carry can be correctly transmitted to secure the multiplication of high accuracy unlike a case where the multiplication of a high performance mode does not transmit carry.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a pipelined multiplication circuit in a data processing device.

[Description of prior art]

Conventionally, this type of pipelined floating-point multiplication circuit, as shown in FIG. A partial product group creation circuit 3 that inputs the multiplier and and creates only the upper Ml + N1 (where Ml is the bit length of the mantissa part and N1 is the value that specifies the multiplier precision) bits of the partial product group of the multiplicand and the multiplier. , this partial product group creation circuit 3
a multi-input carry save adder 4 that adds the outputs of and outputs the final sum and final carry; a final sum register 5 that stores the final sum and final carry; and a final carry register 6.
and this final sum register 5, final carry register 6, 2
It was comprised of a carry look-ahead adder 7 for adding human power, an arithmetic result register 8, and a control circuit 9 for controlling these. For example, the mantissa is 56 bits (Ml)
, in the case of the value 8 (Nl) that specifies the multiplication precision, when the multiplication is performed with a recode multiplier, the 29 decimal points below 64 bits l-(Ml + N1 bits) are truncated, as shown in Figure 2. A partial product is required.

When these 29 multiples are added using the multi-input carry save adder shown in FIG. 3, 27 three-man power adders are required. However, compared to general pipelined multiplication circuits, the bit width of the three-power adder is 66 bits at maximum, and the bit width of the carry look-ahead adder is 64 bits, which is significantly smaller. A significant reduction in the amount of hardware was achieved without degrading the performance of high-speed floating-point multiplication of 1 element/machine cycle.

However, there is a problem with the accuracy of multiplication, and this multiplier is difficult to use for data processing that requires accuracy.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pipelined multiplication circuit that takes advantage of the advantage of realizing high-performance multiplication with a small amount of hardware while also making it possible to use highly accurate data processing.

[Features of the invention]

The present invention provides a pipelined multiplication circuit that multiplies floating-point data by two operators, in which a multiplicand of M (M is the bit length of the mantissa) bits and a multiplier of M bits (K is the high-precision mode multiplication width regulation bit) is used. A part that creates an upper partial product group with the above multiplicand and the above multiplier, and a +N (N is the specified value of multiplication accuracy in high performance mode) bit part in the upper M- of the lower partial product group that focuses on the multiplicand and the lower M- of the multiplier. A product group creation circuit, a multi-input carry save adder that adds the outputs of this partial product group creation circuit and outputs the final sum and final carry, and a multiplier that adds bits from M+N+1 to M0 below the decimal point of the upper partial product group. upper partial product group local clearing means for making the summation output of the partial product group of the part zero, lower partial product group clearing means for making the summation output of the lower partial product group zero, and the output of the carry save adder. The present invention is characterized by comprising a required result creation means for outputting a required operation result by repeatedly multiplying an input M-bit multiplicand by a bit multiplier, and a mode switching means for switching between high-performance mode operation and high-precision mode operation. shall be.

[Explanation based on examples]

FIG. 4 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 5 is a block diagram showing the detailed configuration of the partial product group generation circuit 13, which is a part of FIG. 4, and FIG. 6 is a block diagram showing the detailed configuration of the required result creation means 16, which is a part of FIG. FIG.

The configuration of this device will be explained below based on FIGS. 4, 5, and 6. First, in Figure 4, 10 ha56
This is a multiplicand register that stores the multiplicand of the number of bits (MUM is the bit length of the mantissa). 11 is a multiplier register that stores a 56-bit (M bit) multiplier. 12 is an arithmetic multiplier switching means. Two arithmetic multipliers for the number of multiplications determined by the arithmetic multiplier in the high performance mode and the prescribed bit length of 28 bits (K bits) for the multiplication width in the high precision mode are set as shown in Table 1.

The calculation multiplier selection means selects the high-performance mode calculation multiplier in the high-performance mode, the high-precision mode first calculation multiplier in the high-precision mode, and the high-precision mode second calculation multiplier in the second multiplication. and output it. Setting the lower 28 bits of the multiplier (bits in M-) to zero is equivalent to setting the sum of the lower partial product group of the lower 28 bits (bits in M-) of the multiplicand and the multiplier to zero; This corresponds to partial product group clearing means. 13 is a partial product group creation circuit that creates multiples of the multiplicand and the multiplier. The algorithm for generating multiples of the multiplicand uses the recoding method.

The recoding method is multiplier ax a2 a3 ... a 5
4a55as6 is divided into 29 groups MO to M28 of 3 focuses each with one bit overlapping as shown in Table 2. The weighting of the 3 bits in each set is (-2, ■, 1), which is 3
The magnification is set according to the bit pattern as shown in Table 3, and the partial product 29 corresponding to this 3-bit MO-M2S is
pieces are created.

Table 3 14 shows the upper partial product group of the multiplicand and the upper 28 bits (K bits, t) of the multiplier, from 65 bits below the decimal point (M + high-performance mode multiplication accuracy specification value N (8 bits) + 1 bit) to 8
This is an upper partial product group local clearing means that makes the total output of the 4-bit (bits in M+) part zero. In the high performance mode, this means discards the 64 bits below the decimal point of the lower partial product group and passes the remaining part of the partial product group as is, and in the high precision mode, means to pass the entire partial product group as is. It is. Reference numeral 15 is a multi-input carry save adder that adds 29 outputs from the lower partial product group local clearing means to create a final sum and a final carry.

Reference numeral 16 denotes a required result generating means which inputs the final sum and final carry output of the multi-input carry save adder and outputs the required operation result. Reference numeral 17 is a result register for storing the calculation result. Reference numeral 18 denotes a control circuit that controls processing of the exponent part and the like. 19 is a mode switching means for switching between high performance mode and high precision mode.

Next, the configuration of the partial product group generation circuit 13 shown in FIG. 5 will be explained. Input the multiplicand and the operation multiplier, and input the partial products 13-15 to 13-29 with a bit width of 58 bits corresponding to the upper partial product group of the upper 28 bits of the multiplicand (K bits), and the lower 28 bits of the multiplicand and the operation multiplier. (M-bit)
It corresponds to the 64 bits below the decimal point (M+N bits) of the lower partial product group of the lower partial product group, and the bit width is 1.
0.12.14, . . . , 36 partial products 13-1 to 13-14 are created sequentially.

Next, FIG. 6 is a detailed circuit diagram of the required result generating means 16. 16-1 is a four-person carry save adder.

16-2 and 16-3 are final phase registers and final carry registers for storing the final phase and final carry of the four-manpower carry save adder. The outputs of these registers are shifted 28 bits (K bits) to the four-man carry-save adder 1.
It is returned to the input of 6-1.

16-4 is a propagation carry generation circuit which extracts a propagation carry generated from the final and final carry to be truncated in repeated multiplication. 16-5.16-6 is the final phase and final carry input from the multi-input carry save adder 15, the final phase register 16-2 and the final carry register 1
This is a selection circuit that switches the input from 6-3. 16-
7 is a carry look-ahead adder which inputs the outputs of the selection circuits 16-5 and 16-6 and adds them.

Next, assuming that A is the multiplicand and B is the multiplier, the operation of calculating AXB in the high performance mode and the high precision mode will be described. First, A and B are stored in the multiplicand register 10 and the multiplier register 11, respectively.

In the high performance mode, A passes through the signal line 1000 and is input to the partial product group generation circuit 13. On the other hand, B is the signal line 11
00 and enters the arithmetic switching means 12, where B itself is selected as the arithmetic multiplier, and is connected to the partial product group generating circuit 1 from the signal line 1200.
Sent to 3. The partial product group generation circuit 13 generates 29 partial products Z1 to 229 as shown in FIG. Z
229 from l is inputted to the upper group local clearing means 14 from the signal line 1300, and each partial product from Zls to 229 is rounded down to 64 digits below the decimal point l-(M+N bits) to become Y15 to Y29. Zl to Zl4, Yt
Y211 from s is substantially equivalent to the output of the partial product group generation circuit 3 shown in FIG. 1, and is input to the multi-input carry save adder 15 as shown in FIG. 3 through the signal line 1400 and is added. This results in the final phase S and final carry C. S and C enter the required result generating means 16 via signal lines 1500 and 1501. S and C input into the required result creation means 16
pass through the selection circuits 16-5 and 16-6, enter the carry look-ahead adder 16-7, are added together, and the 56 bits below the decimal point are stored in the result register 17 from the signal line 1600, and are connected to the multiplier in FIG. AXB with the same precision and vector performance
The multiplication of is completed. In high precision mode, if the upper bit of B is B1 and the lower edict bit is B2, then AXBmiAx (B+B2) = A X B 1 + A X B 2, and AX
B requires two repetitions of multiplication (AXBI and AXB2<7). A is input to the partial product group generation circuit 13 via the signal line 1000. B is input to the arithmetic multiplier switching means 12 via the signal line 1100, and first, after one machine cycle of the high precision mode first arithmetic multiplier B1, the high precision mode second arithmetic multiplier B2 is sequentially selected and the partial product is changed from the signal line 1200. It is sent to the group creation circuit 13. First, Zl29 is created from the partial product Z10i of A and B1, and z229 is created from the partial product Z20t of A and B2 with a delay of 1 machine cycle in the same way as in the high performance mode, and is created from the signal line 1300 with a delay of 1 machine cycle. It is sent to the partial product group local clearing means 14. In the upper part product group local clearing means 14, nothing is done from Zlol to Zl29 and from Z201 to Z229, and the signals are sent to the multi-input carry save adder 15 similar to that shown in FIG. 3 via the signal line 1400 with a difference of one machine cycle. entered and Zlo
From l to Zl29, Sl, C1 from Z2oz to Z2
29, the final phase and final carry of S 2 and C2 are created with a shift of one machine cycle. 31, C2 and B2
, C2 enter the required result generating means 16 with a difference of one machine cycle. S□ and 01 sent at the beginning are stored in the final phase register 16-2 and final carry register 16-3<
Both initial values are 0), and the contents are shifted by 28 bits and added by a four-man carry save adder 16-1, and the final phase and final carry are stored in the final phase register 16-2 and final carry register 16-3. Stored. B2 and C2, which are sent with a delay of one machine cycle, enter the final phase and final carry register 16-2, 16-3 in the four-man carry save adder 16-1 in the same way as Sl and C1. The outputs of these registers enter the carry look-ahead adder 16-7 via selection circuits 16-5 and 16-6, are added together with the output of the propagation carry generation circuit 16-4, and 56 bits below the decimal point are added to the signal line. 16
00 is stored in the result register 17, and the AXB operation ends. In this mode, high-precision multiplication is possible because carries can be propagated correctly, whereas multiplication in high-performance mode does not propagate carries.

By switching the multiplication between the high-performance mode and the high-precision mode described so far using a mode switching means, for example, an instruction operand, it is possible to switch between the mixed high-speed and relatively accurate multiplication and the relatively high-speed and high-precision multiplication. Can be executed.

〔Effect of the invention〕

The present invention makes it possible to switch between high-performance mode and high-accuracy mode multiplication using a mode switching means, thereby taking advantage of the advantages of conventional pipelined multiplier circuits, such as high performance with a small amount of hardware, while also having problems with accuracy. This makes it possible to use it for data processing that requires precision.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional pipelined multiplication circuit. FIG. 2 is a detailed block diagram of three parts of the partial product group generation circuit shown in FIG. 1. FIG. 3 is a detailed block diagram of the multi-input carry save adder shown in FIG. 1. FIG. 4 is a block diagram showing the configuration of a circuit according to an embodiment of the present invention. FIG. 5 is a detailed circuit diagram of the partial product group generation circuit 13 of FIG. 4. FIG. 6 is a detailed block diagram of the required result creation means 16 shown in FIG. 4. 1. IO... Multiplicand register, 2.11... Multiplier register, 3.13... Partial product group creation circuit, 4.15.
...Multi-input carry save adder, 5...Final phase register, 6...Final carry register, 7...Carry look ahead adder, 8.17...Result register, 9.1 . . . Control circuit, 12 . . . Operation multiplier selection means, 14 . . . Upper partial product group local clearing means, 16 . . . Required result creation means,
19...Mode switching means. 3rd riU M 4 times +000 +200 Atsushi 5 Figure M 6 Ro

Claims (1)

[Claims] (1) It is inserted between each output side of the multiplicand register and multiplier register of a pipelined multiplication circuit that multiplies floating-point data by hand, and the input side of the result register, and performs high-performance mode operation and high-precision mode operation. a mode switching means for switching a multiplicand of M (where M is the bit length of the mantissa) bits;
The upper M of the upper partial product group of the upper K of the bit multiplier (however, K is the specified bit length of the high-precision mode multiplication width) and the pinto, and the lower partial product group of the above multiplicand and the lower M- bits of the above multiplier
- +N (However, N is the specified value of multiplication accuracy in high performance mode)
a partial product group creation circuit that creates a focused part; a multi-input carry save adder that adds the outputs of this partial product group creation circuit and outputs the final phase and final carry; An upper partial product group local clearing means that sets the summation output of the partial product group of the bit part from M+N+1 to M+ to zero, a lower partial product group clearing means that makes the summation output of the lower partial product group zero, and the above-mentioned carry save addition. By taking the output of the device as input and repeating the multiplication of the M-bit multiplicand by the bit multiplier,
1. A pipelined multiplier circuit with a mode, comprising a required result creation means for outputting a required operation result.