JPS6035855A - Multiple transmission system - Google Patents

Abstract

PURPOSE:To store a point-to-point terminal in a loop network by dividing a frame into a channel for a terminal and a point-to-point terminal and distributing the signal of each channel to each terminal. CONSTITUTION:A multiplexing device 2 and a frame synchronizing device 10 are connected to a main transmission line 1 with a loop shape and a terminal P5 having a loop control function and point-to-point P-P terminals T6 are connected to each device 2 respectively through a loop shaped subtransmission line 3 and a P-P terminal line 4 to constitute a loop net work. The device 10 transmits a frame constituted of a synchronizing pattern 7, a packet multiple channel 8 and a general terminal channel 9 and having fixed length with synchronization TF. Each device 2 distributes a signal from the channel 8 to the terminal P5 through the transmission line 3 and also distributes a signal from the channel to the terminal T6 through the line 4. The device 2 is also provided with a switch separating the transmission line 3 at the fault of the transmission line 3 and constituting a loop, so that the working rate of the system is improved.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a multiplex transmission system, and in particular to a loop network connecting terminals with a loop control function and an India-to-India network.
This relates to a multiplex transmission system that accommodates point terminals.

[Background of the invention]

Conventionally, a loop transmission method (hereinafter referred to as a token) is used in which a special pattern (hereinafter referred to as a token) is sent to a loop-shaped transmission path connecting several vI terminals, and a terminal that acquires this token can send data to the transmission path.・Ring) has been proposed and is being put into practical use. In the above-mentioned Token Ring, since the terminal must perform token control, only packet-type terminals (hereinafter referred to as packet terminals) equipped with a token control function can be connected. However, terminals that do not have a token control function, so-called terminals that are connected from one point to another (hereinafter referred to as P-p terminals)
If K is set so that it can be accommodated in the token ring, an extremely efficient system can be realized.

Conventionally, when accommodating a packet multiplex loop network KP-P terminal, control is performed as follows. First of all,
A frame of a certain length is sent on a transmission path, and the frame is broadly divided into a packet multiplex channel and a channel for P-P terminals. Furthermore, the channel for PP terminals is divided into small channels corresponding to fixed length terminals. Each node connected to the transmission path puts data from the packet end* onto the packet multichannel channel, and puts data from the P-PM end into a small channel corresponding to a predetermined terminal within the P-P terminal channel. This realizes multiplexing functionality.

By providing each seed with a multiplexing function in this manner, it was possible to accommodate packet multiplex network leak KP-P terminals. However, recently, the loop control function for packet multiplexing and net-to-network communication has been integrated into LSIs and is often built into terminals. Such a packet multiplexing network KP with a built-in loop control function terminal
- When accommodating P terminals, the loop control function of each terminal must be modified. However, since the loop control function is integrated into an LSI, modification is an F! It was i away.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned conventional problems, and to make it possible to accommodate P-PM terminals in a loop network with a built-in loop control function terminal without modifying the loop control function of each terminal. To provide a multiplex transmission system that allows
be.

[Summary of the invention]

In order to achieve the above object, the multiplex transmission system of the present invention provides a loop network in which terminals each having a built-in loop control means are connected.
A frame synchronizer that transmits frames at a predetermined period, and divides the seven frames into a channel for loop control terminals and a channel for point F-to-point terminals,
A feature of the present invention is that a multiplexer is provided for distributing the signals of each channel to the loop control terminal and the point-to-point terminal.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of a loop network to which the present invention is applied, and FIG. 2 shows an example of the configuration of array A on the main transmission path in FIG.

In Fig. 1, 1 is the main transmission line, 2 is the multiplexing device, 3 is the sub-transmission line, 6 is the terminal with built-in loop control function [F], 6 is the PP terminal , 10 is a frame synchronizer. Multiplexer 3 and frame synchronizer 10
are connected in a loop by the main transmission path IK. On the main transmission path 1, seven frames shown in FIG. 2 are flowing at a constant interval by a frame synchronizer 10.

As shown in FIG. 2, the frame is composed of a synchronization pattern 7, a packet multiplex channel 8, and a general terminal channel 9. And channel 9 for general terminals is Sara kl131i! It is divided into corresponding small channels 11. The frame synchronizer 10 has a function of transmitting the above frame onto the main transmission line 1 at a constant interval T1.

FIG. 3 shows an example of a plotter configuration of the frame synchronizer 10 shown in FIG. 1.

Initially, the flip flips 19, 20 are in the reset state M
There is K. First, the synchronization pattern generation circuit 24 operates,
The synchronization pattern is transmitted to the main transmission line 1'. At the same time, part of one synchronization pattern is input to the delay circuit 28 as a gate control signal, and the gate 27 is opened after the delay time has elapsed.

When Gate 27 opens! The mark signal from the error generating circuit 26 is transmitted to the main transmission line 1' in accordance with the clock supplied from the tarlock generator 13. Furthermore, when a synchronization pattern is transmitted, the synchronization pattern detection circuit lδ detects it and starts the counter 16, so the counter 1
6 starts Kashin F. The comparator 18 is the counter 16
In order to detect whether the count value has reached a value corresponding to one frame time, the set value and the counter output are constantly compared. When one frame time has elapsed, the comparator 18
Since the detection output is sent from the main transmission line 1', the gate 27 is closed and the mark transmission to the main transmission line 1' is interrupted.

When the first transmitted synchronization pattern goes around the loop once and returns, it is input from the main transmission line 1 to the synchronization pattern detection circuit 12, where the synchronization pattern is detected. When the synchronization pattern detection circuit 12 detects a synchronization pattern, it sets the flip 70 knob 19 and simultaneously reads the data t FIFO (Fir+wt i
n First out )29 Input K. If the synchronization pattern at the beginning of one frame does not come back when one frame has been transmitted on the transmitting side, the 7-rip/7-sync block 19 remains in the reset state, so the 7-rip/7
The trigger 20 also continues in the reset state. When the 7-rip/7-tab 20 is in the reset state, the reset input activates the synchronization pattern generation circuit 24, and the 1-reset output opens the AND gate 25 along with the tarok to activate the mark generation circuit 26. Therefore, the synchronization pattern and mark signal are transmitted in the same way as at the beginning.

If the synchronization pattern at the beginning of the frame has returned, the flip 712 block 19 has been set, so an AND gate is performed between the set output of the 7 rip 70 block 19 and the output of the comparator 18. 21 and 7 lips.
Set 7p knob 20. When the 7-rip prop 20 is set, the AND gate 30 is asked with the set output pin and the PIF029 is activated.
The data is then transmitted from the FIFO 29 to the main transmission path 1'.

Note that when a synchronization pattern is received, the synchronization pattern detection circuit 12 detects this and starts the counter 14, so the counter 14 starts counting. Similar to the comparator 18, the comparator 17 constantly compares the set value and the counter output in order to detect that the count value of the counter 14 has reached a value corresponding to one frame time. When one frame time has elapsed, a detection output is sent from the comparator 17 to reset the flip-flop 19.

When the 7 rip-flop 19 is reset, an AND game 22 is opened between the 9 set output and the output of the comparator 18,
7.Reset the rip flip 20.

By such operation of the 7-frame synchronizer 1O, frames can be sent on the main transmission line 1 at a constant period T.

FIG. 4 shows an example of the configuration of the multiplexer 2 of the 1st 15A.

The multiplexing device 2 is set at each node position on the loop-shaped main transmission path 1, and has the following functions.

Among the frames flowing through the middle main transmission path 1, a function of sending a packet multichannel signal to the subtransmission path 3; (l) a function of putting the signal from the subtransmission path 3 on the packet multichannel;
IlψP, a function to send data of the unsupported small channel (channel corresponding to the PP terminal connected to the multiplexer 2) to the PP terminal 6 at the end of the channel for the PP terminal in the @ frame
- It has a function of putting the data of PMMo2 etc. on the corresponding end unsupported small channel, and a function of adjusting the sending rate between the M main transmission line 1, the sub transmission line 3, and the PP terminal @line daytime.

First, the above (1) and (it)K will be described.

The clock extraction circuit 34 extracts a clock from the signal on the main transmission line 1. This clock is the basic clock for the operation of the multiplexer 2.

When the synchronization detection circuit 31 detects a synchronization pattern from the signal on the main transmission line 1, the flip-flop 36 is activated. While the 7-rip flip 36 is set, the AND gate 37 opens at the set output and supplies the tarot to the FIFO 47°48, so the signal on the main transmission path 1 is input to the PIF048, and
signal is sent to main transmission path 1/. When the switch 49 is on, the signal of the PIFO 48 flows to the sub-transmission line 3 at the transmission speed of the sub-transmission line 3, and then enters the PIF 047 after a cycle.

Further, when the switch 49 is off, the signal does not go through the sub-transmission path 3 and directly enters the PIF04γ. The switch 49 is turned off when there is a failure in the subtransmission line 3 or when the power of the packet terminal is turned off. In addition, the obstacles are:
By monitoring the timing signal on the sub-transmission line 3,
Or detected by other methods.

By providing the switch 49, the loop network can be connected to the multiplexer 2,
This is an important point in terms of composition.

When the counter 35 counts the length of the packet multiplexing channel based on the clock from the clock extraction circuit 34, it outputs a control signal to the flip-flop 36 to reset it. When the flip-flop 36 is reset, the main transmission line side clock signal is not supplied to the FIFOs 4'r and 48, so that the main transmission line 1. ]/
,! =Transmission and reception of signals between FIFO 47 and 48 is stopped. Note that the clock on the sub-transmission line side is always connected to frequency divider 4.
It is supplied from 2.

The signal output from the FIFO 47 is sent to the main transmission line 1/, but then the synchronization pattern created by the synchronization pattern generation circuit 32 when synchronization of the input signal is detected is first sent out, and immediately after that, the signal is sent from the FIFO 47 to the main transmission line 1/. The delay circuit 33 adjusts so that the signal is sent out. The delay circuit 33 is adjusted by the clock from the clock extraction circuit 34.

Next, the functions of (iiD and (IV)) above will be described.

The channel register 39 contains the number of the small channel used by the P-P terminal 6 connected to the multiplexer 2. On the other hand, as described above, the counter 35 counts the length of the packet multiplexing channel 8, resets the 7-lip-flop 36, and then counts the corresponding small channel in the PP terminal channel. The count value is output to the comparator 40. The comparator 40 compares the count value of the counter 35 and the value of the channel register 39, and compares the count value of the counter 35 with the value of the channel register 39, and compares the value of the main transmission line 1. When it is detected that the channel is flowing, gates 44 and 43 are opened.

When gate 44 is opened, the signal on main transmission line 1 is input to buffer 46 . The signal in the buffer 46 is sent to the general terminal 6 through the P-P terminal circuit [4. P-P terminal 6
The signals are input to the bus 45 through the line 4, and sent to the main transmission line 1' when the gate 43 is open. Since 43 and 44 are opened only when the values of counter 35 and channel register 39 match, this multiplexer! Only the small channel corresponding to the terminal 6 connected to t2 can be accessed. Note that the clock on the PP terminal line 4 side is always supplied from the frequency divider 41.

In this way, by using the frame synchronization device 10 shown in FIG. 3 and the multiplexing device 2 shown in FIG. You can connect without having to do anything.

In the embodiment, a case where the present invention is applied to a packet multiplexing loop network has been described, but the present invention is not limited to packet multiplexing. In other words, the loop control device connected to the sub-transmission path may be of any type that allows any signal to flow through the loop transmission path.

〔Effect of the invention〕

As explained above, according to the present invention, terminals that perform point-to-point communication can be accommodated in a loop network such as a bucket multiplex system, and there is no need to modify conventional equipment. This is extremely effective when the loop control function is built into the terminal and implemented as an LSI. Therefore, if applied to, for example, a packet multiplex loop network, a packet type terminal and a P-P
You can easily configure a loop network that can connect multiple terminals at the same time.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a loop network showing an embodiment of the present invention, FIG. 2 is a configuration diagram of frames flowing on the main transmission path of 1@, and FIG. 3 is a block configuration of the frame synchronization device shown in FIG. 1. FIG. 4 is a block diagram of a plotter of the multiplexing apparatus shown in FIG. 1. II Main transmission line, 2: Multiplexer, 3: Sub transmission line, 4: P
-P terminal line, 5: Terminal with built-in loop control function, 6+ point-to-point connection terminal, 10: Frame synchronizer, 14.16.35 f counter, 17, 18.40
: Comparator, 19,20,36 : Flop/70 knob, 29,47.48 jFIFOS45,46 +
Buffer, 27.43.44 + Gate, 12.15.
31: Synchronization detection circuit, 28.38: Delay circuit. αυ Figure 1

Claims (1)

[Claims] ■In a loop network connecting terminals with built-in loop control means, a 7-relay network that transmits fixed-length frames at predetermined intervals on a loop-shaped main transmission path.
A synchronizer and the frame are divided into the terminal channel and the point-to-point terminal channel, and the signals of each channel are connected to the sub-transmission line to which the loop control terminal is connected and the point-to-point F connection terminal. A multiplex transmission system characterized by providing a multiplexing device for distributing data to sub-transmission lines to which it is connected. 2. The multiplex transmission system according to claim 1, wherein the point-to-point terminal channel of the frame is roughly divided into 1vK sub-channels corresponding to point-to-point terminals. B) The multiplexing device is connected to a loop control terminal via one transmission line, and is provided with a switch for disconnecting the sub-transmission line when there is a failure or the like. The multiplex transmission method described in paragraph 1.