JPS6033763A - Speed selecting communication system - Google Patents

Abstract

PURPOSE:To improve the call processing ability by selecting automatically an idle time slot in matching with a speed selection request from a subscriber terminal device to perform the speed selection communication. CONSTITUTION:A subscriber terminal devices are different in speed and the communication is attained by a changeover circuit 501. A storage memory 321 in a line concentrator multiplexer 505 stores a subscriber line number corresponding to an idle time slot number retrieved by a read-ware 502 for idle time slot retrieval based on request speed type information VC. A data buffer 504 is a buffer memory accessed by a line number memory and applying line concentration multiplex to a line data from a subscriber terminal device 101 and a read output LD is transmitted to a multiplex line. The time slot number assigned to each terminal device is informed to an exchange station by using a control channel CH for call processing.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a speed selective communication system, and more specifically, the present invention relates to a speed selective communication system, and more specifically, a method for accommodating different speed data terminals in a time division multiplexing device or a time division switching center to perform data communication. In this data communication system, when a data terminal makes a speed selection request to the switching center, the switching center automatically selects an available time slot that matches the requested speed band on the time division multiplex line. The present invention relates to a system that enables data communication at a required communication speed.

[Prior art]

Conventionally, in multiplex transmission lines and subscriber lines between multiplexing devices or stations, the speed type of data terminals is assigned as follows.
I couldn't make a fixed decision. Therefore, when not only the traffic demand but also the distribution of terminal speeds fluctuates temporally and geographically, the network side has the disadvantage that it cannot flexibly deal with the traffic fluctuations. Conventionally, terminals with various speeds have been accommodated in multiplexed channel positions fixedly determined by each speed, as shown in FIG. In FIG. 1, the data and control line information sent from the terminal 101 are processed by the in-home line terminating device 102 into an envelope (normally, for 6 or 8 bits of data, an F bit for synchronization, a state At the same time, it is assembled into a bipolar signal that matches the subscriber line signal level.
It is sent to the subscriber line 103. In addition, the in-home line termination device 1
02 also performs reverse conversion of the data from the subscriber line 103 and sends it to the terminal 101.

The bipolar signal on subscriber line 103 is converted into a unipolar signal by in-office line termination device 104, and the unipolar signal is multiplexed by multiplexer 105. The output of the multiplexing device 105 is connected to an intra-office line termination device 107 connected to an exchange 108 using a multiplexing line 106. Different types of in-home line termination equipment 102 and in-office line termination equipment 104 are installed for each speed type of terminals to be accommodated, and when a subscriber has multiple input/output devices with different speeds, the type correspondingly, each device 102.1
It was necessary to install 04 on the network side for each speed.

FIG. 2 is a diagram showing a conventional switching principle using a time division switch on the switching center side. On the input highway 201, the write operation of the information Di and Dj carried by the time slits t1 and tj is performed by selecting the address specified by the time slot counter 203, which operates in synchronization with the clock phase of the input highway 201, by the selector 204, and This is done by using this to access the address in the data buffer memory 205. On the other hand, for a read operation, the holding memory 202 accessed by the time slot counter 207 that operates in synchronization with the clock phase of the output highway 206 is selected by the selector 204, and the data buffer memory specified by the holding memory 202 is The data is read from the address on 205 to the output highway 206. An exchange operation can be realized by these series of write and read operations. In the system shown in FIG. 2, the incremented address of the time slot counter 203 or the address of the holding memory 202 has a one-to-one correspondence with the accommodation position of the subscriber terminal multiplexed on the incoming highway 201. The data transmission speed of each subscriber's terminal is 2 times, 4 times, or 20 times that of the basic call (low-speed bearer rate),
As the terminal becomes faster, 2x, 4x, and 20x address areas are fixedly reserved as addresses on the holding memory 202, and a method is adopted that can cope with changes in terminal speed. It wasn't. Considering that in the future, the speed will be frequently changed from each subscriber terminal, a problem has arisen that the conventional switching system will not be able to deal with.

[Purpose of the invention]

An object of the present invention is to deal with such conventional problems by automatically selecting an available time slot that matches the requested speed band in response to a speed selection request from a subscriber terminal, and performing speed selection communication. An object of the present invention is to provide a speed selective communication system that can realize flexible communication formats.

[Summary of the invention]

The speed selection communication system of the present invention is a system in which data from data terminals having a plurality of speed types is assembled into frames and transmitted by time division multiplexing. The feature is that the communication is performed according to the requested speed by selecting an available channel on the time division multiplex line that corresponds to the speed of the specified information.

[Embodiments of the invention]

FIG. 3 is a flowchart of a speed selection algorithm showing an embodiment of the invention, and FIG. 4 is a block diagram of a speed selection control section showing an embodiment of the invention.

When a speed type request is generated from a subscriber terminal, the exchange or concentrator operates according to the flowchart of FIG. 3 in order to automatically select an empty channel for each speed type request.

FIG. 3(a) is an operation flowchart, and FIG. 3(b) is a subscriber table used in FIG. 3(a).

First, when a speed type request is received from a subscriber terminal, it is detected that it is a search for an empty time slot, and the read address of the subscriber table is set to 0 (steps 10 and 1).
1.14). The contents of address 0 in the subscriber table of FIG. 3(b) are read out, and it is determined whether or not it matches the requested speed (steps 15 and 16).

In addition, L at the right end of the daple is low speed (3.2 Kb/s),
M is medium speed (12.8Kb/s), H is high speed (64Kb/s)
s). When it matches the requested speed, the contents read from the subscriber table are shifted sequentially from the left end to "0".
(Step 17; here, "1" at each time slot position is in use, and "0" is vacant).

When "0" is found, the address position X=0 in the subscriber table and the number of shifts y are stored in the register (step 18.22). Next, when the requested speed is low, after calculating and storing the vacant time slot position (x+24y), the corresponding time slot position in the subscriber table is set to "1".
(steps 23.24.27).

In addition, when the requested speed is in the middle, after calculating and storing the empty time slot position (X+24(y+m), the corresponding time slot position is set to "1" (step 23.25).
．． 27, where m=0.3.6, one of the six values of 9 is sequentially selected by a quinary counter).

When the requested speed is high, the empty time slot position (x+24n) is calculated and stored, and then the corresponding time slot position is set to "1" (step 23.26.2
7. Furthermore, the 6 values of n=0, 1, 2...19 are 20
(selected sequentially by a forward counter).

If the corresponding time slot position is set to “1”, (C)
After that, the process returns to step 11 again.

Note that if the speed does not match the requested speed in step 16, or if "0" cannot be found in step 18 (that is, all "1"s), the process proceeds to step 19 via (A), and the read address of the subscriber table is is incremented by +1, and unless the address table read address exceeds 23, return to step 15 and read out the table information (step 1
9.20.15).

However, when the read address exceeds 23, there is no free time slot that matches the requested speed, so a busy state is notified (step 21).

In Figure 4, 24 64 Kb/s channels are multiplexed on a 1,536 Mb/s multiplex transmission path, and within each 64 Kb/s channel, the speed types are homogeneous, that is, only terminal types of the same speed are connected. It is intended to be handled. Reference numeral 301 is a holding memory that stores the empty/occupied state of time slots in each 64 Kb/s channel.
It has a word structure. Each word in holding memory 301 is
Basic bearer rate (low speed bearer rate) is 3.2Kb/
s, 64/5.2=20 (bits) of information,
It is composed of information bits indicating the speed type (2 bits are required when there are three speed types (LMH) as in the example shown in FIGS. 3 and 4).

That is, as shown in FIG. 4, word 0 is "111.
. . 01" Word 1 has "11011" . . . written therein, and these contents are free/occupied information for each channel, with "0" indicating free and "1" indicating in use.

Further, speed type information is written corresponding to each word 0 to 23, where L is a low speed call, M is a medium continuous call, and H is a high speed call.

The holding memory 301 is accessed based on the incremented address information of the 24-ary counter 303 operated by the clock circuit 302, and the output information is stored in the register 3.
It is latched to 04. Note that the counter 303 is set with the vacant time slot search request signal line 305 turned on when a search request is made for a vacant time slot in the requested speed band. If the type information read result does not match the requested speed band, or all channels within the same address (1 channel for high-volume continuous calls, 5 channels for medium-high continuous calls,
When it is detected that the low-speed call channel (20 channels) is in use, the 300 count operation instruction circuit makes adjustments so that it is possible, and when the 0 detection circuit 314 detects 0, the counter Adjust so that the stepping motion of 303 stops. The channel availability/occupancy information latched in the register 304 includes speed type information for each 64 Kb/s channel identified by the decoder 308;
Speed type information V10 based on request from subscriber terminal 101
When the result of decoding 1 by the decoder 307 matches, the signal is input to the shift register 310 in parallel.

Reference numeral 306 is a control line for parallel enable instruction to enable this parallel input. By shifting the shift register 310 to the left one bit at a time using the shift clock 309, the "0" detection path 314 checks whether the time slot corresponding to each address in the holding memory 301 is empty or occupied one bit at a time. “0
``When detection is performed, the information in the quinary counter 311 is latched in the register 313 in the case of a low-speed call, and the value in the 20-decimal counter 312 in the case of a medium-speed call.
The decimal counter 311 and the decimal counter 312 are reset upon parallel input to the shift register 310).

The clock signal line 309 for left shift input to the shift register 310 starts operating when the parallel enable control line 306 of the shift register 310 is turned on, and operates during a time period ( Adjustments are made by the shift time designation circuit 316 so that the operation is performed for 20 channels in the case of low continuous calls, 5 channels in the case of medium continuous calls, and 1 channel in the case of high speed calls. Note that the flip-flop circuit 315 is set when the vacant time slot selection request signal line 305 is turned on, and is reset when "0" is detected.

The information stored in the register 313 is transmitted to the 24x circuit 317.
is added to the adder circuit 318 together with the counter information 303. Information line 3 obtained from this addition result
19 corresponds to an empty time slot number commensurate with the requested speed. Note that it is sufficient to allocate only one free time slot number in the case of low continuous calls, but in the case of medium and high continuous calls, it is necessary to periodically allocate 5.20 empty time slot numbers each. . In order to perform this periodic allocation, the empty time slot number information of 319 is fed back by the repetition number designation circuit 320 given the speed type information 100, and is added to the addition circuit 318 again. For consecutive calls, the periodic allocation described above can be implemented. 321 is a holding memory for holding the line number corresponding to the accommodation position of the terminal or the partner time slot number for time slot conversion during exchange operation, corresponding to the time slot number found as a result of searching for an empty time slot. .

The holding memory 321 accessed by the vacant time slot number information of 319 is accessed by the call processing program.
The line number of the subscriber terminal or the address of the exchange destination is used as the write information, and the information is held in the holding memory 321 until the subscriber terminal issues a disconnection request.

On the other hand, if an empty time slot matching the requested speed band is found in the holding memory 301, the position of the time slot in the holding memory 301 is changed from "0" to "1".
” needs to be rewritten.

For this purpose, the information in the register 313 is fed back to the decoder 324, the exclusive OR of this decoded information and the information in the register 304 is performed, and the result is stored at the address as write information. Additionally, if the subscriber terminal that made the request disconnects, the call processing program rewrites the time slot free/occupied information in the address in the holding memory 301 from "1" to "0". conduct.

FIG. 5 is a diagram illustrating an example of a usage form when the present invention is applied to a line concentrator and multiplexer. It is assumed that the subscriber terminals accommodated in the switching circuit 501 have different speeds, and the switching circuit 5
Assume that the speed is switched by 01 and communication is possible at an arbitrary speed.

As a means for requesting communication at various speeds from the subscriber side, for example, there is a method using the F bit, which is conventionally used when assembling an envelope. As a conventional F-bit pattern, a simple "101010..." pattern was used only for octet synchronization, but this F-bit pattern can be divided into multiple types of patterns for different speeds as shown in Figure 6. By preparing this, it becomes possible to determine the speed type on the concentrator side.

In Figure 6, in the case of low speed request, two “0”s and “1”
3 "1"s are sent alternately, and in the case of medium speed request, 3 "1"s are sent.
For high-speed requests, the last of three “1”s are replaced with “01” and “01”.
In addition, instead of using the F bit, a separate control channel is prepared for each subscriber terminal, and this control channel is used to notify the requested speed type. 50 in the concentrator multiplexer 505 is also possible.
2 is the vacant time slot search leadware described in FIG. 4, and 321 is the leadware 502. is the requested speed type information V
This is a holding memory that stores line numbers of subscribers corresponding to vacant time slot numbers searched based on C. The data buffer 504 is connected to this line number holding memory 32.
1 is a buffer memory for concentrating and multiplexing line data from the subscriber terminal 101;
The read output (line data LD) is sent to the multiplex line 106. In order to perform call processing operations, the switching center is notified of the time slot number assigned to each terminal using the control channel CH. On the other hand, the terminal 503 is a terminal that can independently set the speed change variably, and even in this case, it is possible to allocate time slots according to the requested speed in the same way as in the above-described operation.

FIG. 7 shows an application of the vacant time slot search hardware 502 of the present invention to the switching center side.

In FIG. 7, a free time slot search request (speed band three times that of a basic call) from a terminal that requires three times the bandwidth of a basic call (low continuous call) and information corresponding to the address of the other terminal are shown. , a call route control method is shown assuming that the exchange is notified by using a control channel or the like.

At the exchange, search hardware 502 is used to automatically search for free time slots that match the required speed band (here, ti, ti+α,
The time slot numbers ti+2α, tj, and tj+αtj+2a for the destination terminal correspond. ) An unused address in the data buffer memory 205 is assigned to the corresponding address in the address control holding memory 202 (this is determined by designation by the call processing program or by automatically designating the first address of the searched time slot). ) as α,
Write β.

Through the above operations, the exchange operation can be realized using the information written in the holding memory 202.

In FIG. 7, RQ is a free time slot search request from software, PG is software processing, and T
C is time slot designation information of the exchange partner by the call processing program.

FIG. 8 shows the address control holding memory 20 in FIG.
FIG. 2 is a diagram showing the operation cycle of No. 2;

In FIG. 8, A is a read cycle of a write address to the data buffer memory, B is a read cycle of a read address from the data buffer memory, and C is an exchange partner to the corresponding time slot as a result of searching for an empty time slot. The timeslot write cycle, D, is the software cycle.

Control operations are executed in cycles A to D.

In this way, when a speed change request is made from a subscriber terminal at any time, the hardware is integrated to automatically select an available time slot number that matches the requested speed band. It can be provided at a central office or exchange. Therefore, in the conventional switching system, the speed band is uniquely determined depending on the housing location of the subscriber terminal, but with the above-mentioned hardware, the speed band can be made variable.

〔Effect of the invention〕

As explained above, according to the present invention, in response to a speed selection request from a subscriber terminal, an empty time slot that matches the requested speed band is automatically selected and speed selection communication is performed. It is possible to improve call processing capacity and realize a flexible communication format.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram for accommodating terminals of various speeds, Figure 2 is a diagram of the exchange principle of a conventional time division switch, and Figure 3 is a diagram of the exchange principle of a conventional time division switch.
The figure is a flow chart of an algorithm showing the principle of the present invention, and Figure 4 is a block diagram of a control unit showing an embodiment of the present invention.
FIG. 5 is a diagram showing an example in which the present invention is applied to a line concentrator and multiplexer, FIG. 6 is a diagram showing an example of an F bit pattern, and FIG. 7 is an example in which the present invention is applied to a switching center. 8 is an operation cycle diagram of the address control holding memory in FIG. 7. 101: Terminal, 102: In-house line termination device, 103: Subscriber line, 104: In-office line termination device (for concentrator), 10
5: Multiplexer, 106: Multiplex line, 107: In-office line termination equipment (inside the exchange), 108: Exchange, 201: Incoming highway, 202: Holding memory, 203: Time slot counter (in the clock phase of the incoming highway) 204: selector, 205: data buffer memory, 206: output highway, 2078 time slot counter (synchronized with clock phase of output highway), 300:
Count operation instruction circuit, 301: Holding memory, 302:
Clock circuit, 303: 24-decimal counter, 304: Register, 306: Free time slot selection request signal line, 3
06: Haralel enable instruction control line, 307: Decoder, 308: Decoder, 309: Shift clock, 3
10: Shift register, 311: Quintal counter, 312
: Binary counter, 313: Register, 314: “0”
Detection circuit, 315: Flip-flop, 316: Shift time designation circuit, 317: 24 times circuit, 318: Addition circuit, 319: Assigned time slot number information line, 320
: Repeat count designation circuit, 321 : Holding memory, 322
: Register information, 323: “0” detection signal line, 324:
Decoder, 501: Switching circuit, 502: Hardware for searching for vacant time slots, 503: Variable speed terminal, 5
04: Data buffer, 505: Line concentrator multiplexer.

Claims (1)

[Claims] (1) Accommodates a group of data terminals with multiple speed types,
In a communication system in which data from a group of data terminals is assembled into a frame and transmitted by time division multiplexing, a switching center is provided with a holding memory that stores information indicating the time slot availability and speed type for each channel, When several types of speed selection designation information are detected from the calling terminal, the information is sequentially read from the above-mentioned holding memory, an empty channel corresponding to the speed of the above-mentioned designation information is selected, and the transmission is performed on the time division multiplex line according to the requested speed. A speed-selective communication method that is characterized by performing communication based on