JPS6033544A - Motor-driven camera - Google Patents

Abstract

PURPOSE:To load easily a film in a motor-driven camera with a simple mechanism by setting automatically a single-shot mode whenever the rear cover is open. CONSTITUTION:When the rear cover is opened, an on-off switch turns on and the Q output of an FFDF3 is zero, so neither of DF5 and DF6 is cleared and the output of DF3 is inputted to P terminals of DF5 and DF6 through an OR gate O5 to hold them set. Therefore, an input to an AND gate A9 goes up to 1 and its output is inverted by an inverter N2 and inputted to an AND gate A8. Consequently, the pulse of CC3 by the next release is not accepted by the DF5 and DF6. This state is therefore held and release winding is perforemed only once by turning on a release switch once. Thus, when the rear cover is opened, a single-shot mode is entered regardless of a frame speed mode, and the operability of the camera is improved considerably.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrically driven camera 2 in which a mode is forcibly set in conjunction with opening and closing of a back cover.

Conventionally, this type of device consists of a camera and an electric drive unit that are separate, and the camera is equipped with a lever for manual winding, and when loading film, the electric drive unit is turned off and the winding operation is stopped The film was loaded using a lever, which was very cumbersome. When loading film using an electric drive, the electric drive was set to modera single-shot mode and the film was wound around the spool of the camera. In this case, if the mode was set to continuous shooting mode, the film would be blown off, making it even more difficult to load the film in one go until unnecessary frames were wound. Recently, cameras with a built-in electric drive device have also appeared, and in this type of camera, a lever is not required for manual winding, and film loading must be done electrically, which often causes the aforementioned problems. In order to solve this problem, an electrically driven camera having an auto-loading mechanism has been proposed to facilitate film loading, but the device has the drawbacks of being complicated and expensive. When the camera back is open, regardless of the shooting mode selected, the motorized camera is automatically set to single-shot mode, making it easy to load film with a simple mechanism. This is what we are trying to provide.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an electrically driven camera, where 1 is the electrically driven camera body and 2 is a release button, the first stroke of which turns the photometry switch SWI side, and the second stroke of which turns the release switch 5W2t-ON. A shutter dial 3 inputs shutter speed information to an exposure control circuit (not shown).

Reference numeral 4 denotes a back cover, and opening/closing the back cover operates a switch SWB. Reference numeral 5 indicates a mode selector for switching a frame speed changeover switch (not shown). Reference numerals 6, 7, and 8.9 denote a winding gear train, which is connected to a film winding and camera charging mechanism (not shown) and transmits the output of the motor Mot. 08w1 is an exposure completion switch that is turned on when the shutter operation is completed.

Here, FIG. 2 shows the control circuit of the electrically driven camera shown in FIG. 1, and SW, , 8%, 8%.

SWB is each switch shown in FIG. D.F. ~D
F, is Da Mitsu flip-flop, this flip-flop D
At the input ends of F0 to DF, each of the switches 8wl,
SW, , 8%, SWB resistance Ro -R1
The connection points with lR,,R, are connected. NO is a Noah gate, RO to Tori is an and gate, and Oo to is an or gate. The output of the output terminal Q of the flip-flop DF is input to the AND gate input, and the output of the flip-flop DF is input to the AND gate input.
The output of the output terminal d of , is input to the AND gate A.

Flip flop DF.

The output of the output terminal Q of the output terminal Q is inputted to the antgateon, and the outputs of the output terminals are inputted to the AND gate A. 7
The output of the output terminal Q of the flip-flop DF is inputted to the AND gate AO, A4, and the output of the output terminal Q of the flip-flop DF is inputted to the OR gate 01. The output of the NOR gate NO is added to the AND gate OP. Ii'F0. FF, ,
FF is an SR type flip-flop DF4. DF,
, DF'6 is a D-type flip-flop. Ando) The output of Ao, A is sent to a flip-flop FF via an OR gate 0°.

The output of the analog game 1' AI is input to the reset terminal R of the flip-flop FF. The output of the AND gate A3 is input to the set end S of the flip-flop FF. The output of the AND gate ^, As is applied to the OR gate via the OR gate OI, the output of the AND gate A, is applied to tA, and the output of the AND gate A is applied to the OR gate O! The output of is applied to the reset terminal R of flip-flop FF. The output of the OR gate O1 is applied to the AND gate A, and the output of the AND gate A is input to the set end SK of the flip-flop FFt. The reset terminal R of this flip-flop FF2 has an OR gate 0.
The output of is added. DEC is a decoder, and input terminals A, B, and C of this decoder DEC have flip-flops FFo, FFl, and FF, respectively.

The output of output end Q of is added. flip flop FF
0. The output of FF, , Fl-' is OR gate 04
It is applied to the input end of flip-flop DF4 via . The output of the output terminal Q of this flip-flop DF4 is applied to the input terminal St of the decoder DEC.

The output CCO of the decoder DEC is applied to the ant gate AI, and the output CCI is applied to the AND gate A and to the base of the transistor To via the resistor R1. This transistor T.

A resistor R□ and a release electromagnetic coil ground are connected in series. Dt is a diode connected in parallel to the electromagnetic coil, C8 is the electromagnetic coil and transistor T.
This is a capacitor connected in parallel to the series circuit of O. The output CC of the decoder DEC is applied to the AND gate input and also to the base of the transistor T via the resistor R14. This transistor T is a diode D,
is connected to relay RL, which is connected in parallel.

Mot is a motor, l is a relay contact, and this relay contact l switches from one of the power supply side of the motor Mot and the side of controlling the motor Mot to the other. The output CC of the decoder DEC is applied to the AND gate Ass AJIt A, and the output CC1 is applied to the AND gate input As. COU is a counter, and the CL of this counter COU is
The output CC4 of the decoder]]i':C is input to the yiij child via an inverter N6. This counter CO
Connected to U are resistors t<, R, which are connected in parallel so that 'it(d7.voltage) is applied.

This is a changeover switch that is changed over by the mode selector 5 shown in Fig. 1, and this changeover switch seat M has fixed contacts)], M, L, and S, and these fixed contacts H, M, and L are each connected to a resistor R4*. 1%.

It is connected to the connection point between COU and counter COU.

Further, the end of the resistor &sLt& on the power supply voltage side is connected to the fixed contact S via the resistor R7, and the AND gate A,
is input. The output terminal CR of the counter COU is applied to an AND gate A4 via an inverter N1. The power-up clear circuit consists of a capacitor C0 with a diode D0 connected in parallel, a resistor R8, and an inverter N connected to the connection point thereof. The outputs of are input to the CL terminals of flip-flops DF, DF0, FF0 to FF. Also, inverter N,
The output of is inputted to the P terminal of the flip-flop DF, , DF, via the OR gate OII together with the output from the output wheel Q of the flip-flop I)F.

C8 and R1 are a capacitor and a resistor constituting a differential circuit, and D is a diode connected in parallel to the resistor R1I. The output from the output terminal Q of the flip-flop DF3 is connected to the differentiating circuit and the buffer circuit B. 0 flip-flop DPII, which is input to the flip-flop DF and the CL terminal of DF6 via the output terminal Q of DF6.
The outputs of are input to AND gate A, respectively, and this AND gate A.

The output of NOR gate NO, AND gate A4. Orgate 0. added to. In addition, the output of AND gate A is passed through inverter N, to decoder I) EC's output CC8, and to flip-flop DF through AND gate A.
is input to the CK terminal of . The output of the output terminal Q of the flip-flop DF is applied to the input terminal of the flip-flop DF, and also to the CK terminal of the flip-flop DF. Output terminal Q of flip-flop 1) F
The output of the flip-flop is applied to the input terminal I) and to the AND gate As, and the output of the output terminal Q is applied to the NO gate (NO) and the OR gate On. R9 and R10 are resistors connected in parallel, and an inverter N is connected between them. A capacitor C1 is connected in parallel to the resistor R1, and an inverter N4 is connected between them. These resistances R,,R,
o Capacitor C1t Inverters N, , N form an oscillation circuit. The output of this oscillation circuit is applied to the CK terminals of flip-flops DF0 to DF, FF0 to FF, and the counter.

The frame speed changeover switch SwM is used to change the number of frames per second during quick shooting, and the resistors R4 to R7 are resistors for this information. If you select H mode, the counter COU
Since the preset value of is the lowest, when the count start number 4r3 is input to the CI terminal of COU, the end signal is immediately set to C.
It is output from the R terminal. Further, if the switch SwM selects the L mode, the preset value of the counter COU becomes the highest value, so when a count start signal is input to the CL terminal of COU, a relatively long timer is activated. Switch Sw
If M selects the 8.1 mode, the timer is set to operate for one hour, which is between the ■ mode and the L mode.

Next, the operation of the above configuration will be explained with reference to FIG. Flip-flop DF, ]')F61d will be preset.

When the back cover 4 is closed and the switch SwB is open, the output from the output terminal Q of the flip-flop DF is sent to the differential circuit and buffer circuit B. through flip-flop DF, ,
It is input to the CL terminal of DF6, and the flip-flop DF,
, l) F, is cleared. However, since the time constant of the differentiating circuit is shorter than that of PvC, the flip-flops DFs + DFs are immediately set again.

If release is not done, flip-flop I)
The output terminal Q of Fo, l'')F' outputs 0'', so the output of AND gate A1 also becomes '0'' and does not set the flip-flop FFo.The other flip-flops FF,
, FF are also similar, and the flip-flops FFo~li
"F" remains reset by the PVC signal. Therefore, since decoders D and EC select the CCφ output, they remain in the CCφ state shown in FIG. 3.

When the switches sw, , sw are both turned on by the release operation, the flip-flops DF0. The outputs of the output terminals Q of DFl are respectively 11'', and the AND gate A, whose input is the flip-flop 1) output terminal Q of Fl.
Since the output and decoder l) E C output CCO “
l'' is output, and the output of this AND gate A is input to the set terminal S of the flip-flop FF0 via the OR gate 0°.Therefore, the flip-flop F' lI
'. The output of the output terminal Q becomes 11'', and the decoder DEC
The inputs A-B-C become 1'', ``0'', and ''0'', and the CC1 output is selected this time. This output is connected to the resistor R5,
The transistor T0 is turned on via the transistor T0, thereby driving the camera activation magnet Mg, so that the shutter runs and exposure starts.

When the exposure is completed, the exposure completion switch S w 5 is turned ON, and the output from the output terminal Q of the flip-flop DFt becomes '1'.
'', and the input of the AND gate A3 is input to the set terminal S of the flip-flop FF and set because the output CC1 and the output of the flip-flop DF are both ``1''. Therefore, the input A-B of the decoder DEC -C are 1'' and '1'', respectively.

'0'' and selects CC2 output this time.This output drives relay RL via resistor R14 and connects relay contact l.
Switch Sw5 to connect the motor Mot to the power source, rotate the motor Mot, and wind the film.
Therefore, the output of the output terminal Q of the flip-flop DF becomes "1". The input of AND gate A2 is the output CC2
This is the output of the output end q of the flip-flop DF, and both are @1'', so the output is also 1 and the output of the flip-flop FF.
It is input to reset terminal R of 0 and reset. Therefore, the inputs A, B, and C of Deco and -da DEC are 0'' and 1, respectively.
1".'0", and the decoder DEC selects the CC3 output.

And flip-flop DFa * DFa is PUC
It remains set by the circuit's PUC signal. Therefore, 1'' is added to the inputs of the AND gates A and outputs '1'. This and gate A,
The output of the OR gate is 0. is added to the AND gate A, via. And gate A at this time? When the CC3 output of the decoder DEC is added to the other input of the AND gate A.

The output becomes 1'' and is input to the set end S of the flip-flop FF.As a result, the input A of the decoder DEC
, B, and C are 0 and 1.1, respectively, and the decoder DEC
outputs CC4.

If switch SwM is currently selecting H mode,
When CC4 is output from the decoder DEC, the CC4 output is inputted to the CL terminal of the counter COU via the inverter N6.The counter COU starts counting, but an end signal is immediately output. However, since all the inputs of AND gate A4 are '1'', its output is reset in addition to the flip-flop FF through OR gate 01, and is also input through OR gates 01 and 02. Then reset the flip 70 block FF and input A/B-C of the decoder DEC.
Decision "TO"-"O" data f-1-data DEC selects CCφ output. Here, if the release switch remains in the ON state, continuous shooting is performed in the same manner at the highest frame speed.

Next, if the switch SwM selects the L mode, continuous shooting is performed at the lowest frame speed compared to the above, since the timer of the counter COU is long.

On the other hand, if switch SwM selects S mode,
- After the release winding is completed, the CC4 output state is reached, and the AND gate A connected to one end of the resistor 7
AND gate A4 because the input of 4 remains 70″
``1'' is not output from . Also switch SW
If 1 remains ON, the flip-flop])Q of Fo
Since the output is 0'' and is input to the AND gate A5, 01'' is not output from the AND gate A5. Therefore, the flip-flop (, y R, FF, etc.) is not set and remains in the CC4 output state. However, the switch Swl
If it becomes OF” F, 1” is output from AND gate A5 and the flip-flop F
Flip-flop Fl (
1 is reset, the decoder DEC outputs CCI and returns to its original state.

When the back cover is opened, the switch SWB is turned on, so the output of the output terminal Q of the flip-flop DF is 60'', so the output terminal Q of the flip-flop DF, , DF6 is not cleared, and the output of the output terminal q of the flip-flop DF is 60''. is input to the P terminal of the flip-flop DF, , DF, through the OR gate 0., and the flip-flop DF'w*I
) Leave Fs k set. Therefore, the input of AND gate A0 becomes 11'', and the output of AND gate A is inverted by inverter N and input to AND gate A.

For this reason, the pulse of CC3 caused by the next release will not be accepted by the flip-flops l)F, , ])fi''.Also, since both ORAGENIT 030 inputs are '1', 1'' is input to Antogame 1-A7. , and since the CC3 output is input to the other end, the Andcate A7 outputs 1''. The flip-flop FlI' is set and the inputs A-B-C of the decoder l) E C are l'l.
ON, @N, becomes 111% and outputs CC4. However, since the switch SwB is ON, the Q of the flip-flop DF is 0'' and is input to the AND gate A4, so the output of the AND gate A4 is also lIO''. Further, since the switch Swl remains ON, the Q output of the flip-flop DF is also 0" and is input to the AND gate A5, so the output of the AND gate A5 is also 0". Therefore, since the current state is maintained, only one release/winding is performed when the release switch is turned on once. Next, when the switch Swl is turned off, the Q output of the flip-flop DF0 becomes 1", and the AND gate A5
The inputs are the CC4 output and the output of the output terminal Q of the flip-flop 1) Fo, so both are "1" and its output is also "1".
becomes.

Therefore, the flip-flops FF, , FF are reset, and the inputs A-B-C of the decoder DEC become 0"・1'0
"・锴", and the CCφ output is selected.

The same operation is repeated below. In other words, when the back cover is opened, single shots are taken regardless of the frame speed mode.

When the back cover changes from open to closed, switch SW! 1 is OFF
Therefore, the Q output of the flip-flop DF becomes '1''.On the other hand, the q output of the flip-flop I)F passes through the OR gate 0. to the flip-flop DF.

Since it is input to the P terminal of DF, it is in a state to accept the clock input count. At the same time, the Q output of flip-flop DF is transferred to flip-flop D via a differentiating circuit.
The flip-flops DF, , DF are reset by the differential pulse input to the CL terminal of F, , L)11'. Therefore, the output of AND gate A9 is also lO
” to cancel the inhibition of clock input of A8.

Now, if release switches SWI and SW2 are turned on, 7 lip-flops DF0. The Q outputs of DF and DF are each 1'', and are inputted to the S terminal of flip-flop FIi''0 via AND gate Al and OR gate 0 to set flip-flop FF0. Therefore, the decoder DEC outputs CCI and exposure is started.

When the exposure is completed and the switch SW5 is turned on, the Q output of the flip-flop DF becomes '1' and the
3 to the S terminal of the flip-flop FF, and sets the flip-flop FF. Therefore, decoder I)EC outputs CC2 and winding is started.

When the winding is completed, the switch S w 5 is turned off and the Q output of the flip-flop DF becomes 1. This output is passed through the AND gate A2 to the flip-flop F'
F. The flip-flop F is input to the R terminal of
F0 is reset and decoder DI3C outputs CC3. At this time, the inputs of AND gate A8 are the CC3 output and the output of inverter N2, but the inverter N2 output is 1.
”, one clock is input to the CK terminal of the 7 flip-flop DF, and the flip-flop DF, ,
I) The Q output of F is '1''/0''. The σ output of the flip-flop INF is 1'' and the AND gate A6
Since it is input to the R terminal of the flip-flop FF via the OR gate 02, it is reset. Therefore, the CCI of the decoder DEC is output. Furthermore, if the switches Swl and 8w2 remain in the ON state, release and winding are performed in the same manner as described above.

After the winding is completed, the decoder DEC outputs CC3, but the flip-flop DFa + DFs(7)CK
Since the clock is accepted at the terminal, the Q output becomes '0' and '1' respectively.Flip-flop D Ii'',
The Q output "l" of is inputted to AND gate A through OR gate 03, and AND gate A.

Since the input is a CC3 output, the AND gate A7 outputs '1', which is input to the S terminal of the flip-flop FF, and the flip-flop FF is set.Therefore, the decoder DEC outputs CC4.However, the flip-flop DF, , DI”, OQ output is ’0”/1”
Therefore, the output of AND gate A9 is 0, and since it is input to AND gate A4, the output of AND gate A4 is also θ''.

Furthermore, since the inputs of the AND gate A5 are CC4 and the flip-flop 1) Fo, this state is maintained as long as the switch Swl remains on.

That is, regardless of the mode switch SWM, two frames are shot continuously at the highest speed and then stopped. Next, switch Sw1 is 01i'F
', then the Q output "1" of the 7 flip-flop DFo is input to A5 (and goo), and its output "1" is input to the R terminal of the flip-flop FF via OR gates 01 and 02 to reset it. When the 8-degree release switch is turned on, release and winding are performed in the same manner as described above, and CC3 is output.
The Q outputs of , DF, and DF are both '1'', and the output of AND gate A9 is 1'', and thereafter the flip-flop is 1).
Clock input to the CK terminal of F is prohibited. That is, from now on, the above-mentioned photographing will be performed according to the mode selected by the mode switch SWM.

Also, when the ant gate A0 shown within the dotted line in Fig. 3 is connected, the back cover is closed and the switch SW8
is turned off, the Q of flip-flop DF3
The output becomes 1” and the flip-flop I) Fw s D
F”a is cleared because it is connected to the CL terminal via the differential circuit buffer amplifier Bφ.At the same time, the NOR gate NO
Since the inputs of are both ``0'', ``1'' is output, and the Q output 11'' of the flip-flop DF and the CCO output are input to the AND gate Aφ, so the AND gate Aφ is 11.
This is input to the S terminal of the flip-flop FF through the OR gate 0φ and sets the flip-flop FF0, and the decoder DEC outputs CCI to start exposure and further winding.After this, The decoder DEC outputs CC3, which is input to the CK terminals of the flip-flops DFs and DF through the AND gate A8, and the respective outputs become '1' and 'O'.At this time, as before, the outputs of the flip-flops DF , the mutual output n, I
The decoder DEC outputs CCI to reset the flip-flop FF via 02, and m-release and winding are further performed in the same manner. At this time, decoder I) EC outputs CC3 and flip-flop D
A clock is received at the CK terminal of Ii', DF6, and the output becomes 0'' and 1'', respectively, returning to the CCI state. At this time, since one end of the NOR gate NO is 11", the output is "+" and the output of the AND gate Aφ is "0", which is prohibited. From this point on, the release can be accepted by the switch S w 2. When you close the back cover, the camera automatically skips 2 frames in the highest speed mode and then stops.

As detailed above, according to the present invention, when the back cover is opened, the mode is set to single shot regardless of the frame speed mode, and when the back cover is subsequently closed, the release switch is turned on or the back cover is turned on. A special mechanism is used by configuring the camera so that at the same time as the camera is closed, the 2-frame automatic jump is wound at the highest speed regardless of the frame speed mode, and from then on, shooting is performed according to the mode selected with the mode switch SWM. This makes it easy to load film into an electrically driven camera without having to use the camera.In order to load in single-shot mode, each frame is linked to the finger pressing the release button, so the film can be loaded as desired.

Also, there is no need to go to the trouble of setting the camera to single-shot mode, which greatly improves the operability of the camera.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electrically driven camera showing an embodiment of the present invention, FIG. m2 is a control circuit diagram of the electrically driven camera shown in FIG. 1, and FIG. 3 is a flowchart of FIG. 2. 1... Electrically driven camera body, 4... Back cover, 5...
Mode selector, SW,...photometering switch, S
W,...Release switch, byB...Switch according to opening/closing of the back cover, DF0~DF,...Flip-flop. FF, ~FF, ... flip-flop, DEC...
Decoder, COU...counter, Mot...winding motor. Mg... Electromagnetic coil for release + RL... Relay. l...Relay contact I AO-AI...AND gate, OI~0,...OR gate. Applicant Canon Co., Ltd.

Claims (1)

[Scope of Claims] 0) - An electrically driven camera capable of switching between frame shooting and continuous shooting, characterized in that the camera is set to single frame shooting when the back cover is opened. (2) - In an electrically driven camera that can switch between frame-by-frame shooting and continuous shooting, when the back cover is open, it is set to shoot one frame, and when the back cover is closed, it is set to continuous shooting of the number of frames necessary for blank feed. An electrically driven camera characterized by: