JPS6032201B2 - Pulse width controller - Google Patents

Pulse width controller

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Publication number
JPS6032201B2
JPS6032201B2 JP10999879A JP10999879A JPS6032201B2 JP S6032201 B2 JPS6032201 B2 JP S6032201B2 JP 10999879 A JP10999879 A JP 10999879A JP 10999879 A JP10999879 A JP 10999879A JP S6032201 B2 JPS6032201 B2 JP S6032201B2
Authority
JP
Japan
Prior art keywords
output
pulse width
proportional
controller
com
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10999879A
Other languages
Japanese (ja)
Other versions
JPS5635204A (en
Inventor
正博 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp filed Critical Yokogawa Hokushin Electric Corp
Priority to JP10999879A priority Critical patent/JPS6032201B2/en
Publication of JPS5635204A publication Critical patent/JPS5635204A/en
Publication of JPS6032201B2 publication Critical patent/JPS6032201B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は、PI動作のパルス幅調節計に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PI-operated pulse width controller.

PI動作のパルス幅調節計は電動弁を駆動するに適する
調節計であって、PI動作のアナログ調節計に亀々ポジ
ショナを組合せた構成のものもこの種の調節計の一種と
して慣用されている。
A PI-operated pulse width controller is a controller suitable for driving an electric valve, and a PI-operated analog controller combined with a turtle positioner is also commonly used as a type of this type of controller. .

この方式のパルス幅調節計においては、鰭々ポジショナ
がアナログ調節計の出力と電磁弁の開度に対応する帰還
信号とを比較し、その比較結果により弁モータをオンオ
フ的に駆動するためのパルス幅出力を発生して、アナロ
グ調節計の入力に与えられる制御偏差が小さくなるよう
に電動弁の開度を制御している。ところで従来のPI動
作のパルス幅調節計では、1動作において制御偏差が小
さくなると出力周期が長くなるのが出力のパルス幅は一
定値より小さくならない欠点があり、制御特性のあらさ
細かさを任意に調整することができなかった。本発明は
、1動作における出力のパルス幅を制御偏差に比例させ
るとともに、その比例係数を可変抵抗により任意に調整
できるようにして、上述の如き欠点のない新規なPI動
作のパルス幅調節計を実現したものである。第1図は本
発明パルス幅調節計の一実施例を示す接続図である。
In this type of pulse width controller, the fin positioner compares the output of the analog controller with the feedback signal corresponding to the opening of the solenoid valve, and based on the comparison result, pulses are generated to drive the valve motor in an on-off manner. A width output is generated to control the opening degree of the electric valve so that the control deviation given to the input of the analog controller is reduced. By the way, with conventional PI-operated pulse width controllers, the output cycle becomes longer when the control deviation becomes smaller in one operation, but the drawback is that the output pulse width does not become smaller than a certain value. I couldn't adjust it. The present invention provides a novel PI-operated pulse width controller that does not have the above-mentioned drawbacks by making the output pulse width in one operation proportional to the control deviation and adjusting the proportionality coefficient arbitrarily using a variable resistor. This has been achieved. FIG. 1 is a connection diagram showing an embodiment of the pulse width controller of the present invention.

図において、ACはPI動作のアナログ調節計、POは
轟々ポジショナ、HBはヒステリシス幅設定回路、CV
は操作部で、霞々ポジショナのパルス幅出力によってオ
ンオフ駆動される弁モータと、弁モータにより関度が制
御される電動弁を含んでいる。アナログ調節計ACにお
いて、AEは制御偏差検出回路で、演算増幅器OP,か
らなり、その入力端に測定信号Emと設定信号Esが与
えられ出力端に制御偏差ごを出力する。APは比例増幅
器で、演算増幅器OP2とその出力を分圧帰還するため
の分圧抵抗器RPからなり、入力端に与えられる制御偏
差‘に比例したKpどなる出力電圧を生ずるもので、比
例定数KpはRPによって設定できる。山は比例積分演
算回路で、演算増幅器OP3とその帰還回路に接続され
たコンデンサCIよりなる積分回路を有し、その入力側
に比例増幅器AP出力Kpどが、コンデンサCMを抵抗
RIの並列回路を介して加えられ、出力端にKpごに比
例する電圧とKpどの積分電圧との和に相当する出力電
圧8cを生ずる。雷々ポジショナPOにおいて、ADは
加算器で、演算増幅器OP4からなり、アナログ調節計
ACの出力Ecに電動弁の開度に対応する帰還電圧Ef
を差動的に加算するものである。
In the figure, AC is a PI-operated analog controller, PO is a roaring positioner, HB is a hysteresis width setting circuit, and CV
is an operating section that includes a valve motor that is turned on and off by the pulse width output of the Kasumi positioner, and an electric valve whose relationship is controlled by the valve motor. In the analog controller AC, AE is a control deviation detection circuit consisting of an operational amplifier OP, which receives a measurement signal Em and a setting signal Es at its input terminal, and outputs each control deviation at its output terminal. AP is a proportional amplifier, which consists of an operational amplifier OP2 and a voltage dividing resistor RP for feeding back the output of the operational amplifier OP2, which generates an output voltage of Kp proportional to the control deviation applied to the input terminal, and a proportionality constant Kp. can be set by RP. The mountain is a proportional-integral arithmetic circuit, which has an integrator circuit consisting of an operational amplifier OP3 and a capacitor CI connected to its feedback circuit, and a parallel circuit of the proportional amplifier AP output Kp, capacitor CM, and resistor RI on the input side. The output voltage 8c corresponding to the sum of the voltage proportional to Kp and the integral voltage of Kp is produced at the output terminal. In the thunder positioner PO, AD is an adder consisting of an operational amplifier OP4, which applies a feedback voltage Ef corresponding to the opening degree of the electric valve to the output Ec of the analog controller AC.
is added differentially.

COM−1,COM−2は各々比較器で、COM−1は
抵抗公5・によって正帰還が施された演算増幅器OP5
を有し、加算器ADの出力Edが正極性の範囲において
動作し、COM−2は抵抗R6,によって正帰還が施さ
れた演算増幅器OP6を有し、加算器出力Edが負極性
の範囲において動作する。OP5の入力(十)には加算
器出力Edが抵抗R斑を介して加えられるとともに、一
定電圧−Ehが抵抗R斑を介して加えられており、入力
(一)にはヒステリシス幅設定回路HBより出力Eaが
抵抗R54を介して加えられている。OP6の入力(一
)には加算器出力Edが抵抗R62を介して加えられる
とともに、一定電圧十Ehが抵抗R93を介して加えら
れており、入力(一)にはヒステリシス幅設定回路HB
よりの出力Ebが抵抗R64を介して加えられている。
よってCOM−1は加算器出力Edが増加し上限城値(
=Eh十Ea〉を越えるとオンとなり、出力トランジス
タQ.をオンにし、Edが減少し下限城値L(=Eh)
に達するとオフとなりQ,もオフとなる。またCOM−
2はEdが上限域値一日(=Eh−Eb)に達するとオ
ンとなり、出力トランジスタQ2をオンにし、Edが下
限城値−L(=−Eh)に達するとオフとなりQ2もオ
フになる。すなわちCOM−1のヒステリシス幅はEa
で、COM−2のヒステリシス幅はEbとなる。出力ト
ランジスタQ,,Q2がオンになるとりレーRY,,R
Y2が励磁された接点を閉成する。これら接点の閉成に
よるパルス幅出力で操作部CVの弁モータが正または逆
方向に回転し、電動弁の開度を増加または減少させ、何
れの場合も電動弁は偏差ごを減ずる方向に移動する。V
Fは電動弁の開度に対応する帰還信号Efを発生する回
路で、COM−1,COM−2の出力信号により各々ス
イッチSW,,SW2を駆動し、COM−1,COM−
2のオンオフに同期した正または負のステップ電圧Ep
を生ずる手段と、Epが加わる抵抗RoとコンデンサC
Dの一次遅れ回路よりなっている。COM−1(または
COM一2)がオンになり電動弁の関度が増加(たは減
少)すると、同時に正(または負)のステップ電圧Ep
が一次遅れ回路に加わり、その出力である帰還電圧Ef
は増加(または減少)し、電動弁の関度に対応したもの
となる。この帰還電圧Efは加算器AD‘こアナログ調
節計ACの出力Ecと差動的に加えられる。鎖線で囲ま
れているヒステリシス幅設定回路HBは、演算増幅器O
P7を有している。OP7の入力(一)には偏差ごが抵
抗文7,と可変抵抗R?2の直列回路を介して与えられ
ている。またOP7の入力(一)にはOP7の出力が順
方向接続ダイオードD,と抵抗虫73の直列回路を介し
て加えられるとともに、OP7の出力が逆方向接続のダ
イオードD2と抵抗R74の直列回路を介して加えられ
ている。抵抗R7,とR72の接続点と基準点間に両方
向性ッェナーダィオードZDとスイッチSW3が並列に
接続されている。SW3には比較器COM−1,COM
−2の出力がオアゲートORを介して加えられ、COM
−1,COM−2のいずれか一方がオンのときSW3を
閉成するように構成されている。血は抵抗R7,,R7
2を介してOP7に加わる制御偏差どの最大値(例えば
2V)を制限するためのものである。制御偏差どが負の
とき、ダイオードD,と抵抗R73の接続点から正のヒ
ステリシス幅設定電圧Eaが取り出され、ごが正のとき
ダイオードD2と抵抗R74の接続点から負のヒステリ
シス幅設定電圧Ebが取り出される。EaとEbは、Z
Dのッェナ−電圧をE2Dとする「レーミlご蔓ごE2
。lの範囲では、R73
【11Ea=R席可雨どR74
‘21Eb=R両刀馬どとなり、Ea,E
bは偏差ごに比例し、lど l>IR7,十R72E2
COM-1 and COM-2 are each a comparator, and COM-1 is an operational amplifier OP5 with positive feedback provided by a resistor common 5.
COM-2 has an operational amplifier OP6 to which positive feedback is provided by a resistor R6, and operates in a range in which the output Ed of the adder AD is positive polarity, and COM-2 operates in a range in which the adder output Ed is negative polarity. Operate. The adder output Ed is applied to the input (10) of OP5 via the resistor R, and a constant voltage -Eh is applied via the resistor R, and the input (1) is connected to the hysteresis width setting circuit HB. The output Ea is applied via the resistor R54. The adder output Ed is applied to the input (1) of OP6 via the resistor R62, and a constant voltage 10Eh is applied via the resistor R93, and the hysteresis width setting circuit HB is applied to the input (1) of OP6.
An output Eb from the output terminal is applied via a resistor R64.
Therefore, in COM-1, the adder output Ed increases and the upper limit value (
= Eh + Ea>, it turns on and the output transistor Q. Turn on, Ed decreases and the lower limit value L (=Eh)
When it reaches , it turns off and Q also turns off. Also COM-
2 turns on when Ed reaches the upper limit value (=Eh-Eb), turning on the output transistor Q2, and turns off when Ed reaches the lower limit value -L (=-Eh), and Q2 also turns off. . In other words, the hysteresis width of COM-1 is Ea
Then, the hysteresis width of COM-2 is Eb. The output transistors Q,,Q2 are turned on by relays RY,,R
Y2 closes the energized contact. The valve motor of the operating part CV rotates in the forward or reverse direction by the pulse width output by closing these contacts, increasing or decreasing the opening degree of the motor-operated valve, and in either case, the motor-operated valve moves in the direction to reduce the deviation. do. V
F is a circuit that generates a feedback signal Ef corresponding to the opening degree of the electric valve, and the output signals of COM-1 and COM-2 drive switches SW, SW2, respectively, and
Positive or negative step voltage Ep synchronized with on/off of 2
, a resistor Ro to which Ep is added, and a capacitor C
It consists of a first-order delay circuit of D. When COM-1 (or COM-2) is turned on and the electric valve's relationship increases (or decreases), at the same time a positive (or negative) step voltage Ep
The feedback voltage Ef that is added to the first-order lag circuit and its output is
increases (or decreases), corresponding to the relationship of the electric valve. This feedback voltage Ef is differentially added to the output Ec of the analog controller AC through the adder AD'. The hysteresis width setting circuit HB surrounded by a chain line is connected to the operational amplifier O.
It has P7. The input (1) of OP7 has a resistance value 7 for each deviation and a variable resistance R? It is provided through two series circuits. In addition, the output of OP7 is applied to the input (1) of OP7 via a series circuit of forward-connected diode D and resistor 73, and the output of OP7 is applied to the series circuit of reverse-connected diode D2 and resistor R74. It has been added through. A bidirectional Zener diode ZD and a switch SW3 are connected in parallel between the connection point of the resistors R7 and R72 and a reference point. SW3 has comparators COM-1 and COM
-2 outputs are added through the OR gate OR and COM
SW3 is configured to be closed when either one of -1 and COM-2 is on. Blood is resistance R7,,R7
This is to limit the maximum value (for example 2V) of which control deviation is applied to OP7 via V2. When the control deviation is negative, a positive hysteresis width setting voltage Ea is taken out from the connection point between the diode D and the resistor R73, and when the control deviation is positive, a negative hysteresis width setting voltage Eb is taken out from the connection point between the diode D2 and the resistor R74. is taken out. Ea and Eb are Z
``Remi I Go Tsurungo E2'' where the voltage of D is E2D
. In the l range, R73
[11Ea = R seat available for rain R74
'21Eb=R double sword horse, Ea, E
b is proportional to each deviation, l > IR7, 1R72E2
.

ーの範囲では・R72 Ea=鷺E20 (3’ Eb=鷺E2D t4) となり、Ea, Ebは一定となる。-R72 in the range of - Ea = Heron E20 (3’ Eb = Heron E2D t4) Therefore, Ea and Eb are constant.

このように構成した本発明調節計の動作を以下に説明す
る。
The operation of the controller of the present invention constructed in this way will be explained below.

いま測定信号Emと設定信号Esとの間に制御偏差ご(
ただしどく0とする)が生ずると、アナログ調節計AC
が出力Ecを生ずる。この出力Ecが亀々ポジショナP
Oの加算器ADに加わり、加算器出力Bdが比較器CO
M−1の上限域値日を越すとCOM−1がオンとなり、
それに続くリレーRY,が動作し操作部CVの電動弁を
動かすとともに、正のステップ電圧+Epが発生し電動
弁の関度に対応する帰還電圧Efが指数関数的に増大す
る。EfはACの出力Ecと差動的に加算器ADに加え
られているので、加算器出力Edは減少しその結果Ed
が下限城値Lに達するとCOM−1がオフとなり、それ
に続くリレーRY,も開放され電動弁は停止し、正のス
テップ電圧十Epもなくなり帰還電圧Efの増大も止る
。その後アナログ調節計出力EcがACの積分動作によ
り増大し、加算器出力EdがCOM−1の上限値日を越
えると、COM−1が再びオンとなり電動弁が動き、帰
還電圧Efも増大する。このようにして制御偏差ごが小
さくなるように操作部CVの電動弁がオンオフ駆動され
、第2図に示すようにPI動作を行う。第2図において
、イは加算器ADの出力Edの状態、口はリレーRY,
のオンオフの状態、ハは電動弁の開度の変化を示す線図
であり、時間LIこよる出力が比例P動作を与え、t2
十Wこよる出力が積分1動作を与える。そして積分動作
において、パルス幅信号のオフ時間t2とオン時間t3
はそれぞれ次式で与えられる。
Now, there is a control deviation between the measurement signal Em and the setting signal Es (
However, if this occurs, the analog controller AC
produces an output Ec. This output Ec is Kamame positioner P
The adder output Bd is added to the adder AD of O and the adder output Bd is added to the comparator CO
When the upper limit date of M-1 is exceeded, COM-1 turns on,
The subsequent relay RY operates to move the electric valve of the operating part CV, and a positive step voltage +Ep is generated, and the feedback voltage Ef corresponding to the function of the electric valve increases exponentially. Since Ef is added to the adder AD differentially with the AC output Ec, the adder output Ed decreases, resulting in Ed
When reaches the lower limit value L, COM-1 is turned off, the subsequent relay RY is also opened, the motor-operated valve is stopped, the positive step voltage Ep disappears, and the feedback voltage Ef stops increasing. Thereafter, the analog controller output Ec increases due to the integral action of AC, and when the adder output Ed exceeds the upper limit value of COM-1, COM-1 is turned on again, the electric valve moves, and the feedback voltage Ef also increases. In this way, the electric valve of the operating portion CV is turned on and off so that the control deviation becomes small, and a PI operation is performed as shown in FIG. 2. In Fig. 2, A is the state of the output Ed of the adder AD, and the port is the relay RY,
, and C is a diagram showing changes in the opening degree of the electric valve, and the output due to time LI gives a proportional P operation, and t2
An output of 10 W gives an integral action. In the integration operation, the off time t2 and on time t3 of the pulse width signal
are given by the following equations.

・=c,R,憲 ■ ヒ=C。・=c, R, Ken ■ He=C.

R。昔 ‘6)ただし、農》等毒 一方ヒステリシス幅設定電圧Ea偏差ごがZDを含むリ
ミッタの範囲内(ご≦三青書三E2D)においては■式
に示す如く偏差ごに比例しているので、にC,R,長
のら=C。
R. However, as long as the hysteresis width setting voltage Ea is within the range of the limiter including ZD (≦ Sanseisho 3E2D), it is proportional to each deviation as shown in formula ■. C, R, long
Nora=C.

R。母1ご ■比し、k・=電器; となり、りま一定で、t3は偏差に比例する。R. Mother 1 ■Compare, k = electric appliance; Therefore, the rima is constant and t3 is proportional to the deviation.

なお偏差がど>三青書2E2Dの範囲においてはEaが
一定であるため、らが偏差に反比例し、t3が一定とな
る。また偏差が正の場合でも、ごミ三青書三E2oの範
囲では積分動作は偏差ごに比例する。したがって可変抵
抗K72を調整することにより、積分動作におけるパル
ス幅を第3図に示す特性に加減できる。すなわち、制御
特性をより細く、つまりアナログ調節計の特性を近くご
せたし、ときはR72を大きくする。また操作端CVを
ひんぱんに動かしたくないときはR72を小さくして、
制御特性をあらくすればよい。なお、R花を可変にする
代りにR7,を可変にすれば第4図に示す特性となり、
R7,,R72固定でR73,R74を可変にすれば第
5図に示す特性となる。また、偏差が大きくlごl>三
青書ヱE2Dの範囲ではヒステリシス幅を−定にしてい
るため、ステップ偏差が生じたときただちに比例動作の
出力がある。偏差どの最大値を制限しないと、比例帯大
で偏差が大きい場合には比例動作の出力がただちにでな
い不都合がある。なお、シヱナーダィオードDZの代り
に第6図に示す可変リミッ夕回路を用いると第7図に示
す特性となる。なお上述では、ステップ電圧Epを一次
遅れ回路を介して加算器ADに加える場合を例示したが
、第8図に示すように、出力パルスに同期して生ずるス
テルプ電圧Epを可変抵抗RDを介してPI動作のアナ
ログ調節計ACの積分回路の入力に与え、アナログ調節
計ACにEc−Efなる電圧を得るようにしてもよい。
In addition, since Ea is constant in the range where the deviation is > Sanseisho 2E2D, ra is inversely proportional to the deviation, and t3 is constant. Furthermore, even if the deviation is positive, the integral action is proportional to each deviation within the range of Gomi Sanseisho 3E2o. Therefore, by adjusting the variable resistor K72, the pulse width in the integral operation can be adjusted to the characteristics shown in FIG. In other words, the control characteristics can be narrower, that is, the characteristics of an analog controller can be made close to those of an analog controller, and R72 can be increased. Also, if you do not want to move the control end CV frequently, reduce R72.
All you have to do is roughen the control characteristics. In addition, if R7 is made variable instead of making R flower variable, the characteristics shown in Fig. 4 will be obtained,
If R7, , R72 are fixed and R73, R74 are made variable, the characteristics shown in FIG. 5 will be obtained. In addition, in the range where the deviation is large, the hysteresis width is set to - constant, so that when a step deviation occurs, a proportional operation is immediately output. If the maximum value of the deviation is not limited, there will be an inconvenience that the output of the proportional operation will not be output immediately when the proportional band is large and the deviation is large. Note that if the variable limiter circuit shown in FIG. 6 is used instead of the signer diode DZ, the characteristics shown in FIG. 7 will be obtained. In the above description, the case where the step voltage Ep is applied to the adder AD via the first-order delay circuit is illustrated, but as shown in FIG. 8, the step voltage Ep generated in synchronization with the output pulse is applied via the variable resistor RD. It may be applied to the input of an integrating circuit of a PI-operated analog controller AC to obtain a voltage Ec-Ef at the analog controller AC.

この実施例によれば、前記積分回路が加算器および一次
遅れ回路としても用いられ、加算器ADとコンデンサC
oが不用になり、全体構成を簡単にできる利点がある。
また第8図においては手動操作と自動操作をバンプレス
に切換えることができる。すなわち、手動操作時にはA
/M切換スイッチS^Mを手動側Mに切換え、かつ手動
操作スイッチMS,,MS2を操作して出力パルスを調
節する。このときS^Mにより積分回路のコンデンサC
,に充電されていた電荷を放電させるとともに、コンデ
ンサCMと抵抗R,の並列回路を積分回路から切離し基
準点に接続するようにして、積分回路の入出力を零に保
つように構成されている。したがって、手動操作から自
動操作へ切換えたとき、制御偏差の大きさに関係なく比
較器COM−1,COM−2は共にオフになり、バンプ
レス切換ができる。以上説明したように本発明において
は、制御偏差の絶対値が小さに場合に比較器のヒステリ
シス幅を制御偏差に比例させることによって、積分動作
における出力のパルス幅を偏差に比例させ、かつその比
例係数を可変抵抗により調整可能に構成しているので、
制御特性のあらさ細かさを任意に調整できる新規なPI
動作のパルス幅調節計が得られる。
According to this embodiment, the integration circuit is also used as an adder and a first-order delay circuit, and the adder AD and the capacitor C
This has the advantage that o is not needed and the overall configuration can be simplified.
Further, in FIG. 8, manual operation and automatic operation can be switched bumplessly. In other words, during manual operation, A
Switch the /M changeover switch S^M to the manual side M, and operate the manual operation switches MS, MS2 to adjust the output pulse. At this time, the capacitor C of the integrating circuit is
In addition to discharging the charge stored in , the parallel circuit of capacitor CM and resistor R is disconnected from the integrating circuit and connected to the reference point, so that the input and output of the integrating circuit is kept at zero. . Therefore, when switching from manual operation to automatic operation, both comparators COM-1 and COM-2 are turned off regardless of the magnitude of the control deviation, allowing bumpless switching. As explained above, in the present invention, when the absolute value of the control deviation is small, by making the hysteresis width of the comparator proportional to the control deviation, the pulse width of the output in the integral operation is made proportional to the deviation, and the pulse width of the output in the integral operation is made proportional to the deviation. Since the coefficient is configured to be adjustable using a variable resistor,
A new PI that allows you to arbitrarily adjust the roughness and fineness of control characteristics.
A pulse width controller of operation is obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明調節計の一実施例を示す接続図、第2図
〜第5図はその動作説明図、第6図は本発明に用いるリ
ミッタの他の例を示す接続図、第7図はその動作説明図
、第8図は本発明調節計の他の実施例を示す接続図であ
る。 AC・・・・・・PI動作のアナログ調節計、P0・・
・・・・更々ポジショナ、CV・…・・操作部、HB…
・・・ヒステリシス幅設定回路。 〆/図 〆J図 久4図 〆 Z 図 〆j図 久7図 〆3図 〆8図
FIG. 1 is a connection diagram showing one embodiment of the controller of the present invention, FIGS. 2 to 5 are diagrams explaining its operation, FIG. 6 is a connection diagram showing another example of the limiter used in the present invention, and FIG. The figure is an explanatory diagram of its operation, and FIG. 8 is a connection diagram showing another embodiment of the controller of the present invention. AC: PI-operated analog controller, P0...
...Positioner, CV...Operation unit, HB...
...Hysteresis width setting circuit. 〆/Figure〆〆J Zukyu Figure 4〆〆 Z Figure〆J Zukyu Figure 7〆〆Figure 3〆〆Figure 8

Claims (1)

【特許請求の範囲】[Claims] 1 制御偏差に比例する信号に応答し比例動作出力と積
分動作出力とを加算した出力信号を発生するアナログ調
節計と、操作部の電動弁の開度に対応した帰還信号を前
記アナログ調節計の出力に差動的に加算する手段と、ヒ
ステリシス特性を有する比較器を含みアナログ調節計出
力と帰還信号の差に応じて電動弁の開度を制御するため
のパルス幅出力を生ずる手段と、一定電圧を前記比較器
の出力に応じてオンオフして得たステツプ電圧を一次遅
れ回路を介して取り出し前記電動弁の開度に対応した帰
還信号を発生する手段とを具備するPI動作のパルス幅
調整計において、前記比較器のヒステリシス幅を制御偏
差の絶対値が一定以下のとき制御偏差に比例させ、その
比例係数を可変抵抗により設定する手段を設けたことを
特徴とするパルス幅調節計。
1. An analog controller that responds to a signal proportional to the control deviation and generates an output signal that is the sum of the proportional operation output and the integral operation output, and a feedback signal that corresponds to the opening degree of the electric valve of the operation section to the analog controller. means for differentially adding to the output; means for generating a pulse width output for controlling the opening of the motor-operated valve according to the difference between the analog controller output and the feedback signal; A pulse width adjustment for PI operation, comprising means for extracting a step voltage obtained by turning the voltage on and off according to the output of the comparator through a first-order delay circuit and generating a feedback signal corresponding to the opening degree of the motor-operated valve. 1. A pulse width controller, characterized in that the hysteresis width of the comparator is made proportional to the control deviation when the absolute value of the control deviation is below a certain value, and means is provided for setting the proportionality coefficient by a variable resistor.
JP10999879A 1979-08-29 1979-08-29 Pulse width controller Expired JPS6032201B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10999879A JPS6032201B2 (en) 1979-08-29 1979-08-29 Pulse width controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10999879A JPS6032201B2 (en) 1979-08-29 1979-08-29 Pulse width controller

Publications (2)

Publication Number Publication Date
JPS5635204A JPS5635204A (en) 1981-04-07
JPS6032201B2 true JPS6032201B2 (en) 1985-07-26

Family

ID=14524498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10999879A Expired JPS6032201B2 (en) 1979-08-29 1979-08-29 Pulse width controller

Country Status (1)

Country Link
JP (1) JPS6032201B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158004A (en) * 1984-08-29 1986-03-25 Yazaki Corp Automatic controller

Also Published As

Publication number Publication date
JPS5635204A (en) 1981-04-07

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