JPS6031640A - Random number generator - Google Patents

Random number generator

Info

Publication number
JPS6031640A
JPS6031640A JP58140846A JP14084683A JPS6031640A JP S6031640 A JPS6031640 A JP S6031640A JP 58140846 A JP58140846 A JP 58140846A JP 14084683 A JP14084683 A JP 14084683A JP S6031640 A JPS6031640 A JP S6031640A
Authority
JP
Japan
Prior art keywords
random number
integrated circuit
number generator
dynamic
random numbers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58140846A
Other languages
Japanese (ja)
Inventor
Masashi Nagasawa
長澤 正氏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58140846A priority Critical patent/JPS6031640A/en
Publication of JPS6031640A publication Critical patent/JPS6031640A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • G06F7/588Random number generators, i.e. based on natural stochastic processes

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To simplify the generation of random numbers by coating the surface of a chip with a radioactive substance and accelerating the incidence of particles to a memory cell. CONSTITUTION:Bit patterns on a dynamic MOSRAM integrated circuit chip 1 are irregularly arrayed by alpha particles irradiated by radioactive substance americium 2 coated on the chip 1. The random number can be obtained by reading out a bit pattern generating bit inversion by the incidence of alpha particles stored in the integrated circuit chip 1 through a drawing line 4.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は乱数発生装置、特に、情報処理装置等で使用す
る乱数を発生するための半導体集積回路を用いた乱数発
生装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a random number generator, and more particularly to a random number generator using a semiconductor integrated circuit for generating random numbers used in information processing devices and the like.

〔従来技術〕[Prior art]

従来の乱数発生装置は、情報処理装置等において発生し
て使う乱数を合同法等の算術的操作により、発生するも
ので擬似乱数を用いていた。
Conventional random number generators use pseudo-random numbers, which are generated by an arithmetic operation such as a congruence method, to generate random numbers for use in an information processing device or the like.

したがって、乱数を得るためには、算術的操作を行なわ
なければならないうえに、発生する乱数が擬似乱数であ
るため、使用目的に対して乱数の妥当性を検討しなけれ
ばならなりという欠点があった。
Therefore, in order to obtain random numbers, arithmetic operations must be performed, and since the generated random numbers are pseudo-random numbers, the validity of the random numbers must be considered for the purpose of use. Ta.

また、従来の他の乱数発生装置は、真空管等で発生する
熱雑音をサンプリングして乱数を得る方法が知られてい
るが、アナログ系であるためデジタル系への変換が必要
であり、しかも装置が大きくなるという欠点があった。
In addition, other conventional random number generators are known to obtain random numbers by sampling thermal noise generated by vacuum tubes, etc., but since they are analog systems, conversion to digital systems is required, and the equipment The disadvantage was that it became large.

すなわち、従来の乱数発生装置は、乱数の発生に多大の
71−ドウエアを使用するものであり、乱数の発生が容
易でないという欠点があった。
That is, the conventional random number generator uses a large amount of 71-ware to generate random numbers, and has the disadvantage that it is not easy to generate random numbers.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、乱数を簡便に発生できる乱数発生装置
を提供することにある。
An object of the present invention is to provide a random number generator that can easily generate random numbers.

すなわち、本発明の目的は、乱数を算内的操作によって
発生する代りに乱数を発生する半導体装置を内蔵した乱
数発生装置を提供することにある。
That is, an object of the present invention is to provide a random number generation device incorporating a semiconductor device that generates random numbers instead of generating random numbers by internal operations.

〔発明の構成〕[Structure of the invention]

本発明の乱数発生装置は、読み出されたビットパターン
を記憶するとともに記@されている前記ビットパターン
の任意のビットがα粒子の入射により反転するダイナミ
ックMO8R,AM集積回路チップと、前記ダイナミッ
クMO8RAM集積回路の上に塗布され前記α粒子を発
生する放射性物質とを含んで構成される。
The random number generator of the present invention includes a dynamic MO8R, AM integrated circuit chip that stores a read bit pattern and inverts any bit of the written bit pattern by the incidence of α particles, and the dynamic MO8RAM. and a radioactive substance that is coated on the integrated circuit and generates the α particles.

すなわち、本発明の乱数発生装置は、ダイナミックMO
8RAMのメモリセル容量をα粒子入射により発生する
電荷を容易に捕獲できる容量としたダイナミックMO8
lllAM集積回路とチップ上に塗布された放射性物質
とを含んで構成される。
That is, the random number generator of the present invention has a dynamic M.O.
Dynamic MO8 with 8RAM memory cell capacity that can easily capture the charge generated by α particle incidence.
It is composed of an IllAM integrated circuit and a radioactive material coated on the chip.

〔発明の原理と作用〕[Principle and operation of the invention]

本発明の乱数発生装置は、ダイナミックMO8ftAM
のメモリセル容量を小さくするとα粒子入射によりビッ
ト反転が起こることを利用し、チップの上に放射性物質
を塗布することによ96粒子のメモリセルへの入射を促
すことにより1メモリセル上のビットパターン配列がボ
アノン分布に従って頓次不規刺配列となるので、この状
態を読み出すことにより、乱数を得ることができるとい
う原理にもとづいている。
The random number generator of the present invention is a dynamic MO8ftAM
Taking advantage of the fact that bit inversion occurs due to the incidence of alpha particles when the memory cell capacity is reduced, the bits on one memory cell are It is based on the principle that since the pattern arrangement becomes a random arrangement according to the Boarnon distribution, random numbers can be obtained by reading out this state.

〔実施例の説明〕[Explanation of Examples]

次に5本発明の実施例について、図面を参照して詳細に
説明する。
Next, five embodiments of the present invention will be described in detail with reference to the drawings.

る。Ru.

第1図および第2図に示す乱数発生装置は、ダイナミッ
クMO8RAM集積回路テップlと、その上に塗布され
た放射性物質の1つである アメリジューム2と、パッ
ケージ3と引出線4とを含んでいる。
The random number generator shown in FIGS. 1 and 2 includes a dynamic MO8RAM integrated circuit TEP1, Ameridium 2, which is one of the radioactive substances coated on it, a package 3, and a leader line 4. There is.

この乱数発生装置は通常のダイナミックMOB几AMを
情報処理装置に接続する方法と同様にして接続すること
により、アメリジューム2より照射されるα粒子により
ダイナミックMO8I’LAM集積回路チップ1のビッ
トパターンが不規則に配列され、引出線4を通してダイ
ナミックMO8RAM集積回路チップlに記憶されα粒
子の入射によりビット反転が起ったビットパターンを読
むことにより乱数を得ることができる。
By connecting this random number generator in the same way as connecting a normal dynamic MOB AM to an information processing device, the bit pattern of the dynamic MO8I'LAM integrated circuit chip 1 is changed by the alpha particles irradiated by the Ameridium 2. A random number can be obtained by reading a bit pattern which is irregularly arranged and stored in the dynamic MO8RAM integrated circuit chip l through the leader line 4, and in which bit inversion occurs due to the incidence of α particles.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す斜視図、第2図は第1
図に示す実施例の中央断面図である。 1・・・・・・ダイナミックMO8RAM集積回路チッ
プ、2・・・・・・アメリジューム、3・・・・・・パ
ッケージ、4・・・・・・引出線。 卒1酊 察2侶
FIG. 1 is a perspective view showing one embodiment of the present invention, and FIG. 2 is a perspective view showing one embodiment of the present invention.
FIG. 3 is a central sectional view of the embodiment shown in the figure. 1...Dynamic MO8RAM integrated circuit chip, 2...Ameridium, 3...Package, 4...Leader line. Graduation 1 Drunkenness 2 Companions

Claims (1)

【特許請求の範囲】[Claims] 読み出されたビットパターンを記憶するとともに記B8
れている前記ビットパターンの任意のビットがα粒子の
入射により反転するダイナミックMOS LLAM集積
回路チップと、前記ダイナミックMUSRAM集積回路
の上に塗布され前記α粒子を発生する放射性物質とを含
むことを特徴とする乱数発生装置。
The read bit pattern is stored and recorded in B8.
a dynamic MOS LLAM integrated circuit chip in which any bit of the bit pattern is reversed by the incidence of α particles; and a radioactive substance coated on the dynamic MUSRAM integrated circuit to generate the α particles. Random number generator.
JP58140846A 1983-08-01 1983-08-01 Random number generator Pending JPS6031640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58140846A JPS6031640A (en) 1983-08-01 1983-08-01 Random number generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58140846A JPS6031640A (en) 1983-08-01 1983-08-01 Random number generator

Publications (1)

Publication Number Publication Date
JPS6031640A true JPS6031640A (en) 1985-02-18

Family

ID=15278077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58140846A Pending JPS6031640A (en) 1983-08-01 1983-08-01 Random number generator

Country Status (1)

Country Link
JP (1) JPS6031640A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015156215A1 (en) * 2014-04-08 2015-10-15 株式会社日立製作所 Random number generator, simulation device, and meter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015156215A1 (en) * 2014-04-08 2015-10-15 株式会社日立製作所 Random number generator, simulation device, and meter

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