JPS6031380B2 - facsimile receiving device - Google Patents

facsimile receiving device

Info

Publication number
JPS6031380B2
JPS6031380B2 JP54055981A JP5598179A JPS6031380B2 JP S6031380 B2 JPS6031380 B2 JP S6031380B2 JP 54055981 A JP54055981 A JP 54055981A JP 5598179 A JP5598179 A JP 5598179A JP S6031380 B2 JPS6031380 B2 JP S6031380B2
Authority
JP
Japan
Prior art keywords
signal
circuit
phase
carrier wave
image signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54055981A
Other languages
Japanese (ja)
Other versions
JPS55147876A (en
Inventor
哲朗 前野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic System Solutions Japan Co Ltd
Original Assignee
Matsushita Graphic Communication Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Graphic Communication Systems Inc filed Critical Matsushita Graphic Communication Systems Inc
Priority to JP54055981A priority Critical patent/JPS6031380B2/en
Priority to US06/138,898 priority patent/US4346410A/en
Priority to SE8002826A priority patent/SE446802B/en
Priority to DE3014668A priority patent/DE3014668C2/en
Priority to GB8012590A priority patent/GB2049341B/en
Publication of JPS55147876A publication Critical patent/JPS55147876A/en
Publication of JPS6031380B2 publication Critical patent/JPS6031380B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/00095Systems or arrangements for the transmission of the picture signal

Description

【発明の詳細な説明】 本発明は同期検波により受信信号の復調を行うファクシ
ミリ受信装置に関するもので、特に搬送波を再生する場
合に用いるフェーズ・ロツクド・ループ回路(以下、P
LL回路と略称する)の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile receiving apparatus that demodulates a received signal using synchronous detection, and particularly relates to a facsimile receiving apparatus that demodulates a received signal using synchronous detection.
(abbreviated as LL circuit).

一般に、PLL回路とは、位相比較器、直流変換回路、
電圧保持回路、電圧制御型発振器等を用いて構成され、
ファクシミリ受信装置に入力する画信号の搬送波と同位
相、同周期の搬送波を再生するものである。
Generally, a PLL circuit includes a phase comparator, a DC conversion circuit,
It is constructed using a voltage holding circuit, voltage controlled oscillator, etc.
This reproduces a carrier wave that has the same phase and period as the carrier wave of the image signal input to the facsimile receiving device.

この搬送波の再生動作は、画信号の到着前に完了する必
要があり、さらに、画信号区間中において、回線の影響
による搬送波の変動に対して追随する必要があると同時
に搬送波の存在しない期間において、動作を停止して状
態を保持する必要がある。搬送波の存在しない期間にお
いて、動作を停止して状態を保持するには、電圧保持回
路内のコンデンサの容量を大きくし、これに対処してい
た。
This carrier wave regeneration operation needs to be completed before the image signal arrives, and it is also necessary to follow carrier wave fluctuations due to the influence of the line during the image signal period, and at the same time, during the period when the carrier wave is not present. , it is necessary to stop the operation and hold the state. In order to stop operation and maintain the state during the period when no carrier wave is present, the capacitance of the capacitor in the voltage holding circuit has been increased to cope with this problem.

しかし、電圧保持回路の回路構成によっては、電源を“
ON’したときにランダムな値の電圧がこのコンデンサ
に充電される場合があり、この場合には、このコンデン
サの容量が大きいためにかえってコンデンサに充電され
た電圧を所定の電圧とするまでにPLL回路を長時間動
作させる必要が生じた。しかしながら、従来のファクシ
ミリ受信装置のPLL回路は、前述のごとく画信号到着
前に搬送波と同位相、同周期の信号を再生する必要があ
るため、画信号到着前に送信側から送られて釆て、かつ
、搬送波と同周波数を持つ通信制御信号を用いて行なわ
れていた。
However, depending on the circuit configuration of the voltage holding circuit, the power supply may be
When the capacitor is turned on, a random value of voltage may be charged to this capacitor. It became necessary to operate the circuit for a long time. However, as mentioned above, the PLL circuit of a conventional facsimile receiving device needs to reproduce a signal with the same phase and period as the carrier wave before the image signal arrives. , and a communication control signal having the same frequency as the carrier wave.

通信制御信号とは、回線の確立の確認、送受信状態可能
にあるか否かの確認、相互IDの確認、送受信モードの
通知決定、同期状態の確認、受信終了の確認等、ファク
シミリ通信をシーケンス通りに行うために送受信間でや
りとりする信号である。
Communication control signals are used to control facsimile communication according to the sequence, such as confirming line establishment, confirming whether the transmit/receive state is possible, confirming the mutual ID, determining the transmit/receive mode notification, confirming the synchronization status, and confirming the completion of reception. It is a signal that is exchanged between transmitter and receiver for the purpose of communication.

第1図は、標準的中速ファクシミリ通信と言えるCCI
TT勧告T−30に記載されているところの画信号送出
以前の通信制御信号を示すタイミングチャートである。
第1図より、画信号送出前に送信側からファクシミリ受
信装置に送出されて来る通信制御信号はGC信号と位相
信号である。このGC信号と位相信号は一般的には画信
号の搬送波と同一周波数であるため、この2個の信号を
用いてPLL回路を動作させて、画信号到着前に画信号
の搬送波と同位相、同周期の信号を再生させる。第2図
はGI信号とGC信号との関係を示すタイミングチャー
トである。
Figure 1 shows CCI, which can be called standard medium-speed facsimile communication.
3 is a timing chart showing a communication control signal before sending out an image signal as described in TT Recommendation T-30.
As shown in FIG. 1, the communication control signals sent from the sending side to the facsimile receiving device before sending out the image signal are a GC signal and a phase signal. These GC signals and phase signals generally have the same frequency as the carrier wave of the image signal, so these two signals are used to operate the PLL circuit, so that the GC signal and the phase signal are in phase with the carrier wave of the image signal before the image signal arrives. Regenerate signals with the same period. FIG. 2 is a timing chart showing the relationship between the GI signal and the GC signal.

GC信号は、受信側から送出されて来るGI信号を確認
すると、すぐに1.5秒間送出される信号である。CC
ITT勧告T−30に記載されている通信様式の伝送時
間は3分であるが、近来、その2分モード版が考えられ
、GI信号のすぐ後に、任意の周波数の信号(破線A)
を付加して2個のモードを区別するGI信号が受信側か
ら送出される場合が増えて来ている。
The GC signal is a signal that is sent for 1.5 seconds immediately after confirming the GI signal sent from the receiving side. C.C.
The transmission time of the communication format described in ITT Recommendation T-30 is 3 minutes, but recently a 2-minute mode version has been considered, and a signal of any frequency (dashed line A) is sent immediately after the GI signal.
Increasingly, the receiving side is sending out a GI signal that distinguishes between two modes by adding a GI signal.

この場合には、実質的には、0.79砂間しか受信側に
送出されないことになっている。これは、画信号到着前
に、PLL回路を動作する時間が少なくなったことに他
ならないものであり、前述のように、電圧保持回路のコ
ンデンサに所定の電圧と大きくかけ離れたものが充電さ
れた場合には、画信号到着前に、画信号の搬送波と同位
相、同周期を持つ信号を完全に再生できなかつた。また
、第3図は位相信号のタイミングチャートである。
In this case, in reality, only 0.79 minutes are sent to the receiving side. This is nothing but a reduction in the amount of time the PLL circuit operates before the image signal arrives, and as mentioned above, the capacitor of the voltage holding circuit is charged with a voltage that is far different from the predetermined voltage. In some cases, a signal having the same phase and period as the carrier wave of the image signal could not be completely reproduced before the image signal arrived. Further, FIG. 3 is a timing chart of phase signals.

位相信号も画信号の搬送波と同一周波数であるが、搬送
波のない期間が定期的に現われるため、PLL回路の動
作タイミングの取り方が非常に難かしくなるという欠点
もあった。本発明は上記欠点を解決するためになされた
ものであり、ファクシミリ受信装置において、送信側に
送出される通信制御信号をもファクシミリ受信装置の復
調回路に入力して、PLL回路を動作させることにより
、画信号到着前に完全に画信号の搬送波と同位相、同周
期の信号を再生するファクシミリ受信装置を提供するも
のである。
Although the phase signal also has the same frequency as the carrier wave of the image signal, periods in which no carrier wave is present appear periodically, making it extremely difficult to determine the operation timing of the PLL circuit. The present invention has been made to solve the above-mentioned drawbacks, and in a facsimile receiving device, the communication control signal sent to the transmitting side is also input to the demodulation circuit of the facsimile receiving device to operate the PLL circuit. The present invention provides a facsimile receiving apparatus which reproduces a signal having the same phase and period as the carrier wave of the image signal completely before the image signal arrives.

以下、図面に基づいて本発明を説明する。第4図は本発
明の一実施例におけるファクシミリ受信装置の概略構成
図である。第4図において、破線B内は復調回路を示し
、破線C内はPLL回路を示す。図において、1は制御
回路であり、内部に周波数検知機能を有している。2は
変調回路である。
The present invention will be explained below based on the drawings. FIG. 4 is a schematic diagram of a facsimile receiving apparatus according to an embodiment of the present invention. In FIG. 4, the area within broken line B indicates a demodulation circuit, and the area within broken line C indicates a PLL circuit. In the figure, 1 is a control circuit, which has a frequency detection function inside. 2 is a modulation circuit.

3はハイブリッド回路であり、理想的に使用されると変
調回路2から出力された信号は端子14,15から回線
にのみしか送出されないが、実際には理想的に使用しが
たいので、変調回路2から出力された信号は回線にも復
調回路にも入力される。
3 is a hybrid circuit, and when used ideally, the signal output from the modulation circuit 2 is sent only to the line from terminals 14 and 15, but in reality it is difficult to use it ideally, so the modulation circuit The signal output from 2 is input to both the line and the demodulation circuit.

4‘まAGC回路、5は波形整形回路、6はPLL回路
内にある位相比較器、7はPLL回路の動作または保持
を切換えるためのゲート回路、8はゲ−ト回路7を経て
入力する位相比較器の出力を直流成分に変換しかつ電圧
保持回路の機能をも果すローパスフィルター(以下、L
PFと略称する)、9はLPF8の出力電圧レベルによ
り自己の発振周波数を変える電圧制御型発振器(以下、
VCOと略称する)であり、その公称周波数は制御回路
1により切換えられる。
4' is an AGC circuit, 5 is a waveform shaping circuit, 6 is a phase comparator in the PLL circuit, 7 is a gate circuit for switching the operation or holding of the PLL circuit, and 8 is a phase input via the gate circuit 7. A low-pass filter (hereinafter referred to as L) converts the output of the comparator into a DC component and also functions as a voltage holding circuit.
9 is a voltage controlled oscillator (hereinafter referred to as PF) that changes its oscillation frequency depending on the output voltage level of LPF 8.
(abbreviated as VCO), whose nominal frequency is switched by the control circuit 1.

10は同期検波回路、11は信号処理回路、12は記録
回路であり、その動作は制御回路1により制御される。
10 is a synchronous detection circuit, 11 is a signal processing circuit, and 12 is a recording circuit, the operation of which is controlled by the control circuit 1.

上記構成を持つファクシミリ受信装置において、PLL
回路Cの出力信号を画信号到着前までに、画信号の搬送
波と同位相、同周期にする動作の説明を行う。なお、本
実施例の説明はCCITT勧告T−30に記載されてい
るファクシミリ中遠機の国際規格の通信様式に従って進
める。まず、ファクシミリ受信装置の電源を“ON”に
する。
In the facsimile receiving device having the above configuration, the PLL
The operation of making the output signal of the circuit C the same phase and period as the carrier wave of the image signal before the image signal arrives will be explained. The description of this embodiment will proceed in accordance with the communication format of the international standard for facsimile long-distance machines described in CCITT Recommendation T-30. First, turn on the power of the facsimile receiving device.

このとき、LPF8内のオベアンプ8bの電源電圧を±
12Vとすれば、電圧保持用のコンデンサ8dには十1
2Vから−12Vまでの範囲内にある電圧がランダムに
充電される。仮りに、コンデンサ8dに充電された電圧
を十12Vとすれば、LPF8はこの電圧レベルを維持
しつつ出力することになる。その結果、VCO9からは
公称周波数と全く異なる周波数を持つ信号が出力される
。続いて、ファクシミリ受信装置は待期状態に入る。次
に、送信側がファクシミリ受信装置を呼び出すと、この
呼出音により送受信間の回線が確立される。回線確立後
、被呼側にファクシミリ端末が存在することを発呼側に
通知する通信制御信号(以下、CED信号と略称する)
が受信側から送信側に伝送される。このCED信号の周
波数は2100日2であり、入力画信号の周波数にほぼ
等しい。また、このCED信号は制御回路25の制御信
号により変調回路2からハイブリッド回路3に出力され
、ハイブリッド回路3から回線を経て送信側に送出され
る。同時に、CED信号は、ハイブリッド回路3から復
調回路Bにも出力される。このとき、今まで閉じていた
ゲート回路7は制御回路1からの制御信号により、初め
て開かれる。復調回路Bに入力したCED信号は、AG
C回路4を経た後に二万に分かれ、一方は波形整形回路
5は通過してPLL回路Cに入力し、他方は同期検波回
路101こ入力する。
At this time, the power supply voltage of the amplifier 8b in the LPF 8 is ±
If the voltage is 12V, the voltage holding capacitor 8d has 11V.
A voltage ranging from 2V to -12V is randomly charged. Assuming that the voltage charged in the capacitor 8d is 112V, the LPF 8 will output while maintaining this voltage level. As a result, the VCO 9 outputs a signal having a frequency completely different from the nominal frequency. Subsequently, the facsimile receiving device enters a standby state. Next, when the sender calls the facsimile receiver, the ring tone establishes a line between the sender and the receiver. After the line is established, a communication control signal (hereinafter abbreviated as CED signal) notifies the calling party that a facsimile terminal exists on the called party.
is transmitted from the receiving side to the sending side. The frequency of this CED signal is 2100 days, which is almost equal to the frequency of the input image signal. Further, this CED signal is output from the modulation circuit 2 to the hybrid circuit 3 by a control signal from the control circuit 25, and is sent from the hybrid circuit 3 to the transmission side via a line. At the same time, the CED signal is also output from the hybrid circuit 3 to the demodulation circuit B. At this time, the gate circuit 7, which has been closed until now, is opened for the first time in response to a control signal from the control circuit 1. The CED signal input to demodulation circuit B is
After passing through the C circuit 4, it is divided into 20,000 parts, one of which passes through the waveform shaping circuit 5 and is input to the PLL circuit C, and the other part is input to the synchronous detection circuit 101.

PLL回路Cはゲート回路7が開いているため、このC
ED信号を用いて動作する。
Since the gate circuit 7 of PLL circuit C is open, this C
It operates using the ED signal.

つまり、このCED信号と同位相、同周期の信号となる
ように動作する。まず、位相比較器6は波形整形回路5
の出力信号とVCO9の出力信号とを、位相比較して位
相誤差信号を出力する。ところで、VCO9からは前述
のように公称周波数と大きくかけ離れた周波数を持つ信
号が出力されているために、この位相誤差信号は始めの
うちは大きな誤差を示すことになる。そして、この位相
誤差信号はゲート回路7を経て、LPF6に入力し、L
PF8が保持している直流電圧レベルを所定の電圧レベ
ル(例えば土OV)にならしめるように動作する。しか
し、LPF8内のコンデンサ8dには、大きな電圧(例
えば十12V)が充電されており、急には所定の電圧レ
ベル(例えば±OV)まで下がらないが、CED信号の
存続期間が2.6秒以上あるので、この期間中には充分
にLPF8の出力直流電圧レベルは所定の電圧レベルと
なり得る。したがって、VCO9からはCED信号と同
一の周波数(2100HZ)を持つ信号が出力されるこ
とになる。以上の説明において、PLL回路Cから出力
される信号の周波数は、画信号の搬送波の周波数とほぼ
等しくなり、後は位相と周期の誤差を修正するだけで良
い。次に、受信側から機種及び機能を知らせるCI信号
を出す。
In other words, it operates to become a signal with the same phase and same period as this CED signal. First, the phase comparator 6 is connected to the waveform shaping circuit 5.
The output signal of the VCO 9 and the output signal of the VCO 9 are compared in phase to output a phase error signal. By the way, since the VCO 9 outputs a signal having a frequency that is significantly different from the nominal frequency as described above, this phase error signal initially shows a large error. This phase error signal passes through the gate circuit 7 and is input to the LPF 6.
It operates to normalize the DC voltage level held by PF8 to a predetermined voltage level (for example, OV). However, the capacitor 8d in the LPF 8 is charged with a large voltage (for example, 112 V) and does not suddenly drop to a predetermined voltage level (for example, ±OV), but the duration of the CED signal is 2.6 seconds. Because of the above, the output DC voltage level of the LPF 8 can sufficiently reach the predetermined voltage level during this period. Therefore, the VCO 9 outputs a signal having the same frequency (2100 Hz) as the CED signal. In the above description, the frequency of the signal output from the PLL circuit C is approximately equal to the frequency of the carrier wave of the image signal, and it is only necessary to correct phase and period errors. Next, the receiving side issues a CI signal informing the model and function.

このGI信号も復調回路に入力するが、GI信号の周波
数が1850HZであるため、制御回路1はゲート回路
7を閉じてPLL回路を動作させず、保持状態にする。
続いて、受信側から送出されて来るGI信号に応じて、
送信側から通信可能なモードを知らせるGC信号が出力
される。
This GI signal is also input to the demodulation circuit, but since the frequency of the GI signal is 1850 Hz, the control circuit 1 closes the gate circuit 7 and does not operate the PLL circuit, leaving it in a holding state.
Next, in response to the GI signal sent from the receiving side,
A GC signal is output from the transmitting side to notify the mode in which communication is possible.

このGC信号は一般的には画信号の搬送波と同一周波数
(2100HZ)であり、また同一変調回路で変調され
、さらに同一回線を通過するため、CC信号は画信号の
搬送波と同位相、同周期となる。したがって、受信側に
GC信号が入力すると、制御回路1はゲート回路7を開
き、GC信号を用いて、PLL回路Cを動作させる。こ
れにより、PLL回路Cの出力信号は、短時間の内に位
相と周期を修正され、函信号の搬送波と同位相、同周期
となり得る。なお、GC信号が受信側に到着すると、受
信装置はGI信号が受信側に到着すると、受信装置はG
I信号の送出を停止する。また、GC信号に続いて、送
信側からは画信号の搬送波と同一周波数(2100HZ
)を持つ位相整合信号を送出する。
This GC signal generally has the same frequency (2100Hz) as the carrier wave of the image signal, is modulated by the same modulation circuit, and passes through the same line, so the CC signal has the same phase and period as the carrier wave of the image signal. becomes. Therefore, when a GC signal is input to the receiving side, the control circuit 1 opens the gate circuit 7 and operates the PLL circuit C using the GC signal. As a result, the phase and period of the output signal of the PLL circuit C are corrected within a short time, so that the output signal can have the same phase and period as the carrier wave of the box signal. Note that when the GC signal arrives at the receiving side, the receiving device receives the GI signal, and when the GI signal arrives at the receiving side, the receiving device
Stop sending the I signal. In addition, following the GC signal, the transmission side transmits a signal at the same frequency as the carrier wave of the image signal (2100Hz).
) is sent out.

受信側は、この位相整合信号を再生して、記録装置12
の位相を再生した位相整合信号に合致させる。位相整合
信号の再生は、PLL回路Cから出力される信号が画信
号の搬送波と同位相、同周期となっているため、余計な
位相整合信号再生回路を設けなくても、同期検波回路1
0および信号処理回路11により十分に再生できる。な
お、の期間中にもPLL回路Cを動作させても良いoな
お、ファクシミリ送信装置や受信装置には種々のものが
あり、送信側においてGC信号の変調回路と画信号の変
調回路とが異なっている場合や、受信側においてGC信
号の変調回路と画信号の変調回路が異なっている場合が
あり、GC信号区間中にPLL回路の出力信号が、画信
号の搬送波と位相及び周期が完全に一致することはない
The receiving side reproduces this phase matching signal and sends it to the recording device 12.
match the phase of the regenerated phase matching signal. Since the signal output from the PLL circuit C has the same phase and the same period as the carrier wave of the image signal, the phase matching signal can be reproduced by the synchronous detection circuit 1 without providing an extra phase matching signal reproducing circuit.
0 and the signal processing circuit 11, sufficient reproduction is possible. It is also possible to operate the PLL circuit C during the period of . There are various facsimile transmitting devices and receiving devices, and the GC signal modulation circuit and the image signal modulation circuit are different on the transmitting side. In some cases, the modulation circuit for the GC signal and the modulation circuit for the image signal may be different on the receiving side, and the output signal of the PLL circuit during the GC signal period may be completely in phase and period with the carrier wave of the image signal. There will never be a match.

しかし、この位相信号区間中に送信側から送出される位
相信号は、必ず画信号と同一変調回路で変調され、また
、同一復調回路で復調されるため、位相信号と画信号の
搬送波とは周期及び位相が完全に一致する。したがって
、この位相信号区間中に、PLL回路を動作させれば、
ほとんどのファクシミリ受信装置において、画信号到着
前に、PLL回路の出力には、画信号の搬送波と同位相
及び同周期の信号が得られる。ただし、位相信号に対し
てPLL回路を動作させることは、前述のように困難が
伴うため、本実施例のように、GC信号と画信号との変
調回路及び復調回路を同一にした方が好ましい。受信側
において、位相整合が終了すると、受信装置は位相整合
が終了したことを示すCFR信号を送出する。
However, the phase signal sent from the transmitting side during this phase signal period is always modulated by the same modulation circuit as the image signal, and demodulated by the same demodulation circuit, so the phase signal and the carrier wave of the image signal have a period of and the phases are completely matched. Therefore, if the PLL circuit is operated during this phase signal period,
In most facsimile receiving apparatuses, a signal having the same phase and period as the carrier wave of the image signal is obtained at the output of the PLL circuit before the image signal arrives. However, since it is difficult to operate the PLL circuit for the phase signal as described above, it is preferable to use the same modulation circuit and demodulation circuit for the GC signal and the image signal as in this embodiment. . On the receiving side, when the phase matching is completed, the receiving device sends out a CFR signal indicating that the phase matching has been completed.

このときPLL回路Cは保持状態にある。送信側はこの
CFR信号を受けて、始めて、画信号の送出を始める。
そして、受信側では、同期検波回路10‘こおいて、P
LL回路Cで再生された画信号の搬送波と同位相、同周
期の信号により、画信号の冒頭部から正常な同期検波が
行うことができる。
At this time, the PLL circuit C is in a holding state. Only after receiving this CFR signal does the transmitting side begin transmitting the image signal.
Then, on the receiving side, in the synchronous detection circuit 10', P
By using a signal having the same phase and the same period as the carrier wave of the image signal reproduced by the LL circuit C, normal synchronous detection can be performed from the beginning of the image signal.

以上はCCITT勧告T−30に記載されている伝送様
式に従って説明を行った。
The above explanation has been made according to the transmission format described in CCITT Recommendation T-30.

そのため、CED信号と画信号の搬送波とが同一であっ
た。しかし、一般のファクシミリ装置には、CCITT
勧告T−30に従う伝送モードの他に各ファクシミリメ
ーカーの自社伝送モードがあり、これらは、CED信号
と画信号の搬送波との周波数が異なる場合がある。この
場合には、VCOの公称周波数を制御回路により切換れ
ば良い。すなわちCED信号送出時にはVCOの公称周
波数をCED信号の周波数と一致させて、LPFから出
力されるVCOの制御電圧レベルを所定の電圧レベルと
し、次に画信号の搬送波と同周波数を持つ通信制御信号
が到着したときに、VCOの公称周波数を画信号の搬送
波と同一周波数に切換えれば、画信号到着前に画信号の
搬送波と同位相、同周期を持つ信号が再生できる。以上
のように、本発明によれば、ファクシミリ受信装置にお
いて、画信号到着前に送信側に伝送する通信制御信号を
復調回路内に入力して加え、復調回路内のPLL回路を
動作こせることにより、電源を‘‘ON’’したときに
、PLL回路内の電圧保持回路のコンデンサにいかなる
電圧が充電されても、受信側から送出されて来る前に所
定の電圧に設定できるため、次に受信装置に到着した画
信号の搬送波と同周波数を持つ送信側通信制御信号に対
してPLL回路を動作させると短時間で画信号の搬送波
と同位相、同周期の信号が再生できる。
Therefore, the carrier waves of the CED signal and the image signal were the same. However, general facsimile machines have CCITT
In addition to the transmission mode complying with Recommendation T-30, each facsimile manufacturer has its own transmission mode, and in these transmission modes, the frequencies of the CED signal and the carrier wave of the image signal may differ. In this case, the nominal frequency of the VCO may be switched by a control circuit. That is, when transmitting the CED signal, the nominal frequency of the VCO is made to match the frequency of the CED signal, the control voltage level of the VCO output from the LPF is set to a predetermined voltage level, and then a communication control signal having the same frequency as the carrier wave of the image signal is sent. If the nominal frequency of the VCO is switched to the same frequency as the carrier wave of the image signal when the image signal arrives, a signal having the same phase and period as the carrier wave of the image signal can be reproduced before the image signal arrives. As described above, according to the present invention, in a facsimile receiving apparatus, a communication control signal to be transmitted to the transmitting side is inputted into the demodulation circuit and added to the demodulation circuit before the arrival of the image signal, and the PLL circuit in the demodulation circuit is operated. , no matter what voltage is charged to the capacitor of the voltage holding circuit in the PLL circuit when the power is turned on, it can be set to a predetermined voltage before it is sent from the receiving side, so the next receiving When the PLL circuit is operated for a transmission side communication control signal having the same frequency as the carrier wave of the image signal that has arrived at the device, a signal having the same phase and same period as the carrier wave of the image signal can be reproduced in a short time.

したがって、画信号到着前に画信号の搬送波と同位相、
同周期の信号が確実に再生できるので、画信号の冒頭部
から正常な同期検波が行なえると共に正常な記録画が再
生できる。図面の簡単な説明第1図は通信制御信号の説
明図、第2図はGI信号とGC信号のタイミングチャー
ト、第3図は位相整合信号のタイミングチャート、第4
図は本発明の一実施例におけるファクシミリ受信装置の
ブロックダイアグラムである。
Therefore, before the image signal arrives, it is in phase with the carrier wave of the image signal.
Since signals of the same period can be reliably reproduced, normal synchronous detection can be performed from the beginning of the image signal, and a normal recorded image can be reproduced. Brief Description of the Drawings Figure 1 is an explanatory diagram of communication control signals, Figure 2 is a timing chart of GI signals and GC signals, Figure 3 is a timing chart of phase matching signals, and Figure 4 is an explanatory diagram of communication control signals.
The figure is a block diagram of a facsimile receiving apparatus according to an embodiment of the present invention.

1・・・・・・制御回路、2・・・・・・変調回路、3
・・・・・・ハイブリッド回路、6・・・・・・位相比
較器、7・・・・・・ゲート回路、8・・・・・・LP
F,9・・・・・・VC○,1 0・・・・・・同期検
波回路、B・・・・・・復調回路、C・・・・・・PL
L回路、8d”””コンデンサ。
1...Control circuit, 2...Modulation circuit, 3
...Hybrid circuit, 6...Phase comparator, 7...Gate circuit, 8...LP
F, 9...VC○, 1 0...Synchronous detection circuit, B...Demodulation circuit, C...PL
L circuit, 8d""" capacitor.

第1図 第2図 第3図 第4図Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1 入力する変調信号の搬送波を再生するフエーズ・ロ
ツクド・ループ手段と、このフエーズ・ロツクド・ルー
プ手段が出力する再生搬送波を用いて同期検波を行う復
調手段と、画信号到着前に自らが送信局に伝送する通信
制御信号をフエーズ・ロツクド・ループ手段に入力する
手段と、前記通信制御信号がフエーズ・ロツクド・ルー
プ手段に入力したときにフエーズ・ロツクド・ループ手
段を動作させる制御手段とを具備したことを特徴とする
フアクシミリ受信装置。
1. A phase locked loop means for regenerating the carrier wave of the input modulated signal, a demodulating means for performing synchronous detection using the regenerated carrier wave outputted by the phase locked loop means, and and control means for operating the phase locked loop means when the communication control signal is input to the phase locked loop means. A facsimile receiving device characterized by:
JP54055981A 1979-04-17 1979-05-08 facsimile receiving device Expired JPS6031380B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP54055981A JPS6031380B2 (en) 1979-05-08 1979-05-08 facsimile receiving device
US06/138,898 US4346410A (en) 1979-04-17 1980-04-10 Facsimile receiver
SE8002826A SE446802B (en) 1979-04-17 1980-04-15 FACSIMILE RECEIVER
DE3014668A DE3014668C2 (en) 1979-04-17 1980-04-16 Facsimile receiver
GB8012590A GB2049341B (en) 1979-04-17 1980-04-16 Fascimile receiver synchronous detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54055981A JPS6031380B2 (en) 1979-05-08 1979-05-08 facsimile receiving device

Publications (2)

Publication Number Publication Date
JPS55147876A JPS55147876A (en) 1980-11-18
JPS6031380B2 true JPS6031380B2 (en) 1985-07-22

Family

ID=13014248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54055981A Expired JPS6031380B2 (en) 1979-04-17 1979-05-08 facsimile receiving device

Country Status (1)

Country Link
JP (1) JPS6031380B2 (en)

Also Published As

Publication number Publication date
JPS55147876A (en) 1980-11-18

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