JPS6029979B2 - Failure diagnosis device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault diagnosis device capable of pointing out a fault in an error detection and correction device in a data transfer and processing device.

The error detection and correction code referred to here is, for example, the 64 code shown in FIG.
An explanation will be given using a "single error correction double error detection" code consisting of 8 information bits and 8 check bits. In Figure 1, "0" to "63" are information bits, and CO to C7 are check bits.The conventional error detection and correction device concentrated all the information bits in one place, but the actual logic board When realizing the circuit above, the information bits are divided into several blocks, and each block is divided into blocks.

It becomes possible to assemble the blocks with exactly the same circuit and reduce manufacturing costs. In particular, in the case of a main memory device, it is divided into four blocks, so that input/output data control, error detection and correction devices, etc. can all be made into the same circuit, and the number of types of logic boards can be reduced. Although it has the above-mentioned advantages, it has the disadvantage that it is difficult to identify which block is at fault when the error detection and correction device fails because the information bits are dispersed in each block.
In order to solve this drawback, the present invention is a fault diagnosis device that points out the fault range, and will be explained in detail below with reference to the drawings. First, an error detection and correction device that divides into blocks will be explained.

The symbols in Figure 1 are rearranged as shown in Figure 2, divided into 4 blocks, and each block is D1 (0, 4 in By), D2 (By
e1,5), D3 (Byte 2,6), D4 (Byte3
,7).

By means 8 bits of information, Byteo~7
correspond as shown in the table in Figure 2. Groups of bits set to "1" in each row of each block are named PO to P7 shown in the table of FIG. That is, PO of the DI block indicates information bits 0, 1, 2, 32, and 35. Also, PO of the D4 block indicates information bits 25, 28, 31, 59, 60, and 61. FIG. 3 is a diagram of the entire error detection and correction device. 1 is a data line for a signal consisting of 64 information bits and 8 check bits as shown in Fig. 1, and AI to A4 are data control circuits including error detection and correction devices, all of which are configured identically. Only the information bits are different.

AI is B〆eo, 4 information bit and C0, C4 check bit, A2 is BXel, 5 information bit and C1, C
A3 includes information bits in Bytes 2 and 6 and inspection bits in C2 and C6, and A4 includes information bits in Bytes 3 and 7 and inspection bits in C3 and C7. B.I.
~B4 is a register that holds data consisting of 18 bits, CI~C4 is a register output line, and GI~G4 is a syndrome (signal generation circuit) that indicates the accuracy of information bits.
This is the generation circuit for the syndrome
As shown in the figure. In Fig. 3, SO to S7 are the bit lines of the syndrome, and if there is no error in the information bits, all “
0” and an odd number of 1s means a single error; an even number of “1s” means a single error.
” indicates two or even number of errors. These judgments are made by the error bit determination circuit 2, and in the case of a single error, a signal indicating the error bit position is also decoded. 8 indicates the error position. Indication signal lines EI to E4 are correction circuits that correct register outputs of registers CI to C4 by signal line 3, and 4 is 64 data lines whose errors have been corrected.

Next, FIG. 4 will be explained. GI to G4 are syndrome generation circuits. FI to F8 are parity circuits that take the exclusive OR of the bits set to "1" in each row in the code divided into each block in FIG. shall be. P7 in Figure 2
, PO to P6. Further details of this are shown in FIG. F5 to F8 are completely equivalent to FI to F4, so they are omitted. In Figure 4, the syndrome generation circuit G
Although only the I block is shown, G2 to G4 are similarly configured. In Figure 5, the input d of the circuit FI
1 to d8, d12 are information bits (see Figure 2) 0 to 7, 35 for the syndrome generation circuit GI, and the output is P7, but information bits (see Figure 2) for the syndrome generation circuit G2 are Reference) 8 to 15, 43 and the output is P
Changes to O. The state of the change is shown in FIG. That is, P7 is P7→PO→PI→P for GI~G4
It has changed to 2. The same applies to output signals for other input/output signals. Next, in order to generate a syndrome, it is necessary to connect P7 and PO to P6 of each block in the table of FIG. 2 to combine the information of all the blocks into one. These are circuits F2 and F6 in FIG. X, Y, and Z of circuit F2 are P7, PO to P6 from blocks other than itself. In the case of Fig. 5, the syndrome generation circuit GI block is shown, and circuit F2 connects PO of another block to ×, Y, and Z, and circuit F6 connects P4 of another block to U, V, and W. . dcn (n=0 to 3) and dcm (m=4 to 7) indicate check bits. dl to d16 indicate information bits of each block. Output S0, S after connected
4 is a syndrome bit, which is the same as S0 and S4 in FIG. Connect other syndrome bits in the same way,
Syndrome generation circuit G2 block. From Tsuku to SI, S5,
S2 and S6 from the syndrome generation circuit G3 block,
S3 and S7 are generated from the syndrome generation circuit G4 block. The above is a description of the error detection and correction device. Next, a method for pointing out a failure from this circuit will be explained.

In FIG. 3, bl-b4 are for outputting the exclusive OR parity outputs PO-P7 generated in each block to the outside. However, the circuit portion where the syndrome bit is finally generated indicates that syndrome bit. For example, in the case of the syndrome generation circuit G2 block, P0, S
I, P2, P3, P4, S5, P6, and P7 are shown. Note that these are SI and S5, not P1 and P5).
These bl to b4 are placed on the data line so that they can be read. After reading, an exclusive OR of the information data given by an external device (not shown) is generated and compared with the information data that has just been read, so that a faulty part of the error detection and correction device can be pointed out. For example, the information output from bl to b4 shown in FIG. 3 is expressed as HI in FIG. 6 and named as error detection and correction device pointing information (hereinafter referred to as pointing information).

DISO has 11 blocks of S0 (syndrome bits)
, and D2PO indicates the PO output of 12 blocks. The following bits are also the output of the exclusive OR of each block. If all 32 bits of information data are set to "1" as a single pile, the normal state of the indicated information HI is expressed as day 2. If the status according to the indication information HI is day 3, it is determined that the status is different from the status generated by the external device, and D4P
Since O is different, syndrome generation circuit D4b. This means that the circuit that outputs the current PO is faulty. Furthermore, D
The ISO is also different, but as you can see from Figure 5, D4P
This is because since O is different, DISO' had this influence. Further, in order to make this indication effective, it is necessary to be able to stop the operation of the error bit determination circuit 2 shown in FIG. 3, and the control circuit 5 performs this control. That is, it is effective when there is no error in the information when the error detection and correction device is not used, and when an error occurs in the information when the error detection and correction device is used. Although the above description has been made regarding a circuit for generating a syndrome, the present invention is not limited to this and can be similarly applied to a test bit generation circuit. As described above, according to the present invention, failures in distributed logical blocks can be automatically pointed out using an external device, thereby making it possible to shorten failure time and repair time.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a "single error correction, double error detection" code, Fig. 2 is a diagram showing a code obtained by rearranging the codes shown in Fig. 1, and Fig. 3 is a diagram showing error detection to which this invention is applied. A schematic configuration diagram of the correction device, Figure 4 is a schematic configuration diagram of the syndrome generation circuit, Figure 5 is a schematic configuration diagram showing the exclusive OR circuit (parity generation circuit) of Figure 4, and Figure 6 is a schematic diagram of the syndrome generation circuit. FIG. 2 is a code diagram showing a process of pointing out a failure using the invention; In the figure, 1 and 4 are data lines, 2 is an error bit judgment circuit,
5 is a control circuit, GI to G4 are syndrome generation circuits, F
I to F8 are parity generation circuits, and bl to b4 are parity output lines. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 2 Figure 6 Snake's boat diagram Dimensions Figure 6

Claims (1)

[Scope of Claims] 1. A fault diagnosis device for a device that divides N information bits into a plurality of blocks and detects and corrects errors in the N information bits using a cyclic coding method, which The number of data control circuits is the same as that of the blocks, and each of the data control circuits has the same configuration. Each of the data control circuits is provided with a signal generation circuit that generates an output signal for detecting error bits according to the parity output. Each of the signal generation circuits has a number of parity generation circuits corresponding to the number of information bits divided into the plurality of blocks, and generates the parity output by appropriately combining the information bits divided as described above. further provided with means for outputting parity outputs of the plurality of parity generation circuits in each of the signal generation circuits to the outside, The failure diagnosis device is configured to point out which of the following has failed. 2. The failure diagnosis device according to claim 1, wherein each signal generation circuit is constructed of the same circuit.