JPS6028429B2 - Facsimile signal division coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile signal division coding apparatus that stores and converts facsimile signals using redundancy suppression coding.

Conventionally, in this type of facsimile signal encoding system, image signals in units of one scanning line stored in a plurality of line memories are sequentially read out and directly encoded by a single redundancy suppressing encoder.

This conventional method is shown in FIG. 1. Image signals generated from a plurality of facsimile terminals 1 pass through an exchange 2 and are stored in line memories 3 corresponding to each line for each scanning line. The image signals stored in 3 are sequentially read out for each line memory by a signal reading mechanism 4, and subjected to redundancy suppression encoding processing by a redundancy suppression encoder 5. Further, the output from the redundancy reduction encoding process 5 is stored in the encoded signal storage device 7 corresponding to each line via the signal writing mechanism 6. Note that 8 is a control device. However, in this conventional method, the processing speed of redundancy suppression encoding changes significantly depending on the state of the image signal included in one scanning line, so the readout speed from line memo 01'' 3 is processed by the redundancy suppression encoder 5. Since it is necessary to assume the slowest possible speed and read out sequentially at that speed, the redundancy suppressing encoder 5
The drawback was that it was not possible to perform multiple processing commensurate with the average processing power of . In order to solve the above-mentioned drawbacks of the conventional example, the present invention provides a waiting memory for storing 1-bit or several-bit image signals instead of the line memory, and sequentially stores the 1-bit or several-bit image signals in one buffer memory. The present invention provides a facsimile signal division and encoding device that stores image signals in units of several bits, divides and encodes image signals while referring to the internal state of the encoder.

Hereinafter, embodiments will be described in detail with reference to the drawings. Figure 2 shows
1 shows an embodiment of the present invention, 1 is a facsimile terminal, 2 is an exchange, 4 is a signaling mechanism, 8 is a control device, 9 is a waiting memory, 1 is a buffer memory 11 is an internal state memory, 12 is a signal read gate circuit, 13 is a redundancy suppression division encoding circuit, 14 is a signal write gate circuit, and 15 is a storage device.

The control device 8 is a device that generates control signals for controlling the signal readout mechanism 4, the signal readout gate circuit 12, the redundancy suppression encoding circuit 13, the signal write gate circuit 14, etc., and is configured using, for example, a microprocessor.

The waiting memory 9 has a smaller storage capacity than the conventional line memory 3 (FIG. 1), and has a capacity to store an image signal having one bit or several bits as a basic unit.

Buffer memory 1, for example, FIF○ (First-
The third
As shown in the figure, an image signal corresponding to the number of bits of the basic unit of the first line, an image signal corresponding to the number of bits of the basic unit of the second line, sequentially read out from each waiting memory 9 by the output mechanism 4,...
...Writing is performed sequentially from the beginning,
It is also a memory that is read out in that order.

The internal state memory 11 is provided corresponding to each line, and stores internal state signals that are being encoded by the redundancy suppression divisional encoding circuit 13.

This is necessary because encoding is performed by dividing into basic units. For example, when using a well-known run-length encoding method as an encoding method, in the present invention, the length of a white or black run is counted by dividing the image signal by the number of basic unit bits and dividing it into multiple time slots. Therefore, the intermediate internal state, ie, the count value of the length of the run, and the signal for identifying whether the run is white or black are stored in the internal state memory 11. The signal readout gate circuit 12 converts the image signals stored in the buffer memory 1 and the internal state signals from the internal state memory 11 into redundancy suppression division codes for each basic unit of each line in response to a control signal from the control device 8. Gate control is performed so that the signals are sequentially sent to the conversion circuit 13.

The redundancy suppression divisional coding circuit 13 performs redundancy suppression coding for each line in a time-divisional manner for each of the basic unit bits of the image signal. A new internal state is obtained using the basic unit bit of the new image signal from the buffer memory 10 and sent to the internal state memory 11.

When there is an encoded output (for example, when the run length has been counted for a certain white or black color), the encoded output is sent to the storage device 11. The signal writing gate circuit 14 selects one of the plurality of internal state memories 11 based on a control signal from the control device 8, writes the internal state encoded by the redundancy suppression divisional encoding circuit 13, and writes the same internal state. When the circuit 13 has a completed encoded output, it selects the storage device 11 of the corresponding line and performs gate control to write the encoded output.

Next, the operation of this embodiment will be explained.

First, image signals generated from a plurality of facsimile terminals 1 are stored in a waiting memory 9 corresponding to each line via an exchanger 2. This waiting memory 9 can store image signals having one bit or several bits as a basic unit, and is used for alternately writing and reading. The image signals stored in the waiting memory 9 are sequentially sent one bit or several bits at a time for each line to the buffer memory O' for storage by the signal reading mechanism 4. The image signals sequentially stored in the buffer memory 0 in 1-bit or several-bit basic units are sequentially sent to the redundancy suppression division encoding circuit 13 through the signal readout gate circuit 12 along with the contents of the internal state memory 1 corresponding to each line. sent. The redundancy suppression divisional encoding circuit 13 uses the 1-bit or several-bit image signal and the internal state signal stored in the internal memory 11, that is, the previous intermediate result, to generate a newly changed internal state signal and a code. If there is an encoded output, the encoded signal is sent to the signal write gate circuit 14. This internal state signal is recorded in the internal state memory 1 corresponding to each line, and the encoded signal is stored in the storage device 15. As explained above, according to the present invention, redundancy reduction coding is performed by dividing into basic units of one bit or several bits,
In addition, since the buffer memory is used to average the encoding processing speed, the speed of reading from the queue memory can match the average processing capacity of the redundancy reduction encoding circuit, and the number of multiplexed processes is significantly improved. Advantages and therefore, the present invention can provide a facsimile signal division and coding apparatus of great utility.

[Brief explanation of the drawing]

Figure 1 is a diagram for explaining the subordinate method;
The figure is a configuration diagram of an embodiment of the present invention. FIG. 3 is a diagram showing the state of the buffer memory 10. 1
・・・Facsimile terminal, 2...Sakai facsimile machine, 4...
・Signal reading mechanism, 9...Waiting memory, 10...
・Buffer memory, 11... Internal state memory, 12.
...Signal read gate circuit, 13...Redundancy suppression division coding circuit, 14...Signal write gate circuit, 1
5...Storage device. Figure 1 Figure 3 Figure N Ship

Claims (1)

[Claims] 1 In a device that encodes image signals sent from multiple facsimile terminals through multiple lines using a single common encoder and stores the redundancy-suppressing code, a device is installed corresponding to each of the multiple lines, and a plurality of waiting memories each storing one bit or several bits of the image signal as a basic unit; a buffer memory sequentially storing the basic unit of image signal read out from the plurality of waiting memories; and a buffer memory corresponding to each line. An internal state memory stores the internal state in the middle of encoding, and the signal from the internal state memory and the image signal of the basic unit from the buffer memory are read and encoded, and the next internal state or encoding is performed. Input/output of signals between a redundancy suppression divisional encoding circuit that sends signals, the redundancy suppression divisional encoding circuit and the internal state memory corresponding to each line, and input/output of signals to the encoded signal memory corresponding to each line. 1. A facsimile signal division and encoding device, comprising: a control circuit for controlling input of an encoded signal.