JPS6028327A - Logical circuit - Google Patents

Abstract

PURPOSE:To allow the circuitry to make little difference in the operating speed and the circuit threshold value even if any of logical signal input points is used by connecting MOSFETs in parallel between a positive power supply and a logical signal output points, connecting a series circuit of two MOSFETs in parallel between a logical signal output point and ground and devising the connection of each gate. CONSTITUTION:An MOSFET gate 53 placed at a point relatively remoter to a logical signal output point 31 than the position of an MOSFET gate 41 in MOSFETs 51-53 is connected to a logical signal input point 35 to which the MOSFET gate 41 is connected. Further, the MOSFET gate 51 placed at a position relatively nearer to the output point 31 than the point of the MOSFET 43 in the MOSFETs 51-53 is connected to an input point 37 to which the MOSFET gate 43 is connected. The equivalent circuits when giving logical ''1'' to logical input signals IN2 and IN3, IN1 and IN3, and IN1 and IN2 at all times in this case are respectively Figs a, b and (c). Thus, even if any two of the logical signal input points 35, 36 and 37 are used to conduct inverter operation, there is no or little difference in the switching speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit using MOSFETs, and in particular, three or more MOSFETs of the same channel are connected in series between a power supply voltage (including ground voltage) application point and a logic signal output point. Concerning logic circuits with structure.

[Technical background of the invention and its problems]

Figures 1 (a) and (b) are diagrams showing the symbols of a three-man-powered NAND gate gate and NOR dart.If these two darts were to be realized with a CMOSFET configuration, conventionally Figures 2 (,), (b) ) is configured as shown in the circuit of Vr7). Sunawachi, conventional three-person CMOS INA
As shown in FIG. 2(, ), ND r-to is connected to three P-channel MOSFETs between the positive polarity power supply voltage VDD application point and the logic signal output point 11 from which the logic output signal OUT is obtained.
12, 13, and 14 are connected in parallel, and logic signal output point 1
It is constructed by connecting three N-channel MOSFETs 15, 16, and 17 in series between 1 and the ground voltage VSII application point. Further, in this NAND case, the darts of the P-channel MOSFETs 1-2 and the darts of the N-channel MOSFET 15 are connected to each other, and the first logic input signal INI is supplied thereto, and similarly, the darts of the P-channel MOSFETs 1-3 are connected to each other. N-channel MOS
The gates of FETs 1 and 6 are connected to each other, and the second logic input signal IN, 9 is supplied thereto, and similarly the P channel M
OSFET 1 4 darts and N-channel MOSFET
17 is connected to the third logic input signal I.
NJ is supplied.

In addition, the conventional three-man power CM08 NOR dirt is shown in Figure 2 (
As shown in b), contrary to the above NAND gate gate, three P-channel MOSFETs 2 are connected between the VDD application point and the logic signal output point 21 from which the logic output signal OUT is obtained.
2, 23, and 24 are connected in series, and three N-channel MOSFETs 25, 26, and 27 are connected in parallel between the logic signal output point 21 and the VSII application point. In this NOR dart, the dart of the P-channel MOSFET 2 2 and the dart of the N-channel MOSFET 2 5 are further connected to each other, and the first logic input signal INJ is supplied thereto.
Channel MOSFET 2 3 dart and N channel M
The gate of OSFET 2 6 is connected to which the second logic input signal IN 2 is supplied, and similarly the dart of P-channel MOSFET 2 4 and the N-channel MOSFE are connected to each other.
Dart of T27 is connected and the third logic input signal INJ is supplied here.

By the way, the three-man power N shown in Figures 1(a) and (b)
In the NOR dart, any two of the three input signals are always at the vDD level (logic).
IfiVss level (logic ``0'')
level) and may be used to act as an inverter for one logic input signal. However, when using the conventional dart constructed as shown in FIGS. 2(a) and 2(b) in this manner, there are the following drawbacks.

For example, in the NAND gate case, as shown in FIG. 3, the second and third logic input signals IN, ? , IN
, 9, when a 1" level is constantly supplied, Figure 3 (b
), the first and third logic input signals IN4
, When 1# level is always supplied as INJ, and when 11 level is always supplied as the logical input signal INI and IN2 of y1.2.2 as shown in FIG. 3(C), the respective inverters Compare behavior.

Figures 4(a), (b), and (e) are shown in Figure 3 above (
FIG. 2 is an equivalent circuit diagram of the circuit of FIG. 2(a) corresponding to each of a), (b), and (c).

In the case of the circuit of FIG. 4(,), the P-channel MO8FETs 23 and 14 in the circuit of FIG. 2(,) are always off,
Since the N-channel O8FETs 16 and 17 are always on, this circuit can be regarded as a CMOS inverter consisting of the P-channel MO8FET 12 and the N-channel O8FET 15 and receiving the first logic input signal INJ. In addition, in FIG. 4(a), the resistance R,
, R3 are resistors having a value corresponding to the on-resistance of the N-channel MO8FETs 16 and 17, and the capacitor C
NI, CN2 are N channel O8FETs 15 to 1
7 and the VSII application point, and has a value corresponding to the parasitic capacitance based on MOSFETs 15 to 17, and a capacitor C3.
ut is generated parasitically between the logic signal output point 11 and the VIi8 application point, and! l) It has a value corresponding to the capacitance including the parasitic capacitance based on MOSFET 15.

In the case of the circuit of FIG. 4(b), the P-channel MO8FE
T 12 and 14 are always off, the N-channel MO8F
Since ET 15 and 17 are always on, this circuit is connected to the O8FE between P channel MO8FET 13 and N channel.
T16 and can be regarded as a CMOS inverter that receives the second logic input signal IN2 as an input.

In the case of the circuit of FIG. 4(C), the P channel MO8FE
T J 2, 13 is always off, the N-channel MO3
Since FETs 15 and J6 are always on, this 0'' circuit consists of P-channel MO8FET 14 and N-channel MO8FET 17, and the third logic input signal IN
, 9 as inputs.

Note that in this FIG. 4(C) and the above-mentioned FIG. 4(b), the resistor R1*R2la3 is connected to the N-channel MO8FE.
T is a resistor with a value corresponding to the on-resistance of 15 to 17.
This is a capacitor corresponding to the one in Figure (a).

In the circuit shown in FIG. 2(,), if the three N-channel O8FETs 25 to 17 are designed with the same channel length and channel width, the three resistors R1,
The values of R2 and R3 are all equal, and the fourth
Capacitor CNJ in each circuit of figures (a) to (C),
The values of CN2 and CHt are also equal to each other. Now, the logic input signals INJ, IN2, which set the logic signal output point 1 to the ``1# level'' are applied.
Consider the operation of the equivalent circuit in FIGS. 4(,) to (c) when INS is given.

In the circuit shown in FIG.
FET J2 is turned on and logic signal output point 11 is set to “1”.
” level, it is sufficient to charge only the capacitor C3ut connected to the logic signal output point 11 via the MOSFET 12. On the other hand, as shown in FIG.
In this case, in addition to charging the above capacity C3ut,
It is necessary to charge the two capacitors CNI and CN2 at the same time, and in the case of Fig. 4(b), in addition to the capacitor C3ut, C
NI also needs to be charged at the same time. Therefore, the impedance between the logic signal output point 11 and the VBS application point is the smallest in Fig. 4(,), largest in Fig. 4(C), and largest in Fig. 4(b). is a value between.

This difference in impedance means that
This means that the switching speeds are different, and as a result, when the conventional circuit shown in FIG. There is.

・By the way, the circuit threshold voltage V of a CMOS inverter
The is generally given by the following formula (where VtM and Vthp are the threshold voltages of the N-channel and P-channel MO8FETs, DD is the power supply voltage, KP and KN are the O between the P-channel and N-channel
This is a constant indicating the current drive capability determined by the channel length, channel width, etc. of the 8FET. ) Here, Figure 4 (a) ~
When comparing the circuit threshold voltages of each equivalent circuit as an inverter in (c), it is assumed that the current drive capacity of each of MOSFETs 15 to 17 is 3KN independently.
In the case of the circuit shown in the figure (-), MOSFET 15 and resistor R2
What is the connection point? In order to become YVss, MOSFET
The current drive capability of No. 15 is approximately 3KN. However, in the circuit of FIG. 4(b), K u MOSFET
7 e also has a resistor R1 on the VDD side, and a fourth
In the case of the circuit in Figure (c), MOSFET 17 and V
There are two resistors R1+R2 on the DD side, and the current driving ability of the MOSFETs l 6 and 17 incorporated in each circuit is lower than that of the resistor R1 or R1 and R2 alone. Therefore, the circuit threshold voltage as an inverter is the smallest in Figure 4 (,), and the one in Figure 4 (b) is even larger.
The one in figure (c) is the largest. Generally, the noise margin in a CMOS inverter depends on the circuit threshold voltage. Therefore, when the conventional circuit shown in FIG. 2(a) is operated as an inverter, there is a drawback that the noise margin varies depending on which input signal is used.

Also, the above-mentioned drawbacks are not due to NAND gate stupidity,
Conventional three-person CMO8NAND shown in Figure 2(b) above
The same thing happens with darts.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to have n logic signal input points (n is an integer of 3 or more), and to The object of the present invention is to provide a logic circuit in which there is no difference in switching speed and circuit threshold voltage, or in which the difference is small even when using an inverter under operating conditions.

[Summary of the invention]

In order to achieve the above object, the present invention includes a three-man powered CMO8NAND dart, and two series circuits, each consisting of three N-channel MO8FETs connected in series, as a ground voltage application point and a logic signal output point. and connecting each of the three MOSFET gates connected in series in the two series circuits to mutually different logic signal input points of the n logic signal input points, And, of the three MOSFETs connected in series in one series circuit, each of the two logic signal input points to which specific two darts are connected is connected in series in the other series circuit. Of the three MOSFETs listed above, each of the two specified MOSFETs
8FET, 1: D is also placed at a position relatively close to or relatively far from the logic signal output point 2
Each dart of each MOSFET is connected.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings. FIG. 5 is a circuit diagram showing the configuration of an embodiment of the present invention, and is a circuit diagram in which the present invention is implemented in a three-man powered NAND gate indicated by a circle in FIG. 1 (,). .

This circuit includes three P-channel MO8FETs 32 and 33 between the positive polarity power supply voltage VDD application point and the logic signal output point 3 for obtaining the logic output signal OUT'f.

34 are connected in parallel, and two series circuits 40.50 are connected between the logic signal output point 31 and the ground voltage VSS application point.
It is constructed by inserting in parallel. One of the above series circuits 40 further includes three N-channel MO8FETs 41 and 42.
, 43 connected in series, and similarly, the other series circuit 5o includes three N-channel MO8FETs 51, 5.
2 and 53 are connected in series. Furthermore, in this embodiment circuit, the dart of the P-channel MO8FET 32, the dart of the N-channel MO8FET 41, and the dart of the N-channel MO8FET 53 are connected in common, and furthermore, this common dart is a logic signal to which the first logic input signal INI is applied. It is connected to input point 35. Similarly, the above P
Channel MO8FET 33 darts and N channel MO
8FET 42 (DI"-t and N f-y
The darts of the M08FETs 52 are connected in common, and this common dart is further connected to a logic signal input point 36 to which a second logic input signal IN2 is applied. Similarly, the dirt of the above P-channel MO8FET 34 and the N-channel MO8FE
T43)ff-) and N-channel MO8FET
51 darts are connected in common, and this common dart is further connected to a logic signal input point 37 to which a third logic input signal IN3 is applied.

That is, in this embodiment circuit, logic signal output point 3
1 and the ground voltage vBIl application point are two series circuits 40 and 50 each configured by connecting three N-channel MO8FETs 41 to 43 degrees and 51 to 53 in series.
are inserted in parallel.

Furthermore, each of the three MOSFs in the two series circuits 40.50
ET 41-43. The darts 51-53 are connected to different ones of the three logic signal input points 35-37, and are connected to one MOSFET in one series circuit 40.
The three MOSFETs 51 in the other series circuit 50 are connected to the logic signal input point 35 to which the DART 41 is connected.
Among MOSFETs 53 to 53, the MOSFETs 41 and 41 are also located at a position relatively far from the logic signal output point 31.
ET 53 dart is connected. Further, to the logic signal input point 37 to which the dart of one MOSFET 43 in one series circuit 40 is connected, one of the three MOSFETs 51 to 53 in the other series circuit 50 is connected.
The dart of MOSFET 51, which is located relatively close to the logic signal output point 31, is connected to the FET 43 as well.

Next, a three-person CMO8NAND with the above-mentioned configuration.
A case will be explained in which the Dart is used as an I/Putter by always supplying the "'1" level as any two input signals in the same way as described above.

First, as shown in FIG. 3 (,), the logic input signal IN
,? , 1 to always keep INJ at 1” level,
P-channel MO8FETs 33 and 34 are always off, N
Channel MO8FET 42 , 43 , 51 , 52
is always on. Therefore, the equivalent circuit at this time is as shown in FIG. 6(,). That is, a P-channel MO8FET 32 whose dart is connected to the logic signal input point 35 is inserted between the VDD application point and the logic signal output point 31, and between the logic signal output point 31 and the V88 application point. , MOSFET 41, a resistor R12 having a value corresponding to the on-resistance of the MO8FET 42, and the MOSFET 41.
Resistor R1 with a value equivalent to the on-resistance of 8FET 43
3 are connected in series, and similarly logic signal output points 31 and V81
A resistor R14 having a value corresponding to the on-resistance of the MO8FET 51 is connected to the MO8FET 51.
A resistor R'15 having a value corresponding to the on-resistance of 52 and a MOSFET 53 are connected in series. Also, M.O.
Series connection point 44 of SFET 41 and resistor R12 and V8
The dimensions of MO8FET41.42 (
For example, a parasitic capacitor C1l having a value corresponding to the area of the source and drain regions, etc.) is connected. Similarly, a parasitic capacitor C12 having a value corresponding to the dimensions of the MOSFETs 42 and 43 is connected in series with the resistors R12 and R13, between the connection point 45 and the VSS application point. Similarly, the series connection point 54 of resistors R14 and R15 and VSS
A parasitic capacitor C13 having a value depending on the dimensions of the MOSFETs 5f and 52 is connected between the application point and the MOSFET 5f.

Similarly, between the series connection point 55 of resistor R15 and MOSFET 53 and the vss application point, MO8F'ET 52
, 53, the parasitic capacitor C14 has a value according to the dimensions of
is connected. Furthermore, logic signal output point 31 and V88
A parasitic capacitor COUT whose value corresponds to the dimensions of the MOSFETs 41 and 51 is connected between the application point and the application point. Note that parasitic capacitances other than those described above occur, but they are omitted because they are irrelevant to the explanation that follows.

Furthermore, as shown in FIG. 3(b), the logic input signal IN
I, IN,? '? When always setting the level to ``'1#, P-channel MO8IT 32, 3J are always off, N-channel MO8FET 41, 43, 51
, 53 are always on. Therefore, the equivalent circuit at this time is as shown in FIG. 6(b). That is, there is a P-channel MO8 between the VDD application point and the logic signal output point 31.
FET 33 is inserted, logic signal output point 31 and V88
A resistor R11 having a value corresponding to the on-resistance of MOSFET 41 + a resistor R13 having a value corresponding to the on-resistance of MOSFET 42 and MOSFET 43 are connected in series between the application point and the logic signal output point 31. A resistor R14 having a value corresponding to the on-resistance of MOSFET 510 and a resistor R16 having a value corresponding to the on-resistance of MOSFET 52 and MOSFET 53 are connected in series between the V88 application point and the resistor R14. Also, Figure 6 (,)
Similarly, a parasitic capacitor Ctt・C is connected between each of the series connection points 44, 45, 54゜55 and the V8g application point.
Furthermore, a capacitor COUT similar to that shown in FIG. 6(a) is connected between the logic signal output point 3 and the VI18 application point.

Furthermore, in the embodiment circuit of FIG. 5, the circuit shown in FIG.
As shown in c), when the logic input signals INJ and IN2 are always set to the “1# level”, the P channel MO8FE
T 32.34 always off, N-channel MO8FET
41.

42.52.53 are always on. Therefore, the equivalent circuit at this time is as shown in FIG. 6(c). That is, there is a P between the vDD application point and the logic Gf' output point 3.
A channel MO8FET 34 is inserted, and a MOSFET 41 is inserted between the logic signal output point 3 and the VSS application point.
, a resistor R11z R having a value corresponding to the on-resistance of 42
12 and MO8FET 43 are connected in series, and similarly MOSFET 51 is connected between the output point 31 and the VH8 application point.
and MO8F'ET 52.

A resistor R15°R16 with a value corresponding to the on-resistance of 53
are connected in series. Also, in the case of this Fig. 6(c), as in Fig. 6(,), the series connection points 44, 45
.

By the way, in the example circuit shown in FIG.
Channel MO8FET 4' 1~43. If 51~53 are designed with the same channel length and channel width,
Resistance R11""R in the circuit shown in Figure 6 (,) to (C)
All 16 values are equal.

Moreover, the values of each of the capacitors CI1 to C14 and C0UT in each equivalent circuit are also equal to each other.

Next, in each equivalent circuit of FIG. 6 (8) to (C) above, each logic input signal INJ, IN2, IN, l is applied so as to set the logic signal output point 3 to the '1# level. Think about the behavior when being exposed to.

In the circuit of FIG. 6(,), the logic input signal INJ is
0# level, which causes P channel MO8
FET 32 is turned on and logic signal output point 31 is
# When setting the level, the MOS that turns on the capacitor COUT connected to the logic signal output point 31
In addition to charging via FET 32, it is necessary to charge capacitor C13 via resistor R14 and capacitor C14 via resistor R141R15 in series.

On the other hand, in the circuit of FIG. 6(c), when setting the logic signal output point 3 to "1" level, the capacitor C0fJT connected to the logic signal output point 3 is turned on. In addition to charging via the MOSFET s4, the capacitor C11 is also charged via the resistor R11.
It is necessary to charge each capacitor 012 through 1R12 in series. Furthermore, in the circuit of FIG. 6(b), when setting the logic signal output point 31 to the P1# level, the capacitor 00 connected to the logic signal output point 3
In addition to charging through the MO8FET33 that turns on the capacitor Ct1 through the resistor R11, the resistor R
It is necessary to respectively charge the capacitor C13 via the capacitor C14.

Here, since the impedance toward the V8B application point side seen from the logic signal output point 31 is the same in the equivalent circuits of FIGS. 31 can be switched to the "1" level. On the other hand, when setting the logic signal output point 3 to the "1" level in the equinodal circuit shown in FIG. 6(b),
), As in the equivalent circuit of (c), it is necessary to charge two capacitors C11 + C13 in addition to C0UT, so in the circuit of Fig. 6 (b), the logic (,4
The impedance from the signal output point 31 to the 7'mVas application point side has almost no difference from that shown in FIGS. 6(a) and 6(c). Therefore, the equivalent circuit of FIG. 6(b) can also switch the logic signal output point 31 to the 11# level at almost the same speed as the circuits of FIGS. 6(,) and (c).

In other words, in the embodiment circuit shown in FIG. 5, it is possible to prevent any difference in switching speed from occurring no matter which of the three logic signal input points 35, 36, and 37 is used for the adjustment operation. Or, if there is a difference, it can be made smaller.

By the way, in the example circuit shown in Fig. 5, if the current drive capability on the N-channel side is set to be equal to that of the conventional circuit shown in Fig. 2 (,), six N-channel MO8FETs
41 to 43. The individual current drive capabilities of each of 51 to 53 are the three N-channel MO8FETs in Figure 2 (,).
There may be 5 to 17 individual A's of each. For this reason, the six N channels IV! in FIG. [08
The dimensions of each element of FET 41 to 43 degrees and 51 to 53 are as follows:
Three N-channel MO8FETs in the figure (,) 15-1
7 can be made into a German, thereby making Figure 6 (
, ) ~ (c) capacitor C11+ C12r C1
The value of 3r C14 is also /J% smaller than that of capacitors CN1, CN2 in FIGS. 4(a) to 4(C). Therefore,
Compared to the equivalent circuit of the conventional circuit shown in FIG. 4(c), which has the slowest switching speed, the switching speed in FIGS.
) can increase the switching speed in each equivalent circuit.

Furthermore, when comparing the circuit threshold voltages as an inverter of each equivalent circuit of FIGS. 6(a) to (c), FIG.
) and (C) are the same. Also, if we look at Figure 6(b), we can see that MOSFET 4-2 also has a resistor R on the VDD side.
rt Ka MO8FE'l' 52 L Rimo VDD
Because there is a resistor R14 on the side, the current drive capability on the N-channel side is almost the same as that in Figures 6(,) and (c), and the circuit threshold voltage of this equivalent circuit is also as shown in Figure 6(a).
, there is almost no difference from that in (c). Therefore, the noise margins of the equivalent circuits shown in FIGS. 6(,) to (c) do not differ, or even if they do exist, they can be made small. In other words, in the example circuit shown in Figure 2a5, no difference is made in the noise margin no matter which of the three logic signal input points 35, 36, and 37 is used for impark operation. If there is a difference, it can be made smaller.

FIG. 7 is a circuit diagram showing the configuration of another embodiment of the present invention. This embodiment circuit, like the embodiment circuit shown in FIG. N-channel MO8FET41-43
．． The dart connections 51 to 53 are different from those shown in Fig. 5. On the N-channel side of this example circuit, the dirt of MOSFET 41 and the MOSFET
52 darts are connected to the logic signal input point 35,
The dart of MOSFET 42 and the dart of MOSFET 51 are connected to the logic signal input point 37, and
The dart of OSFET 43 and the dart of MOSFET 53 are connected to the logic signal input point 36.

That is, in this embodiment circuit, two series circuits 4
3 MOSFETs each within 0.50 41~43°51
~sa)y''-) are the three logic signal input points 35~3
The logic signal input point 35 to which the dart of MOSFET 41 in one series circuit 40 is connected to different ones of 7, and to which the dart of MOSFET 41 in one series circuit 40 is connected, is connected to three MOSFETs 51 to 7 in the other series circuit 50. The above MO8F out of 53
ET 4J is also connected to the logic signal output point 31 with the dart of MOSFET 52 located relatively far away, and similarly the MOSFET 4 in one series circuit 40 is connected to the logic signal output point 31.
The logic signal output point 7 to which dart number 2 is connected is
Three MOSFETs 5 J~ in the other series circuit 50
53, the MOSFE is located at a position relatively closer to the logic signal output point 31 than the MO8FET 42 mentioned above.
T51 dart is connected.

In this embodiment circuit, for the same reason as mentioned above, regardless of which of the three logic signal input points 35, 36, and 37 is used for impark operation, the switching speed and circuit threshold voltage will be affected. It is possible to prevent the difference from occurring, or to reduce the difference if it does occur.

FIG. 8 is a circuit diagram showing the configuration of still another embodiment of the present invention. This embodiment circuit is an embodiment of the present invention in a three-person NOR gate shown by the symbol in FIG. 1(b).

This circuit connects two series circuits 7o and go in parallel between a positive power supply voltage VDD application point and a logic signal output point 61 from which a logic output signal OUT is obtained, and further connects the logic signal output point 61 and ground. 3 N between the voltage Vlill application point
Channel MO8FET 62.

63 and 64 are connected in parallel. One of the above series circuits 70 further includes three channel MO8FET7J.
, 72, and 73 are connected in series, and similarly, the other series circuit 80 includes three P-channel MO8FETs 81.
, 82 and 83 are connected in series. Further, in this embodiment circuit, the dart of the P-channel MO8FET 71, the dart of the P-channel MO8FET 83, and the r-to of the N-channel MO8FET 62 are commonly connected, and furthermore, this common dart is connected to the logic signal to which the first logic input signal INZ is applied. It is connected to input point 65. Similarly, P channel MO8FET 72 dart and P channel MO8FE
T 82 dart and N channel MO8FET e
The darts of a are commonly connected, and this common dart is further connected to the logic signal input point 6 to which the second logic input signal IN2 is applied.
Connected to 6. Similarly, the darts of the P-channel MO8FET 73, the darts of the P-channel MO8FET 81, and the darts of the N-channel MO8FET 64 are commonly connected, and this common dart is further connected to a logic signal input point 67 to which a third logic input signal INJ is applied. .

That is, in this embodiment circuit, compared to the embodiment circuit shown in FIG. 5, the P-channel MOSFET is replaced with an N-channel MOSFET, and the N-channel MOSFET is replaced with a P-channel MOSFET. Note that in this embodiment circuit as well, the P-channel side MOSFETs 71 to 7
3. The ketone connections 81-83 can be changed in the same manner as in FIG. 7 above.

9 to 13 are circuit diagrams showing the configurations of various embodiments of the present invention. These valley embodiment circuits are cases in which the present invention is implemented in a four-person NAND gate.

The embodiment circuit of FIG. 9 has four P-channel MO8s between the positive power supply voltage VDD application point and the logic signal output point 91
It is constructed by connecting FETs 92 to 95 in parallel and further inserting two series circuits 100 and 110 in parallel between the logic signal output point 91 and the ground voltage V811 application point. One of the above series circuits 100 further includes four N-channel MO8s.
FETs 101 to 104 are connected in series, and the other series circuit 110 is composed of four N-channel MO8s.
It is constructed by connecting FETs 11f to 114 in series.

Furthermore, in the embodiment circuit, P-channel MO8FET
92, N-channel MO8FETs 201 and 114 are connected in common, and this common dart is connected to a logic signal input point 9''6 to which the first logic input signal IN2 is applied.
connected to. Similarly, P-channel MO8FET, 9
3. N-channel MO8FET J O,? .

113 darts are connected in common, and this common dart is further connected to a logic signal input point 97 to which a second logic input signal IN2 is applied. Similarly, P channel MO8F
ET94, N-channel MO8FET103.11
The two darts are connected in common, and this common dart is further connected to a logic signal input point 98 to which a third logic input signal INJ is applied. Similarly, P-channel MO6FET
95, N-channel MO8FET204, 211
are connected in common, and this common dart is further connected to a logic signal input point 99 to which a fourth logic input signal IN4 is applied.

That is, in this embodiment circuit, the logic signal output point 9
1 and the ground voltage VSS application point, there are four N-channel MO8FETs 101~104, 111~
Two series circuits 100 configured by connecting 114 in series
, 110 are inserted in parallel. Furthermore, each of the four MOSFETs 101 to 100 in the two series circuits 100 and 110
The gates 104, 111 to 1140 are connected to different ones of the four logic signal input points 96 to 99. Furthermore, MOSFET 10 in one series circuit 100
The logic signal input point 96 to which dart No. 1 is connected is
4 MOSFETs J 2 in the other series circuit 110
Among the MO8FETs 1 to 114, the MO8FET 101 is also located at a position relatively far from the logic signal output point 91.
Dart of OSFET JJ4 is connected. Similarly, MOSFET 102 in one series circuit 100
The four MO8FETs 111 to 1 in the other series circuit 110 are connected to the logic signal input point 97 to which the dart is connected.
Among the MOSFETs 14, the MOSFETs 102 and 102 are also placed at a position relatively far from the logic signal output point 91.
ET 113 dart is connected. Similarly, the logic signal input point 98 to which the dart of MOSFET 103 in one series circuit 100 is connected also receives a logic signal from MOSFET 103 among the four MOSFETs 111 to 114 in the other series circuit 110. MOSFET J located relatively close to the output point 91
12 darts are connected. Similarly, the logic signal input point 99 to which the dart of MOSFET 104 in one series circuit 100 is connected is connected to the logic signal input point 99 of the other series circuit 110.
Among (04 pieces (7) MOSFETs 111 to 114, the above MO8FETs lθ4 and ρ are also placed at a position relatively close to the logic signal output point 91. MOSFET 11
The dart is connected.

In this embodiment circuit, for the same reason as mentioned above, no difference occurs in the switching speed and circuit threshold voltage, no matter which of the four logic signal input points 96 to 99 is used to operate the inverter. Either the difference can be made smaller, or the difference can be made smaller.

The embodiment circuit of FIG. 10 consists of the two series circuits 100.
The dart connections of the four N-channel MOSFETs 101 to 104 and 111 to 114 provided in each of the four N-channel MOSFETs 11'0 are different from those shown in FIG. On the N-channel side of this example circuit, a MOSFE
Each dart of T 101 and 112 is connected to the logic signal input point 9.
6, each gate of MOSFETs 102 and 111 is connected to the logic signal input point 97, each gate of MOSFETs 103 and 114 is connected to the logic signal input point 98,
Each dart 104 and 113 corresponds to the logic signal input point 99.
are connected to each.

In the embodiment circuit of FIG. 11, the two series circuits 100
, 110, the dart connections of the four N-channel MOSFETs 101-104 and 111-114 are further different from those in FIGS. 9 and 10, respectively. On the N-channel side of this example circuit, MOSFETs 101 and 113
are connected to the logic signal input point 96 by a MOSFE
Each dart of T102 and 112 is connected to the logic signal input point 97.
Each dart of MOSFETs I03 and 111 is connected to the logic signal input point 98, and each dart of MOSFETs 104 and 114 is connected to the logic signal input point 99, respectively.

In the example circuit shown in FIGS. 12 and 13, in a four-person NAND gate, logic signal output point 9 and VS
Another series circuit 12θ is inserted in parallel between the S application point and this series circuit 120.
are four N-channel MOSFETs connected in series 12
It consists of numbers 1 to 124. Furthermore, in the embodiment circuit of FIG. 13, the N-channel side MOSFETs 101 to 10
The dart connections of 4°111 to 114 and 121 to 124 are different from those shown in FIG.

By the way, the circuit configuration as shown in FIG. 2(a) above,
When integrating the conventional three-man-powered CMO8, NANI) dart into one stack, each of the MOSFETs 15 to 17 is configured by aggregating several small-sized elements. This is because when MOSFETs are formed using the silicon dirt process, as the device size increases, the length of the dirt wiring layer becomes longer and its resistance component increases. This is because the impact on the environment cannot be ignored. Therefore, conventionally, the three Ns connected in series in the circuit shown in FIG.
The channel MOSFETs 25 to 17 are, for example, the 14th
As shown in the figure, two MOSFETs J5A, 1 are connected in series between the logic signal output point 11 and the VSS application point and each have a channel width of a difference of MOSFET 15.
5B and two each MO8FETJ6A, 16 each with a channel width of y2 of MOSFET 16
B, and two MO8FETs f 7 A and 17 B each having a channel width equal to that of MOSFET 17. In addition, MOSFET I5 +, 25A + 15
B, 16, J6A.

It is assumed that the channel lengths of 16B, 17.17, and 17B are all equal.

FIG. 15 is a pattern plan view when the circuit shown in FIG. 14 is actually integrated. In the figure, 200 is a P-type well region formed on an N-type semiconductor substrate. On this well region 200, a plurality of N+
+ In the semiconductor region 201, 201B, . . . , 201G are arranged in a line. Among these, one N++ semiconductor region 20IA located at the uppermost position in the figure is
This is the source region of MOSFET 17A in FIG. 14. One N++ semiconductor region 201B located adjacent to the region 201 is M in FIG.
Drain of OSFET 17 A and MOSFET
This is the source region of f 6 A. Above area 201
One N+ type hot conductor region 201C arranged adjacent to BK serves as the drain of MOSFET 16A and the source region of MOSFET 15A in FIG. One N+m semiconductor region 201D located adjacent to the region 201C serves as the drain region of MOSFETs 15A and 15B in FIG. 14. One N++ semiconductor region 201E located adjacent to the region 201DK is connected to the MOSFET 15 BO source and MOSFET in FIG.
16 B drain region. Above area 2θ
One resistant semiconductor region 201F placed in instantaneous contact with the IE serves as the source of MOSFET 16B and the drain region of MOSFET 17B in FIG. Furthermore, 1 i, ? is arranged in contact with the area 201F and is located at the lowest position in the figure. N+ at i location
+The semiconductor region 201G is the MOSFET in FIG.
17B source area.

In addition, the N++ semiconductor regions 201A to 201G in the above seven locations
On the lower surface between each two of them, there is a layer made of polycrystalline silicon.

- interconnection layers 202A to 202F are formed respectively.

Further, on the surface of the well region 200, five wiring layers 203A to 203E made of aluminum are arranged in parallel along the arrangement direction of the N+ type thick conductor region 201 via an insulating film (not shown). has been done. The third logic input signal IN3 is transmitted to one wiring layer 203.1 among them, and the two dirt wiring layers 202A and 202F are connected to the contact hole 204 in this wiring layer 203A via 204B. It is connected. Above 1
The second logic input signal IN' is in the main wiring layer 203B.
is transmitted, and a contact hole 205k is formed in this wiring layer 203B.

The two dirt wiring layers 202B via 205B.

202E is connected. One wiring layer 203C above
The first logic input signal INJ is transmitted to the wiring layer 2θ3C, and the contact hole 206 is connected to the wiring layer 2θ3C.
The two dirt wiring layers 2o2C and 2o2D are connected via. Furthermore, the ground voltage VS8 is supplied to the one wiring layer 203D, and the two
N++ semiconductor region 201k at the location.

201G is connected. In addition, the one wiring layer 20
3E is for guiding the logic output signal OUT to the logic signal output point 11, and this wiring layer 203E is connected to the N++ semiconductor region 20 through a contact hole 208.
1D is connected.

FIG. 16 is an enlarged sectional view taken along the line x-x' in FIG. 15. Go to Figure 16 and 209 is f of MOSFET.
- It is a silicon oxide film that also serves as an insulating film.

As shown in FIG. 15 or 16, among the arrays of the N++ semiconductor regions 20, wiring f3203. Centering on one area 201D connected to D, this area 2
01D and two areas 201 located on both sides of this
Of the three dirt wiring layers 2021 to 202C and 202D to 202F existing between each of the two dirt wiring layers 201G and 201G, two dirt wiring layers are arranged at positions corresponding to each other with the region 201D as the center. 202A and 202F
are supplied with the signal INJ transmitted through the wiring layer 203A, and are similarly arranged at corresponding positions with the area 201D as the center (two dirt wirings). The signal IN2 transmitted by the wiring layer 203B is supplied to i202B and 202E, and the two dirt wiring layers 202C are similarly arranged at corresponding positions with the region 203D as the center.
and 202D have a signal INI transmitted through the wiring layer 203C.
is supplied.

Under such a premise, in order to construct the circuit according to the embodiment of the present invention shown in FIG. 5, one of the series circuits 18 in the circuit shown in FIG.
Signal IN1. is applied to darts 5A', 26A, and 17A.
IN2. This can be realized by supplying INJ to each and reversing the dart connections of MOSFETs 15B and 17B in the other series circuit 18B. FIG. 17 is a nozzle/plan view corresponding to FIG. 15 when the embodiment circuit of FIG. 5 is realized in this manner. That is, the difference between FIG. 17 and FIG. 15 is that the dirt wiring layer 2
02D is connected to the wiring layer 203C through a contact hole 204C, and the bracket wiring layer 202F is connected to the wiring layer 203k through a contact hole 206C. The wiring layer 203C is connected to the wiring layer 203C. That is, in the case shown in FIG. 17, the wiring layer 203F.

N+ type semiconductor region 201D and region 20 connected to
Three dirt wiring layers between 1 and 202A~
202C as the logic input signal IN3.

Three wiring layers 203A to which IN2 and INl are transmitted
The three dirt wiring layers 202D-202F existing between the region 201D and the region 201Cz are connected to different wiring layers 203C to each other among the three wiring layers 203C. I try to connect to different things.

Moreover, 3 that exists between the areas 201D and 201
One wiring layer 20 in which one dirt wiring layer 202k of ~202C is connected to the main dirt wiring layer 202.
3A, among the three dirt wiring layers 202D to 202F existing between the regions 201D and 201G, the dirt wiring layer 202 is also located at a position relatively close to the region 201D. The layers 202D are connected through contact holes 204C. Further, similarly, one wiring layer 20 to which one dirt wiring layer 202C among the three dirt wiring layers 202A to 202C existing between the area 201D and the area 201 is connected.
3C, among the three dirt wiring layers 202D to 202F existing between the region 201D and 2θIG, a dirt wiring layer 202F is located at a position relatively far from the region 201D compared to the dirt wiring layer 202C. are connected through contact holes 206C.

In this way, the embodiment circuit shown in FIG. 5 can be realized by only slightly changing the wiring with respect to the conventional pattern, and there is almost no increase in area.

FIG. 18 is a plan view of the N-channel side when this invention is extended to an n-input 0MO8NAND circuit and the circuit is integrated. In this case, two series circuits each configured by connecting n N-channel MO8FETs in series are inserted in parallel between the logic signal output point and the VSS application point. 30 in Figure 18
0 is the well area of the P bottle, 301, 301. . . . is an N+ type semiconductor region arranged in a − column, 302°30
2, . . . are dirt wiring layers formed between the two N+ type semiconductor regions 301 and made of polycrystalline silicon, and 303, 303 .・
. . are wiring layers made of aluminum that transmit the input signals INI to INn, the voltage VSB, or the logic signal OUT. And each of these wiring layers 30
3° 303, . . . are connected to the dirt wiring layer 302 or the N+ type semiconductor region 3 through the contact hole 304.
01. Also in the case of the tree / in FIG. 18, there is one N+ type semiconductor region 301 connected via a contact hole 304 to one wiring layer 303 from which the logic input signal OUT is obtained, and this region 301 n dirt wiring layers 302 existing between each of two N+ type semiconductor regions 301 and 301 arranged on both sides of the circuit and connected to one wiring layer 303 through which the voltage V8B is transmitted. are respectively connected to different wiring layers among the n wiring layers to which the n logic input signals INJ to INn are transmitted. Moreover, to the wiring layer 303 to which at least two of the n dirt wiring mfeso2 are connected, the two of the n gate wiring layers 302 of the other n are also connected. Two gate wiring layers 302 disposed relatively close to or relatively far from one N+ type semiconductor region 301 connected to a wiring layer 303 through which a signal OUT is transmitted are connected to each other. There is. This first
If an n-input logic circuit is configured using a pattern as shown in FIG. 8, it can be realized by only slightly changing the wiring compared to the conventional pattern, and there is no increase in area.

〔Effect of the invention〕

As explained above, according to the present invention, there are n logic input points (n is an integer of 3 or more), and even if any logic input point is used to operate the inverter, the switching speed and circuit It is possible to provide a logic circuit in which there is no difference in threshold voltage, or even if there is a difference, the difference is small.

[Brief explanation of the drawing]

Figures 1 (a) and (b) are symbol diagrams of a three-man powered NAND dart and NOR gate, Figure 2 (a),
(b) is a circuit diagram of each dart in FIGS. 1(a) and (b), and FIGS. 3(a) and (b). (C) is a simple diagram showing different usage examples of the three-person NAND gate shown in Fig. 1 (,), and Fig. 4 (a), (
b), (e) are shown in Figure 3 (a), (b), (
An equivalent circuit diagram corresponding to C), FIG. 5 is a circuit diagram showing an embodiment of the present invention, and FIG. 6 (a), (b)', (
C) is an equivalent circuit diagram of the circuit in FIG. 5, FIGS. 7 to 13 are circuit diagrams showing other embodiments of the present invention, and FIG.
The figure is a circuit diagram when the conventional circuit shown in Fig. 2 (-) is integrated, Fig. 15 is a pattern plan view of the circuit shown in Fig. 14, and Fig. 1
Figure 6 is an enlarged sectional view taken along the line x-x' in Figure 15;
FIG. 17 is a +turn plan view on the N channel side when integrating the circuit according to the embodiment of the present invention shown in FIG. FIG. 31.61.91...Logic signal output point, 35-37.
65-67.96-99...Logic signal input point, 40,
50, 70, 80, 100, 110° 120...Series circuit, 32~J4.71~73°81~83.92~9
5...P channel MO8FET. 41-43.51-53.62-64, 102-104
．． 111-114, 121-124...N channel M
O8FET 0 Applicant's agent Patent attorney Takehiko Suzue 1st (a) 2nd (a) 5S (b) ■DD ss ← p -th> ぢ, 9 -N Bargu ZZZZZ z 44 t- -d 09 faction zzzzzz z 4 L `` Dimensions 17th IN3 1N2 INI Vss ou'r 200 18th 30υ 125 )-

Claims (2)

[Claims] (1) Each n MOSF (n is an integer of 3 or more)
2 or n-1) series circuits configured by connecting ETs in series and inserted in parallel between a logic signal output point and a predetermined potential application point, and n series circuits to which n input signals are applied. Connect the logic signal input point and the darts of each of the n MOSFETs connected in series in the above 2 to n-1) series circuits to mutually different logic signal input points of the above n logic signal input points. At the same time, the above 2 to n-1)
n M connected in series in one specific series circuit
The two logic signal input points to which at least two specific darts of the OSFETs are connected are connected in series in one specific series circuit different from the above 2 or n-1). Of the n connected MOSFETs, each of the two MOSFETs located at a position relatively closer to or farther from the logic signal output point than the specific two MO8FETs. - means for connecting the gates. (2) One conductive type semiconductor substrate, and the other conductive plastic semiconductor regions formed at multiple locations on the substrate so as to be separated from each other and arranged in series in a predetermined direction and serve as the source region or drain region of the MOSFET. and a plurality of semiconductor regions formed so as to extend on the surface of the substrate between two semiconductor regions arranged adjacent to each other among the plurality of semiconductor regions, a part of which becomes the r-) electrode of the MOSFET. and a specific one of the semiconductor regions at the plurality of locations.
connected to a first semiconductor region disposed at the first semiconductor region;
A second wiring layer for transmitting the logic output signal obtained in the semiconductor region, and a second wiring layer arranged on both sides of the first semiconductor region (1) and a specific wiring layer different from the first semiconductor region in the plurality of semiconductor regions. a third wiring layer that is commonly connected to the second and third semiconductor regions at two locations and supplies a predetermined potential to the second and third semiconductor regions; A fourth wiring layer, n pieces of the first wiring layer existing between the first and second semiconductor regions, and n pieces of the first wiring layer existing between the first and third semiconductor regions. interconnection layers to mutually different interconnection layers of the n fourth interconnection layers, and connect at least a specific one of the n first interconnection layers existing between the first and second semiconductor regions. The specific two respective first wirings of the n first wiring layers existing between the first and third semiconductor regions in the two fourth wiring layers to which the two are connected. A logic device characterized in that the layer is also provided with a connection portion for connecting two first wiring layers each disposed at a position relatively close to or relatively far from the first semiconductor region. circuit.