JPS60256864A - Data transfer device - Google Patents

Abstract

PURPOSE:To attain the bucket transfer between optional processors by using a transfer device for connection between devices to realize a bucket transfer element and distributing the transfer device and processors in a 2-dimensional form. CONSTITUTION:When an input buffer part 10 supplies a bucket from an input port 101, an output signal 110 is delivered. A decoding circuit 13 decides an output port 104 or 105 according to the bit position designated from a bit string of a signal 110 by an output designated position signal 107. Then a request signal 111 or 112 to a controller 19 or 20. A detection circuit 16 supplies the signal 110 and detects a bit string designated by a specific output address designating signal 108 for execution of transfer control. The controller 19 selects one of request signals 111, 121 and 131 sent from circuits 13-15 in order of early arrival and delivers a transfer designating signal 135 to an output buffer part 25. Furthermore, either one of output signals 110, 120 and 130 of an input buffer is selected by a multiplexer 22. The part 25 supplies an output signal 140 of the multiplexer 22 and transmits the bucket to the port 104 by the signal 135.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transfer device that transfers a plurality of packets.

(Prior Art and its Problems) In recent years, with the development of LSI, multiprocessor systems that aim to improve performance by using a large number of processors to share and process large tasks have become popular. In a multiprocessor system, processing is performed while data is exchanged between a plurality of processors, so the method of data transfer between processors has a large effect on performance. Conventional methods include a crossbar switch method and a multistage network method. The crossbar switch method is
Although it has high performance because any input can be connected to any output, the number of circuit elements increases on the order of N2 relative to the number of processors (N), resulting in high costs. In addition, the multi-stage network method uses the aforementioned crossbar.
It connects small input switches (mostly 2 manpower x 2 outputs) in multiple stages, and although the performance is equivalent to the crossbar switch method and the cost is on the order of N1ogN, it still has the disadvantage of being expensive. .

(Object of the Invention) An object of the present invention is to provide a data transfer device that eliminates the above drawbacks and allows a plurality of processors to communicate efficiently.

(Structure of the Invention) According to the present invention, a packet consisting of a plurality of bit strings is input to two input ports and one specific input port, and two output ports and one specific output are input depending on some bit strings included in the packet. A device that sends a packet to one of the boats, and includes an input buffer section that inputs and temporarily stores the packet to each of two input ports and a specific input boat, and a bit string stored in the input buffer section. A decoding circuit extracts one bit from a preset position and selects one of two output ports, and a decoding circuit extracts one bit from a preset position and selects one of two output ports. A detection circuit that disables the selection and selects a specific output port, and a detection circuit that is arranged corresponding to each of the output port and the specific output port, and that outputs one of the plurality of selection signals coming from the plurality of decoding circuits or detection circuits in advance. An arbiter that selects according to set conditions, a multiplexer that takes out one packet from one input buffer section among a plurality of input buffer sections corresponding to one selection signal selected by the arbiter, and a multiplexer. The output buffer section includes an output buffer section for temporarily storing packets output from the output port, and an output buffer section for transmitting the packets to the corresponding output port.

Furthermore, according to the present invention, a plurality of transfer devices 100 are arranged in each row 2.
The fifth column of each of the first to Nth columns is 2(2) of 2j transfer devices 100.
Divide into groups 1 to 2 (J-
The transfer devices 100 numbered 1) connect their respective first output ports to the respective first output ports of the transfer devices 100 numbered 1 to 1-1) of the corresponding destination set in the (J+1)th column. Connect the output port of text box 2 to the first input port of each transfer device 100 numbered from (2'''+1) to number 2j of the corresponding destination group, and The transfer devices 100 numbered from (2")+1') to number 21 transfer their respective first output ports to number 1' and number 2 (J-+) of the corresponding partner pair. Device 1
00 to each second input port, and each second output port to the corresponding pair of destinations (2J+I+t
) to the second input port of each of the transfer devices numbered 2j, and if J is the final column N, connect the first column as the destination group, and Connect a processor to each specific input port and specific output port, go to the bit string that specifies each specific output, and if it is in the column position, (K-1), , (L-
1) corresponds to a bit string expressed in binary, and the output port is specified by specifying the bit position corresponding to each column number.

(Detailed Description of Configuration) According to the present invention, a transfer device realizes an element that connects devices and transfers packets, and by arranging transfer devices and processors in a two-dimensional manner, it is possible to connect arbitrary processors. A data transfer device capable of packet transfer can be provided.

(Embodiment) FIG. 1 is a block diagram showing a first embodiment of the present invention.

101.102. is an input port, 103 is a specific input port, 104 and 105 are output ports, 106 is a specific output port, and 107 is an output position designation signal to set the bit position that specifies the output port, or 108 is a specific output port. This is a specific output addressing signal for setting a bit string.

10.11.12 is the input buffer section, 13, 14.15
is a decoding circuit 16, 17, 18 is a detection circuit, 19, 2
0.21 is an arbitrator, 22, 23, and 24 are multiplexers, and 25', 26, and 27 are output buffer sections.

When the input buffer unit 10 receives a packet from the input port 101, it outputs an output signal 110. The decoding circuit 13 outputs an output position designation signal 107 from the bit string of the output signal 110.
Output port 104 or 105 is determined based on the bit position specified by , and either request signal 111 or 112 is output to arbiter 19 or 20. For example, when the data at the designated bit position is "0", the request signal 111 is output, and when it is "1", the request signal 112 is output.The detection circuit 16 receives the output signal 110 and outputs the specific output address designation signal. The bit string designated by 108 is detected. If the bit string matches the specific output address designation signal 108, an invalidation signal 113 is sent to the decoding circuit 13, invalidating the packet transfer to the output port 104 or 105. 21 to request packet transfer to the specific output port 106.The arbitrator 19 sends request signals 111 and 4 to the decoding circuits 13, 14, and 15, respectively, to request packet transfer to the specific output port 106.
121 and 131, select one in a first-come, first-served manner, output a transfer designation signal 135 to the output buffer section 25, and further send the multiplexer 22 to select one of the output signals 110, 120, and 130 of the input buffer. A selection designation signal 132 is issued. The output buffer section 25 inputs the output signal 140 of the multiplexer 22 and outputs the transfer designation signal 1.
35, the packet is sent to the output boat 104. Although the current explanation has shown the case of transfer to the input port 101 and output port 104, the same applies to other ports.

FIG. 2 is a block diagram showing an example of the configuration of the input buffer unit 10 shown in FIG. 1, in which the shift register 20 is a controller. Data input signal 20 of input port 101
1 and sequentially input packets to the shift register 20. When the controller 21 receives the input request signal 202, it returns an approval signal 203 and outputs an input command signal 204 to the shift register 20.

FIG. 3 is a block diagram showing an example of the configuration of the decoding circuit 13 shown in FIG. 1, where 31 is a multiplexer 32 and 33 is a gate circuit. When the output signal 110 is input, the multiplexer 31 extracts the bit output signal 301 from the bit position specified by the output position designation signal 107. Gate circuit 32
When the bit output signal 301 is "0" and there is no invalidation signal 113, the gate circuit 32 outputs the request signal 111, and when the bit output signal 301 is "1", the gate circuit 33 outputs the request signal 112.

FIG. 4 is a block diagram showing an example of the configuration of the detection circuit 16 shown in FIG. 1, where 41 is a multiplexer and 42 is a comparator. When the output signal 110 is input, the multiplexer 41 takes out the partial pit string 401 specified by the specific output address designation signal 108. The comparator 42 outputs an invalidation signal 113 and a request signal 114 when the specific output address designation signal 108 and the partial bit string 401 match.

FIG. 5 is a block diagram showing a configuration example of the arbiter 19 shown in FIG. 1. 51 is a priority encoder which inputs request signals 111, 121, and 131, selects the earliest one, outputs an address signal 132 corresponding to the selected request, and outputs a transfer command signal 135.

FIG. 6 is a block diagram showing a configuration example of the multiplexer 22 shown in FIG. 1. 61 is a multiplexer that inputs output signals 110, 120, and 130, and outputs address signal 1.
One of the outputs designated by 32 is selected and an output signal 140 is output.

FIG. 7 is a block diagram showing an example of the configuration of the output buffer section 25 shown in FIG. 1. 71 is a shift register, and 72 is a controller. Controller 72 transfers command signal 1
31 is received, the set designation signal 7 is sent to the shift register 71.
04 and sets the output signal 140 to the shift register, then outputs the output request signal 702 to the output port 104, and when the approval signal 703 comes, outputs the shift designation signal 705 and sends out the packet from the data output cuff 01.

FIG. 8 is a block diagram showing a second embodiment of the present invention. 1 row of 2N transfer devices 100 shown in FIG.
Arrange in a dimension. Inside the broken line are one set in the fifth example and the corresponding set in the (Jl1) column that is its counterpart. 5th column 1.2. . . . the first output port of each 2(J-1)th transfer device 100 in column (Jl1). ...The output port of sentence box 2 is connected to the 2nd (J-1)th first input port of the (Jli) column.
”)+1, . . . connect to the first input port of No. 2J. (2('-0+1), (2(J-
1) +2), -... The first output port of the transfer device 100 numbered 2J is the second input port of the transfer device 100 numbered 1,2゜2 (J-1) in the (Jl1) column or The second output port is (2''+1), (2-''+2).

. . . connect to the second input port of 21. Pl.

PP, PP,...P, P l, Jl1. JlII, Nl2N, I2N, J2N, J
lIl...P2NN are processors connected to a specific input port and a specific output port of each transfer device 100.

FIG. 9 is a diagram showing an example of a packet used in the second example of the present invention. 90 is a packet format, and field 91 is a field for specifying the position in the row direction and is composed of N bits.

1.2... Nth bit of each transfer device 1o.

The bit strings in the following fields 92N+1 to N+(1ogN)+1 are designated as selections in the column direction. Fields 91 and 92 are used together to select a specific output port for each transfer device. In this way, all processors p,
pp, . . . PIIIN, 12N, N can be specified as separate addresses and packets can be sent from any location.

For example, for the transfer device 100 located at the row-th position, the binary representation log(L-1) of (L-1) is output so that the bit position of the field 91 is specified. It is given as a position designation signal 107.

Furthermore, in order to specify a specific output, for field 91, the bit string log(K-1
) and field 92 (L-''), log(L-1) which is the binary representation of .log(L-1).

log(K-1) is provided as a bit string of the specific output addressing signal 108.

FIG. 10 is a diagram for more specifically explaining the second embodiment of the present invention, and is a block diagram showing an embodiment in the case of 4 rows and 2 columns. T, 1T,, -'T48. ．． ...frost...is the transfer device 100, P, 1P,...P4□,
P21...P4□ each indicate a processor. 1 shows a route when sending a packet 1000 to a processor P3□ (processor P212>"). The packet 1000 is sent to the
．． The 3rd bit position is 110” (in the figure, the 1st bit is on the far right)
It becomes.

As shown in FIG. 10, the transfer device frost is located in the first row.

T21, T(1, T41 output position designation signal 107 is given log(1-1)="0", and the second column transfer device'
Log(21)""12 is given to the output position designation signal 107 of I'll, T2□1T321T4□. Also, transfer devices TII+T2□, T3□, T41, 'r, □.

The specific output addressing signals 108 of T2□, T3□, and T4□ have 0.00' and "0.01", respectively.
:'0.10'.

"0.11", "1.00',"1.01', 1.10
', gives "1.11".

Therefore, for data transfer to processor P32, "1.10
' will be specified.

In this example, packet 10 issued from processor P21
00 is processed as follows. That is, the transfer device T21 is piped in the first column and the output position designation is "0", so it looks at the first bit, and since it is 0, it transfers it to the transfer device T12.Similarly, the transfer device Since T12 is placed in the second column and the output position designation is 61'', the second bit of packet 1000 is looked at, and since it is "1", it is transferred to the transfer device. Transfer device T3. is the first
Since it is the column, the first bucket of 1000 is the same as T21.
Looking at the bit, it is "0", so transfer device T3
Transfer to □. Since the specific output address designation signal of the transfer device T32 is "1.10", which matches the designation of the bucket) 1000, the transfer device T32 does not transfer it to the output port, but transfers it to the processor P3□ of the specific output port.

As can be seen from the above explanation, the packet 1000 output from the processor P21 is transferred to the transfer device T21=T12=T31=T'
It shows that the data is transmitted to the processor P3□ via az. Similarly, when transmitting data from another processor to processor P3□, the direction of data transfer is automatically determined by looking at the relationship between the location of the transfer device and the bit position of the packet.The data is then transferred to the target processor. I can do it.

If there is a third column, the output position designation signal given to each column is "00'" for the first column and "01" for the second column.
, the third column is specified as 10'', the first column 11 is the first bit of the packet, the second column (j is the second bit of the packet, and the third column 1j is the packet's first bit). You will see the third bit.

It goes without saying that, as another embodiment, if the transfer device 100 is integrated into one chip, a more effective transfer device can be realized.

(Effects of the Invention) According to the data transfer device of the first embodiment of the present invention, a packet is inputted from two input ports and a specific input port, and a part of the pit row of the packet is transferred to two output ports or Since packets can be transferred to one specific output port, the components of a highly versatile data transfer device that has a two-man power, two-output packet transfer means and a packet transfer means between a specific input and output port are required. Realized.

Furthermore, according to the data transfer device of the second embodiment of the present invention, by using the same number of transfer devices as the number of processors (N), it is possible to transfer packets between arbitrary processors,
Furthermore, a data transfer device is realized which has the characteristics that the number of stages of the transfer device passing through to reach the destination processor is small, and the scale and cost are small.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure shows the input buffer section 10°iJ3 shown in FIG. 1, the decoding circuit 13 in FIG. 4, the detection circuit 16 in FIG. 5, the arbitrator 19 in FIG. Block diagram showing each configuration example, No. 8
The figure is a programming diagram to show an embodiment of the data transfer device of the present invention, Figure 9 is a packet format), glO
The figure is a diagram for explaining the second embodiment of the present invention in more detail, and is a block diagram showing an embodiment with 4 rows and 2 columns. In the figure, 100 is a transfer device, 10, 11.12 is an input buffer section, 13, 14.15 is a decoding circuit, 16, 17.18
is a detection circuit, 19.20.21 is an arbitrator, 22.23°24.41.61 is a multiplexer, 25.26.27
is the output buffer section, 20.71 is the shift register, 21
．． 72 is a controller, 32.33 is a gate circuit, 42
is a comparator, 51 is a priority encoder, pHPIJ
ePl, J+8. -'IN, P2N,!・-・P2N,
N is the processor, TIIT21...T,,T,□...
・T4 and 2 indicate transfer devices, respectively. Figure 1 Figure 2 11:3 ffi3 Figure 11+ Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9... (!11

Claims (2)

[Claims] (1) A packet consisting of multiple bit strings is input to two input ports and one specific input port, and some bit strings included in the packet are input to two output ports and one specific output port. a transfer device that sends the packet to any one of the input ports, the input buffer unit inputting the packet to each of the two input ports and the specific input port and temporarily storing the packet; a decoding circuit that extracts one bit of the stored bit string from a preset position and outputs a selection signal for selecting one of the two output ports; a detection circuit that disables the selection of the decoding circuit and selects the specific output port when the bit string matches a set bit string; and a detection circuit that selects the specific output port when the bit string matches a set bit string; a multiplexer for extracting one packet from one of the plurality of input buffer units corresponding to the one selection signal selected by the arbitrator;
A data transfer device comprising: an output buffer section for temporarily storing packets output from the multiplexer and transmitting the packets to the corresponding output port. (2) Input a packet consisting of multiple bit strings from two input ports and one specific input port, and select one of the two output ports or one specific output port depending on some bit strings included in the packet. a transfer device that sends the packet to one input port, the input buffer unit inputting and temporarily storing the packet to each of the two input ports and the specific input port, and the bit string stored in the input buffer unit; Extract one bit from a preset position of one of the two output ports.
a detection circuit that selects the specific output port by invalidating the selection of the decoding circuit when a part of the bit string of the stored bit string matches a preset bit string; an arbiter disposed corresponding to each of the ports and the specific output port, which selects one of the plurality of selection signals coming from the plurality of decoding circuits or the detection circuit according to preset conditions; , a multiplexer that takes out one packet from one of the input buffer units among the plurality of input buffer units corresponding to the one selection signal selected by the arbitrator, and a multiplexer that temporarily stores the packet output from the multiplexer. The transfer devices each having an output buffer section for transmitting a packet from the corresponding output port are arranged in a two-dimensional form with 2N rows and N columns in each fifth column of the first to Nth columns. is divided into 2 (N-J) groups of two transfer devices 100, and the transfer devices 100 from No. 1 to No. 2 (, r-+) in each group have their respective first output ports. First (J+1)
The first input port of each transfer device 100 from number 1 to number 2 (J-1) of the corresponding destination group in the column is connected, and the second output port is connected to the corresponding destination group. of(
2")+1) to 2j, and connects to the first input port of each of the transfer devices 100 from (2(J-1)+1) to 2 of the respective sets.
connects each first output port to numbers 1 to 2 (J-1) of the corresponding destination set O said transfer device 10
0 to each second input port, and also to each second input port of
The output port of (2(J+1
)+1) to the second input port of each of the transfer devices from number 2j, and when J is the last column N, the first
Connect the columns as a pair of destinations, connect processors to each specific capo, 1° port, and specific output port of each of the transfer devices 100, and input a bit string specifying each specific output. If the position is in the second column, (K-1) and (L-1') should correspond to the binary representation of the bit string, and the output port should be specified by specifying the bit position corresponding to the number of each column. 1. A data transfer device configured to perform packet transfer between arbitrary processors.